Intel IXF1104 Datasheet page 43

®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 3. SPI3 Interface Signal Descriptions (Sheet 5 of 8)
Signal Name
MPHY
PTPA
RDAT31
RDAT30
RDAT29
RDAT28
RDAT27
RDAT26
RDAT25
RDAT24
RDAT23
RDAT22
RDAT21
RDAT20
RDAT19
RDAT18
RDAT17
RDAT16
RDAT15
RDAT14
RDAT13
RDAT12
RDAT11
RDAT10
RDAT9
RDAT8
43
Ball
Type
Designator
SPHY
PTPA B11 Output
RDAT7_3 F24
RDAT6_3 G24
RDAT5_3 G23
RDAT4_3 G22
Output
RDAT3_3 G21
RDAT2_3 G20
RDAT1_3 G19
RDAT0_3 G18
RDAT7_2 E21
RDAT6_2 E22
RDAT5_2 D22
RDAT4_2 C22
Output
RDAT3_2 C21
RDAT2_2 C20
RDAT1_2 B22
RDAT0_2 B20
RDAT7_1 F18
RDAT6_1 E18
RDAT5_1 E17
RDAT4_1 F16
Output
RDAT3_1 E16
RDAT2_1 D16
RDAT1_1 C17
RDAT0_1 A17
Standard Description
Polled-PHY Transmit Packet Available.
PTPA allows the polling of the port selected
by the TADR address bus.
When High, PTPA indicates that the amount
of data in the TX FIFO is below the TX FIFO
High watermark. When the High watermark
is crossed, PTPA transitions Low to indicate
that the TX FIFO is almost full. It stays Low
until the amount data in the TX FIFO goes
back below the TX FIFO Low watermark. At
this point, PTPA transitions High to indicate
that the programmed number of bytes are
now available for data transfers.
3.3 V
LVTTL
NOTE: For more information, see
Table 132 "TX FIFO High
Watermark Ports 0 - 3 ($0x600 –
0x603)" on page 203
"TX FIFO Low Watermark Register
Ports 0 - 3 ($0x60A – 0x60D)" on
page 204.
The port reported by PTPA is updated on
the following rising edge of TFCLK after the
port address on TADR is sampled by the
PHY device.
PTPA is updated on the rising edge of
TFCLK.
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
3.3 V
LVTTL
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
3.3 V
LVTTL
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
Receive Data Bus.
RDAT carries payload data and in-band
addresses from the IXF1104 MAC.
3.3 V
LVTTL
Mode
32-bit Multi-PHY
4 x 8 Single-PHY
and Table 133
Bits
[31:24]
[7:0] for port 3
Bits
[23:16]
[7:0] for port 2
Bits
[15:8]
[7:0] for port 1
Datasheet
Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005