Datasheet - Intel IXF1104 Datasheet

Table 147. SPI3 Receive Configuration ($0x701) (Continued) (Sheet 4 of 4)
Bit Name
Rx_port_enable
9
Port 1
Rx_port_enable
8
Port 0
7 Rx_core_enable
6:1 IBA[5:0]
0 RERR_enable
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
Description
SPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
MPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
SPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
MPHY Mode:
0 = Disables the selected SPI3 RX port.
1 = Enables the selected SPI3 RX port.
SPHY Mode:
NA. Write as 1, ignore on Read.
MPHY Mode:
0 = Disables the RX SPI3 core.
1 = Enables the RX SPI3 core.
SPHY Mode:
NA. Write as 0, ignore on Read.
MPHY Mode:
Sets the 6-bit value appended to the 2-bit
address during the port address selection.
SPHY Mode/MPHY Mode:
Frames marked to be filtered (based on the
settings in the "RX Packet Filter Control ($
Port_Index + 0x19)") or frames above the
Frame Size (Addr: Port_Index + 0x0F)"
not dropped in the RX FIFO (see
Errored Frame Drop Enable
optionally indicated with an RERR when sent out
the SPI3 interface.
0 = Packets not indicated with RERR.
1 = Packets indicated with RERR.
1
Type
R/W
R/W
R/W
R/W
"Max
that are
"RX FIFO R/W
($0x59F)"can be
Default
0x1
0x1
0x1
0x00
0
218