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Intel
IXF1104 4-Port Gigabit Ethernet Media Access Controller
Table 5.
GMII Interface Signal Descriptions (Sheet 2 of 2)
Signal Name
RXD7_0
RXD6_0
RXD5_0
RXD4_0
RXD3_0
RXD2_0
RXD1_0
RXD0_0
RXD7_1
RXD6_1
RXD5_1
RXD4_1
RXD3_1
RXD2_1
RXD1_1
RXD0_1
RXD7_2
RXD6_2
RXD5_2
RXD4_2
RXD3_2
RXD2_2
RXD1_2
RXD0_2
RXD7_3
RXD6_3
RXD5_3
RXD4_3
RXD3_3
RXD2_3
RXD1_3
RXD0_3
RX_DV_0
RX_DV_1
RX_DV_2
RX_DV_3
RX_ER_0
RX_ER_1
RX_ER_2
RX_ER_3
CRS_0
CRS_1
CRS_2
CRS_3
RXC_0
RXC_1
RXC_2
RXC_3
NOTE: Refer to the RGMII interface for shared data and clock signals.
49
Ball Designator
Type
AC5
AB5
Y5
Y6
Y7
W7
V7
V8
Y10
AA11
AC11
AD10
W9
W11
Y11
Y9
Input
W20
V19
V20
W22
Y23
Y22
Y21
Y20
T19
T18
T17
T16
W18
Y19
Y18
Y17
V5
AB11
Input
Y24
V18
W5
Y12
Input
AA22
U20
AA5
AA9
Input
AB15
AC16
V4
AD11
Input
AA24
V23
Standard
Description
Receive Data:
Each bus carries eight data bits [7:0] of
the received data stream.
RGMII Mode: When a port ID is
configured in copper mode and the
RGMII interface is selected, only bits
2.5 V
RXD[3:0]_n are used to receive data.
CMOS
Fiber Mode: The following signals
have multiplexed functions when a port
is configured in fiber mode:
RXD4_n: MOD_DEF_0:3
RXD5_n: TX_FAULT_0:3
RXD6_n: RX_LOS_0:3
Receive Data Valid.
2.5 V
RX_DV indicates that valid data is
CMOS
being driven on Receive Data:
RXD[7:0]_n.
Receive Error.
2.5 V
RX_ER indicates an error in Receive
CMOS
Data: RXD[7:0]_n.
Carrier Sense.
2.5 V
CRS indicates the PHY device has
CMOS
detected a carrier.
Receiver Reference Clock.
RXC operates at:
2.5 V
125 MHz for 1 Gigabit
CMOS
NOTE: Shares the same balls as RXC
on the RGMII interface.
Document Number: 278757
Revision Date: 27-Oct-2005
Datasheet
Revision Number: 009
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