Fc Enable ($ Port_Index + 0X12); Fc Back Pressure Length ($ Port_Index + 0X13); Datasheet - Intel IXF1104 Datasheet

Table 84. FC Enable ($ Port_Index + 0x12)
Bit Name
Register Description: Indicates which flow control mode is used for the RX and TX MAC.
31:3 Reserved
2 TX HDFC
1 TX FDFC
0 RX FDFC
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write
Table 85. FC Back Pressure Length ($ Port_Index + 0x13)
Name
FC Back Pressure
Length
1. RO = Read Only, No clear on Read; R = Read, Clear on Read; W = Write only; R/W = Read/Write, No
clear; R/W/C = Read/Write, Clear on Write

Datasheet

Document Number: 278757
Revision Number: 009
Revision Date: 27-Oct-2005
®
Intel IXF1104 4-Port Gigabit Ethernet Media Access Controller
Description
Reserved
When TX HDFC is enabled (half-duplex mode
only), the MAC generates deliberate collisions on
incoming packets when the RX FIFO occupancy
crosses the High Watermark (flow control).
0 = Disable TX half-duplex flow control
1 = Enable TX half-duplex flow control
0 = Disable TX full-duplex flow control [the MAC
will not generate internally any flow control
frames based on the RX FIFO watermarks or
the Transmit Pause Control interface
1 = Enable TX full-duplex flow control [enables
the MAC to send flow control frames to the
link partner based on the RX FIFO
programmable watermarks or the Transmit
Pause Control interface]
0 = Disable RX full-duplex flow control [the MAC
will not respond to flow control frames sent to
it by the link partner]
1 = Enable RX full-duplex flow control [MAC will
respond to flow control frames sent by the link
partner and will stop packet transmission for
the time specified in the flow control frame]
Description
This register sets number the byte cycles
for which the collision has to be applied.
The 6-bit configuration holds the value in
bytes, which applies to the minimum
length/duration of back pressure in half-
duplex mode. Flow control in the receive
path is executed by deliberately colliding
the incoming packets in half-duplex mode.
Register bits 5:0 are used alone.
1
Type Default
0x00000007
R 0x00000000
R/W 1
R/W 1
R/W 1
1
Address Type Default
Port Add +
R/W 0x0000000C
0x13
168