Chipset Features Setup; Sdram Ras-To-Cas Delay - TMC TI6NBF+ User Manual

440bx/440zx/apollo pro plus atx motherboard

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6.5 Chipset Features Setup

This Setup menu controls the configuration of the motherboard chipset.

SDRAM RAS-to-CAS Delay

SDRAM RAS Precharge Time

SDRAM CAS Latency Time

SDRAM Precharge Control

DRAM Integrity Mode

System BIOS Cacheable

Video BIOS Cacheable

Video RAM Cacheable

8 Bit I/O Recovery Time

16 Bit I/O Recovery Time

Memory Hole At 15MB-16MB

Passive Release

Delayed Transaction

AGP Aperture Size (MB)

Auto Detect DIMM/PCI Clk

Spread Spectrum

For Intel 440BX/440ZX chipset

Bank 0/1 DRAM Timing

: SDRAM 10ns

Bank 2/3 DRAM Timing

: SDRAM 10ns

Bank 4/5 DRAM Timing

: SDRAM 10ns

SDRAM Cycle Length

: 3

DRAM CLOCK

: Host CLK

Memory Hole

: Disabled

Read Around Write

: Disabled

Concurrent PCI/Host

: Enabled

Video RAM Cacheable

: 64M

AGP Aperture Size

Auto Detect DIMM/PCI Clk

: Disabled

Spread Spectrum

: Disabled

For VIA Apollo Pro Plus (82C693) chipset

SDRAM RAS-to-CAS Delay

When DRAM is refreshed, both rows and columns are addressed

separately. This field allows you to determine the timing of transition

from Row Address Strove (RAS) to Column Address Strobe (CAS). The

default setting is 3.

TI6NBF+ Pentium II /III ATX Motherboard User's Manual

Chapter 6 BIOS and System Setup

ROM PCI/ISA BIOS