Chipset Features Setup - TMC TI5VG+ User Manual

Chapter 6 BIOS Configuration

6.5 Chipset Features Setup

This Setup menu controls the configuration of the motherboard chipset.
Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing
SDRAM Cycle Length
SDRAM Bank Interleave
DRAM Read Pipeline
Sustained 3T Write
Cache Rd+CPU Wt Pipeline
Read Around write
Cache Timing
Video BIOS Cacheable
System BIOS Cacheable
Memory Hole At 15MB
AGP Aperture Size
CPU/PCI Clock Select
Auto Detect DIMM/PCI Clk
Spread Spectrum
Cyrix M2 ADS# delay
Bank DRAM Timing
These fields define the speed of the DRAM memory onboard. The
options are Normal, Medium, Fast, Turbo, 70ns and 60ns. By default,
these fields are set to 60ns.
SDRAM Cycle Length
This field sets the SDRAM cycle length to either 2 or 3. The default
setting is 3.
SDRAM Bank Interleave
This field enables or disables the SDRAM bank interleave. The default
setting is Disabled.
DRAM Read Pipeline
When enabled, this field supports pipelining of DRAM reads The default
setting is Enabled.
Sustained 3T Write
This field allows support for PBSRAM sustained 3T write. By default,
this field is set Enabled.
Cache Rd+CPU Wt Pipeline
When enabled, this item allows pipelining of cache reads and CPU
writes. The default setting is Enabled.
44
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
: 60ns OnChip USB
: 60ns USB Keyboard Support
: 60ns
: 3 CPU Warning Temperature
: Disabled Current System Temp
: Enabled Current CPU Temperature
: Enabled CPU FAN Speed
: Enabled CHASSIS FAN Speed
: Enabled VCORE :
: Fast VCC3 :
: Enabled +12 V :
: Disabled - 5V :
: Disabled
: 64M
: Default ESC : Quit
: Disabled F1 : Help
: Disabled F5 : Old Values
: Disabled F6 : Load BIOS Defaults
F7 : Load Setup Defaults
TI5VG+ User's Manual
: Enabled
: Disabled
: 70°C/158°F
:
:
:
:
VIO
+5 V :
-12 V :
: Select Item
PU/PD/+/- : Modify
(Shift) F2 : Color