Chipset Features Setup - TMC TI6NL User Manual

Chapter 6 BIOS Configuration

6.5 Chipset Features Setup

This Setup menu controls the configuration of the motherboard chipset.
Auto Configuration
DRAM Speed Selection
MA Wait State
DRAM Integrity Mode
CPU To PCI IDE Posting
System BIOS Cacheable
Video BIOS Cacheable
Video RAM Cacheable
8 Bit I/O Recovery Time
16 Bit I/O Recovery Time
Memory Hole At 15MB
Passive Release
Delayed Transaction
AGP Aperture Size (MB)
SDRAM RAS-to-CAS Delay
SDRAM RAS Precharge Time
SDRAM CAS Latency Time
Auto Configuration
This field predefined values for DRAM, cache timing according to CPU
type and system clock. When this field is enabled, the predefined items
will become read-only.
DRAM Cycle Speed Selection
This field sets the DRAM cycle speed. The options are 60ns and 70ns. By
default, this field is set to 60ns.
MA Wait State
This field sets the wait state of the memory address. The settings are Fast
and Slow. By default, this field is set to Slow.
CPU to PCI IDE Posting
When enabled, the CPU to PCI IDE posting cycles are treated as normal
I/O write transactions. The default setting is Enabled.
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is
disabled.
38
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
: Enabled
CPU Warning Temperature
: 60ns
: Slow
Current CPU Block Temp.
Non-ECC Current CPU/Chips Block Temp. : 27°C/ 80°F
Enabled Current System Temp.
: Enabled
Current Chassis Fan Speed
: Enabled
Current CPU Fan Speed
: Disabled
: 4 VCCP (V): 1.98 V
: 3 VCC3 (V) : 3.45 V
: Disabled +12 V : 12.46 V
: Enabled -5V : - 5.21 V
: Disabled
: 64
: Slow
: Slow
3 ESC : Quit
F1 : Help
F5 : Old Values
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
TI6NL User's Manual
: 66°C/151°F
: 41°C/ 105°F
: 34°C/ 93°F
: 2789 RPM
: 2045 RPM
VTT (V) : 1.50 V
+ 5 V : 4.99 V
-12 V : -12.54V
: Select Item
PU/PD/+/- : Modify
(Shift) F2 : Color