Chipset Features Setup - TMC TI5VGF User Manual

Chapter 6 BIOS Configuration

6.5 Chipset Features Setup

This Setup menu controls the configuration of the motherboard chipset.
Bank 0/1 DRAM Timing
Bank 2/3 DRAM Timing
Bank 4/5 DRAM Timing
SDRAM Cycle Length
Sustained 3T Write
DRAM Read Pipeline
Cache Rd+CPU Wt Pipeline
Cache Timing
Video BIOS Cacheable
System BIOS Cacheable
Memory Hole At 15MB
AGP Aperture Size
CPU/PCI Clock Select
Auto Detect DIMM/PCI Clk
Spread Spectrum
Cyrix M2 ADS# delay
Bank DRAM Timing
These fields define the speed of the DRAM memory onboard. By default,
these fields are set to SDRAM 8ns.
SDRAM Cycle Length
This field sets the SDRAM cycle length to either 2 or 3. The default
setting is 3.
Sustained 3T Write
This field allows support for PBSRAM sustained 3T write. By default,
this field is set Enabled.
DRAM Read Pipeline
When enabled, this field supports pipelining of DRAM reads The default
setting is Enabled.
Cache Rd+CPU Wt Pipeline
When enabled, this item allows pipelining of cache reads and CPU
writes. The default setting is Enabled.
44 TI5VGF Pentium MVP3 ATX Motherboard User's Manual
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
: SDRAM 8ns
OnChip USB
: SDRAM 8ns USB Keyboard Support
: SDRAM 8ns
CPU Warning Temperature
: 3
Current System Temp
: Enabled Current CPU Temperature
: Enabled
CPU FAN Speed
: Enabled
CHASSIS FAN Speed
: Fast
VCORE :
: Enabled
VCC3 :
: Disabled
+12 V :
: Disabled
- 5V :
: 64M Shutdown Temperature
: Default
: Disabled
: Disabled ESC : Quit
: Disabled
F1 : Help
F5 : Old Values
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
: Enabled
: Disabled
: 75 ° C/167 ° F
:
:
:
:
VIO
+5 V :
-12 V :
: 70 ° C/158 ° F
: Select Item
PU/PD/+/- : Modify
(Shift) F2 : Color