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AI5VG+
Pentium MVP3
Baby AT Motherboard
User's Manual
Version 1.0F

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   Summary of Contents for TMC AI5VG+

  • Page 1

    AI5VG+ Pentium MVP3 Baby AT Motherboard User’s Manual Version 1.0F...

  • Page 3: Table Of Contents

    Contents Contents Chapter 1 Introduction............ 1 Chapter 2 Specifications ..........2 Chapter 3 Hardware Description ........5 3.1 Processor and CPU Voltage ..........7 3.2 L2 Cache Memory .............7 3.3 Main Memory ..............7 3.4 BIOS ..................9 3.5 Onboard PCI EIDE ............10 3.6 Onboard Multi-I/O............10 3.7 Onboard CPU Temperature Sensor .........10 3.8 I/O Port Address Map............11...

  • Page 4: Table Of Contents

    Contents 5.11 J13 Wake on LAN Connector ........30 5.12 J14: CPU Fan Power Connector........30 5.13 J20 Front Bezel Connector ..........30 Chapter 6 BIOS Configuration........33 6.1 BIOS Introduction ............34 6.2 BIOS Setup ..............34 6.3 Standard CMOS Setup.............36 6.4 BIOS Features Setup ............39 6.5 Chipset Features Setup ............42 6.6 Power Management Setup ..........44 6.7 PNP/PCI Configuration ...........47...

  • Page 5: Chapter 1 Introduction

    Chapter 1 Introduction Chapter 1 Introduction This manual is designed to give you information on the AI5VG+ Motherboard. It is divided into the following six sections: • • • • Introduction • • • • Specifications • • • • Hardware Description •...

  • Page 6: Chapter 2 Specifications

    Chapter 2 Specifications Chapter 2 Specifications Based on VIA’s MVP3 chipset, the AI5VG+ is a Baby AT Pentium motherboard that supports all the features to make a Microsoft PC’97 compliant PCI/ISA system. The AI5VG+ comes with an Accelerated Graphics Port (AGP) slot, power management functionality that is compliant with ACPI and legacy APM requirements.

  • Page 7

    Chapter 2 Specifications Onboard I/O Winbond W83877 for two serial, one parallel, one floppy drive interface and IrDA support Onboard Bus Mastering EIDE Two EIDE interfaces for up to four devices, support PIO Mode 3/4 or Ultra DMA/33 IDE Hard Disk and ATAPI CD-ROM. BIOS Licensed BIOS with additional features: •...

  • Page 8

    Chapter 2 Specifications This page is intentionally left blank. AI5VG+ User’s Manual...

  • Page 9: Chapter 3 Hardware Description

    Chapter 3 Hardware Description Chapter 3 Hardware Description This chapter briefly describes each of the major features of the AI5VG+ motherboard. The layout of the board is shown in Figure 1 which shows the locations of the key components. The topics covered in this chapter are as follows: 3.1 Processor and CPU Voltage ............

  • Page 10

    Chapter 3 Hardware Description Figure 1: Layout of the AI5VG+ Motherboard AI5VG+ User’s Manual...

  • Page 11: Processor And Cpu Voltage

    Chapter 3 Hardware Description 3.1 Processor and CPU Voltage The AI5VG+ is designed to take a Pentium Processor with a bus speed of 60, 66, 75, 83 and 100 MHz. The internal clock of the CPU can be multiples of 1.5, 2, 2.5, 3, 3.5, 4 and 4.5 of the bus clock, the CPU frequency can be 90 to 300MHz.

  • Page 12

    Chapter 3 Hardware Description (1) 72-pin SIMM (5V) - EDO DRAM SIMM1, SIMM2 Total Memory 4MB×2 16MB 8MB×2 32MB 16MB×2 64MB 32MB×2 128MB 64MB×2 (2) 168-pin DIMM (3.3V) - SDRAM or EDO DRAM DIMM3 DIMM2 DIMM1 Total Memory ----- ----- 16MB ----- -----...

  • Page 13: Bios

    Chapter 3 Hardware Description 168Pin DIMM (3.3V) - SDRAM or EDO DRAM (continued) DIMM3 DIMM2 DIMM1 Total Memory 64MB 16MB 16MB 96MB 128MB 16MB 16MB 160MB 32MB 32MB ----- 64MB 64MB 32MB ----- 96MB 128MB 32MB ----- 160MB 32MB 32MB 72MB 64MB 32MB...

  • Page 14: Onboard Pci Eide, Onboard Multi-i/o, Onboard Cpu Temperature Sensor

    Chapter 3 Hardware Description 2. ISA Plug and Play (PnP) Extension Unlike PCI cards which are plug and play, ISA cards require setting jumpers to resolve hardware conflicts. To make a computer system PnP, an ISA PnP standard is established and supported by new OSes, such as Windows 95.

  • Page 15: I/o Port Address Map

    Chapter 3 Hardware Description 3.8 I/O Port Address Map Each peripheral device in the system is assigned a set of I/O port addresses which also becomes the identity of the device. There are a total of 1K port address space available. The following table lists the I/O port addresses used on the motherboard.

  • Page 16: Interrupt Request Lines (irq)

    Chapter 3 Hardware Description 3.10 Interrupt Request Lines (IRQ) There are a total of 15 IRQ lines available on the motherboard. Peripheral devices use interrupt request lines to notify the CPU for the service required. The following table shows the IRQ used by the devices on the motherboard.

  • Page 17: Chapter 4 Hardware Settings

    Chapter 5 Installation Chapter 4 Hardware Settings The following sections describe the necessary procedures and proper jumper settings to configure the AI5VG+ motherboard. 4.1 SW1(1-8): CPU Frequency Selector ......... 15 4.2 JP1, SW1(4): DRAM Operating Frequency (AI5VG+-100)..20 4.3 JP6: System Frequency Divider (AI5VG+-100) ....... 20 4.4 SW2(1-4): CPU Voltage Selector ..........

  • Page 18

    Chapter 5 Installation Figure 2: Jumper Locations of the AI5VG+ AI5VG+ User’s Manual...

  • Page 19: Sw1(1-8): Cpu Frequency Selector

    Chapter 5 Installation 4.1 SW1(1-8): CPU Frequency Selector For Intel Pentium, IDT WinChip 2-3D / C6 Multiplier CPU FREQ. Clock Clock 66MHz 66MHz 1.5x P54C-100 off on on xx off off off on 66MHz 66MHz P54C-133 off on on xx on off off on P54C/P55C-16 66MHz 66MHz...

  • Page 20

    Chapter 5 Installation For Cyrix 6x86, 6x86L, 6x86MX CPU Clock Multiplier CPU FREQ. Clock P166+ 66MHz 66MHz (133MHz) off on on xx on off off on P200+ 75MHz 64MHz (150MHz) off off on xx on off off on PR200 66MHz 66MHz 2.5x (166MHz)

  • Page 21

    Chapter 5 Installation PR333 100MHz 66MHz 2.5x (250MHz) off off off xx on on off off PR366 100MHz 66MHz (300MHz) off off off xx off on off off MII-366 100MHz 66MHz 2.5x (250MHz) off off off xx on on off off MII-380 100MHz 66MHz (300MHz)

  • Page 22

    Chapter 5 Installation For AMD K5, K6, K6-2 CPU Multiplier CPU FREQ. Clock Clock 66MHz 66MHz 1.5x PR100 off on on xx off off off on 66MHz 66MHz PR133 off on on xx on off off on PR166 / 66MHz 66MHz 2.5x K6-166...

  • Page 23

    Chapter 5 Installation 66MHz 66MHz K6-2/400 off on on xx on off off on K6-2/400 100MHz 66MHz K6-3/400 off off off xx on off on off K6-2/450* 100MHz 66MHz 4.5x K6-3/450* off off off xx on on on off K6-2/475* 95MHz 63MHz K6-3/475*...

  • Page 24: Jp1, Sw1(4): Dram Operating Frequency

    Chapter 5 Installation 4.2 JP1, SW1(4): DRAM Operating Frequency SW1(4) SDRAM Frequency open Run CPU Clock closed Run AGP Clock NOTE: Set the SDRAM Frequency to Run CPU Clock only when the CPU clock is 100MHz and the DIMM module onboard meets PC-100 specifications.

  • Page 25

    Chapter 5 Installation For Dual Voltage CPU: Intel P55C, Cyrix 6x86L/MX/MII, AMD K6/K6-2, IDT WinChip 2-3D CORE K6-233 3.3V 3.2V (0.35µ) off off on on 3.3V 3.1V on on off on 3.3V 3.0V off on off on K6-166/200 3.3V 2.9V 6x86MX on off off on WinChip 2-3D...

  • Page 26: Jp2: Clear Cmos Selection

    Chapter 5 Installation For Dual Voltage CPU: Intel P55C, Cyrix 6x86L/MX, AMD K6/K6-2 CORE K6/K6-2 3.3V 2.2V (0.25µ) off on off off 3.3V 2.1V on off off off 3.3V 2.0V off off off off 4.5 JP2: Clear CMOS Selection Use JP2, a 3-pin header, to clear the contents of the CMOS RAM. Note that if you are using an ATX power supply, the ATX-power connector should be disconnected from the motherboard to be able to clear CMOS.

  • Page 27: Chapter 5 Installation

    Chapter 5 Installation Chapter 5 Installation This chapter describes the connectors and interfaces that the AI5VG+ provides for creating a working system. Refer to Figure 3 for the location of the connectors. The following items are covered in this chapter: 5.1 I/O Connectors ................

  • Page 28

    Chapter 5 Installation Figure 3: Connector Location on the AI5VG+ NOTE: JP1 and JP6 are for AI5VG+-100 only. AI5VG+-66 does not have these jumpers. AI5VG+ User’s Manual...

  • Page 29: I/o Connectors

    Chapter 5 Installation 5.1 I/O Connectors The I/O connectors connect the AI5VG+ to the most common peripherals. To attach cables to these connectors, carefully align Pin 1 of the cables to that of the connectors. Refer to Figure 4 for the location and orientation of the connectors.

  • Page 30: J7: Atx Power Supply Connector

    Chapter 5 Installation 5.3 J7: ATX Power Supply Connector J7 is a 20-pin ATX power supply connector. Refer to the following table for the pin out assignments. Signal Name Pin # Pin # Signal Name 3.3V 3.3V -12V 3.3V Ground Ground PS-ON Ground...

  • Page 31: J6, J5: Serial Ports

    Chapter 5 Installation 5.5 J6, J5: Serial Ports The onboard serial ports of the AI5VG+ are 10 pin-header connectors. J6 is COM1 and J5 is COM2. The following table shows the pin out of the these connectors. Pin # Signal Name DCD, Data carrier detect RXD, Receive data TXD, Transmit data...

  • Page 32: J10, J12: Eide Connectors

    Chapter 5 Installation 5.7 J10, J12: EIDE Connectors J10: Primary IDE Connector Signal Name Pin # Pin # Signal Name Reset IDE Ground Host data 7 Host data 8 Host data 6 Host data 9 Host data 5 Host data 10 Host data 4 Host data 11 Host data 3...

  • Page 33: J9: Parallel Port Connector

    Chapter 5 Installation 5.8 J9: Parallel Port Connector The following table describes the pin out assignments of this connector. Signal Name Pin # Pin # Signal Name Line printer strobe AutoFeed PD0, parallel data 0 Error PD1, parallel data 1 Initialize PD2, parallel data 2 Select...

  • Page 34: J13 Wake On Lan Connector, J14: Cpu Fan Power Connector, J20 Front Bezel Connector

    Chapter 5 Installation 5.11 J13 Wake on LAN Connector J13is a 3-pin header for Wake on LAN function on the motherboard. Pin # Signal Name 5VSB Ground Wake on LAN 5.12 J14: CPU Fan Power Connector J14 is a 3-pin header for the CPU fan power connector. The fan must be a 12V fan.

  • Page 35

    Chapter 5 Installation Speaker: Pins 1 - 4 This connector provides an interface to a speaker for audio tone generation. An 8-ohm speaker is recommended. J20 Pin # Signal Name Speaker out No connect Ground Power LED and Keylock: Pins 11 - 15 The power LED indicates the status of the main power switch.

  • Page 36

    Chapter 5 Installation Reset Switch: Pins 9 and 19 The reset switch allows the user to reset the system without turning the main power switch Off and then On. Orientation is not required when making a connection to this header. Hard Disk Drive LED Connector: Pins 10 and 20 This connector connects to the hard drive activity LED on control panel.

  • Page 37: Chapter 6 Bios Configuration

    Chapter 6 BIOS Configuration Chapter 6 BIOS Configuration This chapter describes the different settings available in the Award BIOS that comes with the AI5VG+ motherboard. The topics covered in this chapter are as follows: 6.1 BIOS Introduction..............34 6.2 BIOS Setup ................34 6.3 Standard CMOS Setup ..............

  • Page 38: Bios Introduction

    Chapter 6 BIOS Configuration 6.1 BIOS Introduction The Award BIOS (Basic Input/Output System) installed in your computer system’s ROM supports Intel/Cyrix/AMD processors in a standard IBM-AT compatible I/O system. The BIOS provides critical low-level support for standard devices such as disk drives, serial and parallel ports.

  • Page 39

    Chapter 6 BIOS Configuration ROM PCI/ISA BIOS CMOS SETUP UTILITY AWARD SOFTWARE, INC. STANDARD CMOS SETUP INTEGRATED PERIPHERALS BIOS FEATURES SETUP SUPERVISOR PASSWORD CHIPSET FEATURES SETUP USER PASSWORD POWER MANAGEMENT SETUP IDE HDD AUTO DETECTION PNP/PCI CONFIGURATION HDD LOW LEVEL FORMAT LOAD BIOS DEFAULTS SAVE &...

  • Page 40: Standard Cmos Setup

    Chapter 6 BIOS Configuration 6.3 Standard CMOS Setup “Standard CMOS Setup” choice allows you to record some basic hardware configurations in your computer system and set the system clock and error handling. If the motherboard is already installed in a working system, you will not need to select this option.

  • Page 41

    Chapter 6 BIOS Configuration Time The time format is: Hour : 00 to 23 Minute : 00 to 59 Second : 00 to 59 To set the time, highlight the “Time” field and use the <PgUp>/ <PgDn> or +/- keys to set the current time. Primary HDDs / Secondary HDDs The onboard PCI IDE connectors provide Primary and Secondary channels for connecting up to four IDE hard disks or other IDE devices.

  • Page 42

    Chapter 6 BIOS Configuration NOTE: The specifications of your drive must match with the drive table. The hard disk will not work properly if you enter incorrect information in these fields. If your hard disk drive type is not matched or listed, you can use Type User to define your own drive type manually.

  • Page 43: Bios Features Setup

    Chapter 6 BIOS Configuration 6.4 BIOS Features Setup This section allows you to configure and improve your system and allows you to set up some system features according to your preference. ROM / PCI ISA BIOS BIOS FEATURES SETUP AWARD SOFTWARE, INC. Virus Warning Video BIOS Shadow : Enabled...

  • Page 44

    Chapter 6 BIOS Configuration Quick Power On Self Test This choice speeds up the Power On Self Test (POST) after you power up the system. If it is set to Enabled, BIOS will skip some items. By default, this choice is Enabled. Boot Sequence This field determines the drive that the system searches first for an operating system.

  • Page 45

    Chapter 6 BIOS Configuration Typematic Rate Setting When disabled, continually holding down a key on your keyboard will generate only one instance. When enabled, you can set the two typematic controls listed next. By default, this field is set to Disabled. Typematic Rate (Chars/Sec) When the typematic rate is enabled, the system registers repeated keystrokes speeds.

  • Page 46: Chipset Features Setup

    Chapter 6 BIOS Configuration 6.5 Chipset Features Setup This Setup menu controls the configuration of the motherboard chipset. ROM PCI/ISA BIOS CHIPSET FEATURES SETUP AWARD SOFTWARE INC. Bank 0/1 DRAM Timing : 60ns OnChip USB : Enabled Bank 2/3 DRAM Timing : 60ns USB Keyboard Support : Disabled...

  • Page 47

    Chapter 6 BIOS Configuration Read Around Write DRAM optimization feature: If a memory read is addressed to a location whose latest write is being held in a buffer before being written to memory, the read is satisfied through the buffer contents, and the read is not sent to the DRAM.

  • Page 48: Power Management Setup

    Chapter 6 BIOS Configuration CPU/PCI Clock Select The default settings for the CPU/PCI clock are 66/33MHz (default) and 100/33MHz, depending on the bus speed of the CPU you have installed. If overclocking causes the system to be unstable, use the defaults. Note that 112/37MHz, 124/41MHz and 133/44MHz settings are only supported if your motherboard has an ICS 9148AF-58 clock generator.

  • Page 49

    Chapter 6 BIOS Configuration Power Management This field allows you to select the type of power saving management modes. Four selections for Power Management include Disabled, Min. Power Saving, Max. Power Saving, and User Define (Default). NOTE: In order to enable the CPU overheat protection feature, the Power Management field should not be set to Disabled.

  • Page 50

    Chapter 6 BIOS Configuration PM Events The VGA, LPT & COM, HDD & FDD, DMA /master, Modem Ring Resume, RTC Alarm Resume and Primary INTR section are I/O events which can prevent the system from entering a power saving mode or can awaken the system from such a mode.

  • Page 51: Pnp/pci Configuration, Ai5vg+ User's Manual

    Chapter 6 BIOS Configuration 6.7 PNP/PCI Configuration This option configures the PCI bus system. All PCI bus systems on the system use INT#, thus all installed PCI cards must be set to this value. ROM PCI/ISA BIOS PNP/PCI Configuration AWARD SOFTWARE INC. PNP OS Installed : No CPU to PCI Write Buffer...

  • Page 52

    Chapter 6 BIOS Configuration IRQ3/4/5/7/9/10/11/12/14/15, DMA0/1/3/5/6/7 assigned to These fields allow you to determine the IRQ/DMA assigned to the ISA bus and is not available to any PCI slot. CPU to PCI Write Buffer When enabled, this option increase the efficiency of the PCI bus to and speed up the execution in the processor.

  • Page 53

    Chapter 6 BIOS Configuration PCI IDE IRQ Map To This field allows you to configure the type of IDE disk controller in your system. The default setup is ISA. If you have equipped with PCI controller, you need to specify which slot has the controller and PCI interrupt is associated with the connected hard drives.

  • Page 54: Load Bios Defaults, Load Setup Defaults

    Chapter 6 BIOS Configuration 6.8 Load BIOS Defaults This option allows you to load the troubleshooting default values permanently stored in the BIOS ROM. These default settings are non-optimal and disable all high-performance features. ROM PCI/ISA BIOS CMOS SETUP UTILITY AWARD SOFTWARE, INC.

  • Page 55: Integrated Peripherals

    Chapter 6 BIOS Configuration 6.10 Integrated Peripherals This option sets your hard disk configuration, mode and port. ROM PCI/ISA BIOS INTEGRATED PERIPHERALS AWARD SOFTWARE INC. OnChip IDE First Channel : Enabled Onboard Parallel Mode : SPP OnChip IDE Second : Enabled Channel IDE Prefetch Mode : Disabled...

  • Page 56

    Chapter 6 BIOS Configuration The system supports five modes, numbered from 0 (default) to 4, which primarily differ in timing. When Auto is selected, the BIOS will select the best available mode. IDE Primary/Secondary Master/Slave UDMA This field allows your system to improve disk I/O throughput to 33Mb/sec with the Ultra DMA/33 feature.

  • Page 57: Supervisor / User Password

    Chapter 6 BIOS Configuration 6.11 Supervisor / User Password These two options set the system password. Supervisor Password sets a password that will be used to protect the system and Setup utility. User Password sets a password that will be used exclusively on the system. To specify a password, highlight the type you want and press <Enter>.

  • Page 58: Ide Hdd Auto Detection, Hdd Low Level Format

    Chapter 6 BIOS Configuration 6.12 IDE HDD Auto Detection This option detects the parameters of an IDE hard disk drive, and automatically enters them into the Standard CMOS Setup screen. ROM PCI/ISA BIOS STANDARD CMOS SETUP AWARD SOFTWARE, INC. HARD DISKS TYPE SIZE CYLS...

  • Page 59: Exit Without Saving, Save & Exit Setup

    Chapter 6 BIOS Configuration 6.14 Save & Exit Setup This option allows you to determine whether to accept the modifications or not. If you type “Y”, you will quit the setup utility and save all changes into the CMOS memory. If you type “N”, you will return to Setup utility. ROM PCI/ISA BIOS CMOS SETUP UTILITY AWARD SOFTWARE, INC.

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