Chipset Features Setup - TMC AI5TT User Manual

Chapter 6 BIOS Configuration

6.5 Chipset Features Setup

This Setup menu controls the configuration of the motherboard chipset.
DRAM Timing
SDRAM (CAS Lat/RAS-to-CAS)
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
PCI 2.1 Compliance
DRAM Timing
The DRAM timing is controlled by the DRAM Timing Registers. The
timing type is dependent on the system design. Slower rates may be
required in some system designs to support loose layouts or slower
memory.
SDRAM (CAS Lat / RAS -to-CAS)
This item allows you to select the CAS# latency for all SDRAM cycles
and RAS# to CAS# delay.
2/2 The timing type.
3/3 The timing type.
System BIOS Cacheable
When enabled, access to the system BIOS ROM addressed at
F0000H-FFFFFH are cached, provided that the cache controller is
disabled.
Video BIOS Cacheable
When enabled, access to video BIOS addressed at C0000H to C7FFFH
are cached, provided that the cache controller is enabled.
40 AI5TT Pentium Baby AT Motherboard User's Manual
ROM PCI/ISA BIOS
CHIPSET FEATURES SETUP
AWARD SOFTWARE INC.
: 70ns Power-Supply Type
: 3/3
: Disabled CPU Warning Temperature
: Enabled
: Disabled Current System Temp.
Disabled Current CPU Temperature
Current CPUFAN Speed
VIO : 3.31 V VCORE
+12 V : 11.26V +5 V
- 5 V : -4.84V -12 V
ESC : Quit
F1 : Help
F5 : Old Values
F6 : Load BIOS Defaults
F7 : Load Setup Defaults
: Auto
: 70°C/158°F
: 25°C/77°F
: 37°C/98°F
: 5720 RPM
: 2.84V
: 5.11V
: -10.93V
: Select Item
PU/PD/+/- : Modify
(Shift) F2 : Color