Chipset Features Setup; Dram Timing; Sdram Cycle Length; Dram Read Pipeline - TMC MI5VMT User Manual

Mvp4 micro atx motherboard

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6.5 Chipset Features Setup

This Setup menu controls the configuration of the motherboard chipset.

Bank 0/1 DRAM Timing

Bank 2/3 DRAM Timing

Bank 4/5 DRAM Timing

SDRAM Cycle Length

DRAM Read Pipeline

Sustained 3T Write

Cache Rd+CPU Wt Pipeline

Cache Timing

Video BIOS Cacheable

System BIOS Cacheable

Memory Hole

Init Display First

Frame Buffer Size

AGP Aperture Size (MB)

Auto Detect DIMM/PCI Clk

Spread Spectrum

DRAM Timing

The DRAM timing is controlled by the DRAM Timing Registers. The

timing type is dependent on the system design. Slower rates may be

required in some system designs to support loose layouts or slower

memory.

SDRAM Cycle Length

This field sets the SDRAM cycle length to either 2 or 3. The default

setting is 3.

DRAM Read Pipeline

When enabled, this field supports pipelining of DRAM reads. The

default setting is Enabled.

Sustained 3T Write

This field allows support for PBSRAM sustained 3T write. By default,

this field is set Enabled.

Cache R/CPU W Pipeline

When enabled, this item allows pipelining of cache reads and CPU

writes. The default setting is Enabled.

MI5VMT User's Manual

ROM PCI/ISA BIOS