Table of Contents
Advertisement
4.3.4 -2V Reference
Source
The Model 485 current measurements are based on compar-
ing the unknown
signal with
an internal
-2V reference
voltage. During each measurement cycle the microprocessor
samples the unknown and uses it along with a zero measure-
ment and -2V signal measurement to compute the unknown
voltage.
The -2V reference is made up of a highly stable zener diode
(VR103). an op-amp and a resistive voltage divider. U107 and
RI22 A, B, C act as a constant current source to minimize the
zener voltage variations.
RI18 C, D is then used to divide
down the -6.35V zener voltage to approximately
-2V.
The output
of U107 I-N)
is used as a reference voltage
for the A/D converter and as a negative supply for various
components.
4.3.5 AID
Converter
The Model 485 uses a combination
constant
frequency
charge balance, single slope analog-to-digital
converter.
A
simplified schematic of the A/D
used in the Model 485 is
shown in Figure 4-5 with an associated output waveform.
The charge balance phase begins when the input enable line
is set high. This occurs at the end of a software-generated
delay period that allows the signal to settle after the ap-
propriate
multiplexer
FET is turned
on. The actual delay
period depends on the selected range and function.
Once this occurs the signal from the buffer amplifier is added
to the offset from Rl22H.
This converts the bipolar signal
from the buffer t +2V) to a &polar
input for the integrator.
The integrator
ramps up until it just passes the charge-
balance comparator threshold voltage. When thejsing
edge
of 03 occursfrom
U116 or when U115goes low, Qgoes high
forcing
ICB into the integrator
input.
Since ICB is much
greater than the current through
Rl22G and Rl22H the in-
tegrator output voltage will ramp in the negative direction.
The integrator will continue ramping downward
until U115B
goes low. Each time the output U117A goes high it is gated
(inside the microprocessor)
with the microprocessor's
inter-
nal clock and these pulses are counted.
Once U117A goes
low the process repeats itself.
The charge balance phase continues for IOOmsec. At the end
of the charge balance phase, the output of the integrator is
resting at some positive voltage. Since the integrator output
is connected to the noninverting
input of the UllOA,
its out-
put will stay high until the integrator ramps negative. During
single slope 0109 is turned off and R120l-i is connected to
+5V.
The single slope comparator
is then gated with the
microprocessor's
internal clock and counted. Once the com-
parator output goes low the microprocessor stops counting
and can compute the reading.
SINGLE SLOPE
R120A
CHARGE
BALANCE
I
'I .5v
UllOB
Figure 4-5. AID
Converter
INPUT
ENABLE/
DISABLE
I
I
U116
4-3
Advertisement
Table of Contents
