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result in a 2V output from the converter f-(2mA) x 1 kD = -2Vl.
On
the
2nA
range,
the
fullscale
output
is 200mV
I-2nAt x IOOMD = -2OOmVl. The maximum
output
voltage
from the converter
for an on-scale reading is *1.9999\1
If 199.99mV for the 2nA range).
Actuating
the ZERO CHECK pushbutton
shorts the feedback
resistance of U105 which results in the offset of U106 being
presented at its output. The ZERO pot is used to eliminate the
offset of the amplifier.
RANGE
RESISTORS
ZERO
INPUT
POT
TO MULTIPLEXgR
Figure 4-2. Current-to-Voltage
Converter
4.3.2 Multiplexer
The multiplexer
connects one of four signals to the buffer
amplifier;
two possible signal lines, zero or the reference.
The multiplexer, shown in Figure 4-3, is made up of 4 JFETS
which are controlled
by the microprocessor
through
Ulll.
The FETs are driven by U102 and part of U103. The drivers
convert the digital signals of the microprocessor
to signals
useable by the FETs.
All ranges, except the 2mA range, are fed to Q106 of the
multiplexer. The 2mA range uses a line that senses the signal
before
the range FET IQlOl)
and feeds it directly to the
multiplexer
lQ105L The sense line is needed because of the
relatively high resistance of the range FET (6OD) as compared
to the resistance of the feedback resistor flkD).
Ordinarily,
F5T switching
creates transients which could be
seen in the final measurement. These effects are minimized in
the Model 485 through the use of software generated delays
and by signal-ground
differenatial
measurements.
4.3.3 Input Buffer Amplifier
The input buffer amplifier provides the necessary isolation
between
the input
signal and the AID
converter.
The
amplifier is a noninverting,
low noise, high impedance circuit
with xl gain for the 20nA-2mA
ranges and x10 gain for the
2nA
range.
The
amplifier
gain
is controlled
by
the
microprocessor.
Figure 44 shows the simplified schematic of
the input buffer amplifier.
Figure 4-3. Simplified
Schematic
of the Multiplexer
INPUT FROM
MuLT'pLEF=-l
sy;
. ..-
I
ilERT!R
>
RlZ2F
1okn
1kQ
FROM Ulll
(PSO)
0
Figure 44.
Simplified
Schematic
of the Input
Buffer
Amplifier
4-2
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