Advantech UNO-2050 User Manual page 52

GND
Ground
PD0~PD17
Flat Panel Data Port Lines 17 to 0. This is the data port to an attached
active matrix TFT panel.
FSCLK
Flat Panel Clock. This is the clock for the flat panel interface.
FVSYNC
Flat Panel Vertical Sync Output. This is the vertical sync for an
attached active matrix TFT flat panel. This represents a delayed
version of the input flat panel vertical sync signal with the appropriate
pipeline delay relative to the pixel data.
FHSYNC
Flat Panel Horizontal Sync Output. This is the horizontal sync for an
attached active matrix TFT flat panel. This represents a delayed
version of the input flat panel horizontal sync signal with the appropri-
ate pipeline delay relative to the pixel data.
FPEN
Flat Panel Display Enable Output. This is the display enable for an
attached active matrix TFT flat panel. This signal qualifies active pixel
data on the flat panel interface.
ENDISP
Display Enable Input. This signal qualifies active data on the pixel
input port. It is used to qualify active pixel data for all display modes
and configurations and is not specific.
VBIASEN
Flat Panel Backlight Enable Output. This is the enable signal for the
backlight power supply to an attached flat panel. It is under control of
the power sequence control logic.
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