Programmable Function Inputs; Board And Rtsi Clocks; Rtsi Triggers - National Instruments DAQ PCI E Series User Manual

Programmable Function Inputs

Board and RTSI Clocks

RTSI Triggers

© National Instruments Corporation
The 10 PFIs are connected to the signal routing multiplexer for each
timing signal, and software can select one of the PFIs as the external
source for a given timing signal. It is important to note that any of the
PFIs can be used as an input by any of the timing signals and that
multiple timing signals can use the same PFI simultaneously. This
flexible routing scheme reduces the need to change physical
connections to the I/O connector for different applications. You can
also individually enable each of the PFI pins to output a specific internal
timing signal. For example, if you need the UPDATE* signal as an
output on the I/O connector, software can turn on the output driver for
the PFI5/UPDATE* pin.
Many functions performed by the PCI E Series boards require
a frequency timebase to generate the necessary timing signals for
controlling A/D conversions, DAC updates, or general-purpose signals
at the I/O connector.
A PCI E Series board can use either its internal 20 MHz timebase or a
timebase received over the RTSI bus. In addition, if you configure the
board to use the internal timebase, you can also program the board to
drive its internal timebase over the RTSI bus to another board that is
programmed to receive this timebase signal. This clock source, whether
local or from the RTSI bus, is used directly by the board as the primary
frequency source. The default configuration at startup is to use the
internal timebase without driving the RTSI bus timebase signal. This
timebase is software selectable.
The seven RTSI trigger lines on the RTSI bus provide a very flexible
interconnection scheme for any PCI E Series board sharing the RTSI
bus. These bidirectional lines can drive any of eight timing signals onto
the RTSI bus and can receive any of these timing signals. This signal
connection scheme is shown in Figure 3-13.
3-19
Chapter 3 Hardware Overview
PCI E Series User Manual