Gpctr0_Out Signal; Gpctr0_Up_Down Signal; Figure 4-31. Gpctr0_Gate Signal Timing In Edge-Detection Mode; Figure 4-32. Gpctr0_Out Signal Timing - National Instruments DAQ PCI E Series User Manual

Chapter 4 Signal Connections
Rising-edge
polarity
Falling-edge
polarity
GPCTR0_SOURCE
GPCTR0_OUT
(Pulse on TC)
GPCTR0_OUT
(Toggle output on TC)
PCI E Series User Manual
Figure 4-31 shows the timing requirements for the GPCTR0_GATE
signal.

Figure 4-31. GPCTR0_GATE Signal Timing in Edge-Detection Mode

GPCTR0_OUT Signal

This signal is available only as an output on the GPCTR0_OUT pin. The
GPCTR0_OUT signal reflects the terminal count (TC) of
general-purpose counter 0. You have two software-selectable output
options—pulse on TC and toggle output polarity on TC. The output
polarity is software selectable for both options. This output is set to
tri-state at startup. Figure 4-32 shows the timing of the GPCTR0_OUT
signal.

Figure 4-32. GPCTR0_OUT Signal Timing

GPCTR0_UP_DOWN Signal

This signal can be externally input on the DIO6 pin and is not available
as an output on the I/O connector. The general-purpose counter 0 will
count down when this pin is at a logic low and count up when it is at a
logic high. You can disable this input so that software can control the
up-down functionality and leave the DIO6 pin free for general use.
t
w
t
= 10 ns minimum
w
TC
4-42 © National Instruments Corporation