Analog Trigger; Figure 3-6. Analog Trigger Block Diagram - National Instruments DAQ PCI E Series User Manual

Chapter 3 Hardware Overview

Analog Trigger

Note:
Analog
Input
Channels
PFI0/TRIG1
PCI E Series User Manual
PCI-MIO-16E-1, PCI-MIO-16E-4, PCI-MIO-16XE-10, PCI-6031E,
PCI-6032E, PCI-6033E, and PCI-6071E
In addition to supporting internal software triggering and external
digital triggering to initiate a data acquisition sequence, these boards
also support analog triggering. You can configure the analog trigger
circuitry to accept either a direct analog input from the PFI0/TRIG1 pin
on the I/O connector or a postgain signal from the output of the PGIA,
as shown in Figure 3-6. The trigger-level range for the direct analog
channel is ±10 V in 78 mV steps for the PCI-MIO-16E-1,
PCI-MIO-16E-4, and PCI-6071E, and ±10 V in 4.9 mV steps for the
PCI-MIO-16XE-10, PCI-6031E, PCI-6032E, and PCI-6033E. The
range for the post-PGIA trigger selection is simply the full-scale range
of the selected channel, and the resolution is that range divided by 256
for the PCI-MIO-16E-1, PCI-MIO-16E-4, and PCI-6071E and divided
by 4,096 for the PCI-MIO-16XE-10, PCI-6031E, PCI-6032E, and
PCI-6033E.
The PFI0/TRIG1 pin is an analog input when configured as an analog
trigger. Therefore, it is susceptible to crosstalk from adjacent pins, which
can result in false triggering when the pin is left unconnected. To avoid
false triggering, make sure this pin is connected to a low-impedance signal
source (less than 1 k
via software.
+
PGIA
-
source impedance) if you plan to enable this input
ADC
Analog
Trigger
Mux
Circuit

Figure 3-6. Analog Trigger Block Diagram

3-14
DAQ-STC
© National Instruments Corporation