Figure 3-2. At-Mio-64E-3 Block Diagram - National Instruments AT-MIO/AI E Series User Manual

Chapter 3 Hardware Overview
Voltage
REF
(32)
Analog
Muxes
(32)
Calibration
Mux
2
Trigger Level
DACs
Trigger
PFI / Trigger
Timing
Digital I/O (8)
DAC0
DAC1
AT-MIO/AI E Series User Manual
Figure 3-2 shows the block diagram for the AT-MIO-64E-3.
Calibration
DACs
3
+
NI-PGIA
Mux Mode
Gain
Selection
Amplifier
Switches
–
Dither
Circuitry
Analog
Trigger
Circuitry
Trigger
Counter/
Timing I/O
Digital I/O
DAC
FIFO
Calibration
6 DACs
12-Bit
Sampling
ADC
A/D
FIFO
Converter
Configuration
AI Control
Memory
DMA/
Analog Input
Interrupt
Timing/Control
Request
Bus
DAQ - STC
Interface
Analog Output
RTSI Bus
Timing/Control
Interface
AO Control
Data (16)
RTSI Bus

Figure 3-2. AT-MIO-64E-3 Block Diagram

3-2
Data
Transceivers
EEPROM
IRQ
8
DMA
Analog
EEPROM DMA
Input
Control Interface
3
Control
DAQ-STC
Plug
Bus DAQ-PnP
and
Interface
Play
Analog 8255
Bus
Output DIO
Interface
Control Control
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