Serial Trigger; Clock Recovery; Jitter Analysis - LeCroy SDA Operator's Manual

Serial Trigger

Available on SDA 6000A (XXL), SDA 5000A (XXL), SDA 4000A (XXL)
Data Type
Sensitivity
Min. Frequency
Max. Frequency
Serial Trigger Length
Clock/Data Output Connector Type
Clock/Data Output
Clock/Data Output Voltage Swing (into 50 Ω)
Clock /Data Output Rise/Fall Time
Recovered CLK and DATA Jitter
Recovered CLK and DATA Phase Relationship
Source
Trigger Sensitivity

Clock Recovery

custom filter settings
damping factor
natural frequency

Jitter Analysis

advanced (peak-peak, rms)
basic (Tj, Rj, Dj)
bathtub curve
conventional
cycle-cycle jitter
Dj breakdown
edge to edge (data to data)
edge to reference (data to
clock)
effective
filtered jitter
32
NRZ encoded for clock extraction (needs
edge density > 20%)
1 division minimum and at least 10 mV
50 MHz
2.7 GHz
up to 32 bits
SMA
1/2 amplitude, AC coupled LVPCL
400 mV typical
200 ps typical
0.015 UI rms typical
Data is centered on the rising edge of the
clock
Channel 4 only
1 division minimum and at least 10 mV
number of poles
Standard PLL settings
(FC, Golden, PCIe, DVI, Custom)
half-period jitter
ISI plot
jitter histogram
jitter wizard
MJSQ
period jitter
periodic jitter (Pj) with peak frequency listing
synchronous N-cycle with bit pattern display
TIE clock jitter
TIE jitter
p-p
p-p
SDA-OM-E Rev H