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LeCroy 3377 Operator's Manual

32 channel camac tdc
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OPERATOR'S MANUAL
MODEL 3377
32 CHANNEL CAMAC TDC
Revised
January 1997
(ECO 1101)
1

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Summary of Contents for LeCroy 3377

  • Page 1 OPERATOR'S MANUAL MODEL 3377 32 CHANNEL CAMAC TDC Revised January 1997 (ECO 1101)
  • Page 2 Chestnut Ridge, New York 10977-6499 Tel: (914) 578-6013 Fax: (914) 578-5984 E-mail: lrs_support@lecroy.com Copyright© December 1997. LeCroy™ is a registered trademark of LeCroy Corporation. All rights reserved. Information in this publication supersedes all earlier versions. Specifications are subject to change.
  • Page 3 CE CONFORMITY CONDITIONS FOR CE CONFORMITY Since this product is a subassembly, it is the responsibility of the end user, acting as the system integrator, to ensure that the overall system is CE compliant. This product was demonstrated to meet CE conformity using a CE compliant crate housed in an EMI/RFI shielded enclosure.
  • Page 4 CAUTION COOLING It is imperative that the Model 3377 TDC be well cooled. Be sure fans move sufficient air to maintain exhaust air temperature at less than 50° C. INSTALLATION Crate power should be turned off during insertion or removal of modules in accordance with the CAMAC specification.

  • Page 5: Table Of Contents

    TABLE OF CONTENTS 1. General Information Purpose Unpacking and Inspection Warranty Product Assistance Maintenance Agreements Documentation Discrepancies Software Licensing Agreement Service Procedure 2. Installation General Installation Cables 3. Product Description Introduction Product Description Specifications Front Panel Displays Inputs and Outputs Control Signal Inputs ECLbus output...
  • Page 6 Buffered Mode Unbuffered Mode ECLPORT (FERA) Mode Buffered Mode Unbuffered Mode FERA Compatibility Standard 4300B FERA Behavior Modified Model 3377 FERA Behavior 4300 Compatible Mode Fast FERA Mode Data Formats Single Word Format Double Word Format Suppressing the Header Example 3377 Programming Sequence 5.

  • Page 7: General Information

    LeCroy are covered by the original equipment manufacturers’ warranty only. In exercising this warranty, LeCroy will repair or, at its option, replace any product returned to the Customer Service Department or an authorized service facility within the warranty period, provided that the warrantor’s examination discloses that the product is defective due to...

  • Page 8: Software Licensing Agreement

    Products requiring maintenance should be returned to the Customer Service Department or authorized service facility. If under warranty, LeCroy will repair or replace the product at no charge. The purchaser is only responsible for the transportation charges arising from return of the goods to the service facility.

  • Page 9: Installation

    “Talker/Listener”, allowing the crate to act as one GPIB instrument. With the power off, the 3377 is inserted into one of the slots of the CAMAC crate. The edge connector on the module should mate with the bus connector with modest pressure.

  • Page 10: Product Description

    Converter (TDC) intended for high rate particle physics experiments. The 500 picosecond digitizing resolution, 32 microsecond maximum full scale, and low dead time make the Model 3377 suitable for a wide range of applications. The Model 3377 can be operated either in Common...

  • Page 11: Specifications

    100 nsec per 16 bit word, and is compatible with existing FERA mod- ules. The many versatile features of the Model 3377 are provided by a Xilinx programmable gate array chip, which contains the control logic for the board. Changing the mode (Common Start/Stop, single/double word)

  • Page 12: Displays

    The control signal terminations and pull down resistors for the control signals and the ECL port are socketed. When several 3377 are bussed together to a 4301 FERA driver, all of the socketed resistors should be removed from each unit, except from the last 3377.

  • Page 13: Signal Inputs

    Signal Inputs Two 34 pin headers are for hit inputs; marked IN. The channels are arranged sequentially from channel 0 at the top to channel 15 and channel 16 to channel 31. The bottom pins (33,34) on both headers are grounded through 100 ohm resistors.
  • Page 14 Begin the reprogramming sequence For completeness, we describe the following commands that are available only during the programming mode of the Model 3377’s internal Xilinx logic chip. These enable the mode to be set by selecting a firmware program from the 4 that are installed in the EPROM, or loading a different program from CAMAC.

  • Page 15: Operating Instructions

    OPERATING INSTRUCTIONS The 3377 has four separate operating modes. The mode is determined by the Xilinx program loaded from the eprom, see below for changing operating mode. The times are measured with respect to a common hit, which can occur before or after the individual time signal to be measured (Common Stop or Common Start mode).

  • Page 16: Operating Modes

    F13, any subaddress. Test the done flag, return Q=1 when program- ming is complete. The host computer should loop on this command until Q is equal to 1. F9, any subaddress. This is REQUIRED after reprogramming. This resets the on board PAL (programmed array logic device) which allows the Xilinx to be programmed, causing all function codes to be ignored by the PAL, except for F30, which starts the reprogramming sequence.

  • Page 17: Mode 0: Common Stop, Single Word Mode

    Mode 0: Common Stop, Single Word Mode Control Registers Control Register #0 Data Shift Value User settable ID Code Edge Recording Readout Mode Buffer Mode Header Mode Mode Control Register #1 Trigger pulse Serial number Trigger Pulse Width delay Trig. clock FERA Mode unit Control Register #2...
  • Page 18 bit 14, 15 Read only, indicates the program load in use. Common Stop Single Word mode is 0 control register 1 (subaddress 1) bits 0-3 Selects the trigger output pulse width, in clock units, 0 to 15. Default is 0. bits 4-7 Selects the trigger pulse delay, in clock units.

  • Page 19: Maximum Time Range

    (7.5 nsec) or less. Offset The Offset register is implemented on the 3377 board, in the program- mable gate array chip. Only the upper 12 bits of this 16 bit word can be set. The lower 4 bits are effectively set to zero. The offset is subtracted from the data read from the MTD133, before the shift is applied.

  • Page 20: Dead Time

    If the 3377 is not set to buffer the data then busy will remain on until the data is read out of the unit.

  • Page 21: Mode 1: Common Start, Single Word

    Mode 1: Common Start, Single Word Control Register Control Register #0 Data Shift Value User settable ID code Edge Recording Readout Mode Buffer Mode Header Mode Mode Control Register #1 Not used Serial number FERA Mode Control Register #2 Not used Max.
  • Page 22 bit 12 Selects Buffer mode 1 = Multi-event buffer mode 0 = Single buffer mode. In this mode the FERA readout is compatible with the 4300B FERA ADC. The request delay (see register 3) must be set appropriately. bit 13 Selects Header mode 0 = always have header (default) 1 = skip header if no data words...

  • Page 23: Common Start Time Out

    bits 10-15 Not used, always reads 0 control register 5 (subaddress 5) bits 0-4 The number of pulses generated in test mode. 0-31 pulses, each 1/2 clock period long. bits 5-6 The test mode clock. 0 = 100 nsec 1 = 200 nsec 2 = 400 nsec 3 = 800 nsec bit 7...

  • Page 24: Dead Time

    The module is now ready for a new event, beginning with the common hit. If the 3377 is not set to buffer (see section “Buffered Mode”) then busy will remain on until the data is read out of the unit.

  • Page 25: Mode 2: Common Stop, Double Word

    Mode 2: Common Stop, double word Control Registers There are only 4 control registers Control Register #0 Not used User settable ID code Edge Recording Readout Mode Buffer Mode Header Mode Mode Control Register #1 Serial number Trigger pulse Trigger out pulse delay Trig.
  • Page 26 bit 14, 15 Read only, indicates the program load in use. Common Stop Double Word mode is 2 control register 1 (subaddress 1) bits 0-3 Selects the trigger output pulse width, in clock units, 0 to 15. Default is 0. bits 4-7 Selects the trigger pulse delay, in clock units.

  • Page 27: Maximum Time Range

    (7.5 nsec) or less. Dead Time The 3377 is a pipelined TDC, and the pipeline is stopped during the transfer of the hit data from the chips to the FIFO event buffer on the board. The time to buffer the data is typically 1.8 µs + 200 nsec per hit.

  • Page 28: Mode 3: Common Start, Double Word Mode

    Mode 3: Common Start, Double Word Mode Control Registers CONTROL REGISTERS, COMMON START, DOUBLE WORD MODE There are 6 control registers. Control Register #0 Not Used User settable ID code Edge Recording Readout Mode Buffer Mode Header Mode Mode Control Register #1 Not used Serial number FERA Mode...
  • Page 29 bit 13 Selects Header mode 0 = always have header (default) 1 = skip header if no data words bit 14, 15 Read only, indicates the program load in use. Common Start Double Word mode is 3 control register 1 (subaddress 1) bits 0-10 Not used, always reads 0.

  • Page 30: Common Start Time Out

    Dead Time After the common start time out the 3377 buffers the data. Buffering takes typically 1.8 µs +200 nsec per hit. During this time the front panel BUSY output is asserted and the module responds with Q=1 to an F27, A1 command.
  • Page 31 CLEAR must arrive at least 100 nsec AFTER the leading edge of the COMMON START, and at least 100 nsec BEFORE the COMMON START TIME OUT or the end of MPI (COMMON START TIME OUT plus the MPI setting).

  • Page 32: Trigger Outputs

    TRIGGER OUTPUTS Trigger Outputs in the Common Stop Modes The eight prompt OR outputs are stretched (one shots) and delayed (pipeline delay) using digital techniques. The trigger output pulse width and delay can be selected, in increments as small as 25 nsec. The output pulses have a jitter with respect to the input of up to 1 clock period.

  • Page 33: Trigger Outputs In The Common Start Modes

    STOP arrives somewhat later than the end of the event time. The width should be set to the desired coincidence resolution (the drift time of the chamber). If the trigger outputs of several 3377 modules are to be combined in a trigger system, an appropriate external clock should be supplied to synchronize the trigger outputs.

  • Page 34: Readout Modes And Data Formats

    A&B). With this change, the REN signal can be used as flow control for the ECLport output in the same way as the 4300, when the 3377 is in unbuffered mode. In addition, a new mode has been provided which allows the use of WAK for flow control when the 3377 ECLport is oper- ated in the fast mode.

  • Page 35: Modified Model 3377 Fera Behavior

    (single or double word). The conversion time can be as short as two microseconds or as long as 103 microseconds. In addition, the 3377 has a multi event buffer, which can hold as many as 31 events. Fortunately, the 3377 can also be operated in an unbuffered mode, which although slightly different than the 4300B FERA ADC, is quite compatible with it.

  • Page 36: Fast Fera Mode

    ECLbus. Fast FERA Mode The 3377 has 2 FERA modes, normal and fast. These are available both in multi event buffered and single buffer modes. In normal FERA mode, flow control is automatic, and uses the WST-WAK handshake. A fast FERA mode can be selected by setting a bit in a control register, which allows readout at 10 Mwords per second by ignoring the handshake.

  • Page 37: Suppressing The Header

    CAMAC or FERA. The event is not suppressed, only the header, so the event ordering remains correctly synchronized among multiple 3377 modules. If the channel occupancy is low, the use of this feature can result in a reduction in the size of the data block for each event, and a small de- crease in readout time (not the same as the dead time).

  • Page 38: Example 3377 Programming Sequence

    EXAMPLE 3377 PROGRAMMING SEQUENCE Step 1: CAMAC Reprogramming (see Operating Instructions) F9, any subaddress (should be executed as first command after powerup) F30, any subaddress (selects programming mode, resets Xilinx chip) F21, any subaddress (selects common start, single word mode)

  • Page 39: Control And Readout

    THEORY OF OPERATION The Model 3377 time digitizer consists of 7 major subsystems: TIME MEASUREMENTS Four LeCroy MTD133 custom monolithic integrated circuits perform the actual time measurements. The 250 MHz clock is provided by a crystal oscillator, and a symmetrizing circuit which adjusts the duty factor to 50%.

  • Page 40: Event Buffer Memory

    The 8 output signals are converted back to ECL and are available at the rear panel. An external clock input allows the synchronization of the digital one shots and delay for multiple 3377 modules. SUPPORT CIRCUITS Nearly all control logic for the module is located in the Xilinx program- mable gate array.
  • Page 41 Common Start modes. On every CAMAC instruction in the crate, the F, A, I, C and Z lines are latched at S2. These can be read if the very next instruction is F1, A6, to a 3377 module (which is in Common Start mode).

  • Page 42: Extending The Time Range

    16 TDC inputs. The 16 bit counter word is strobed after each count, to provide a pulse pattern (each ‘1’ bit produces a pulse) which is sent to sixteen of the 3377 inputs. The 3377 maximum time range is set to 11 microseconds. This...

  • Page 43: Labview™ Support

    The 3377 measures the time of the event relative to the 100 kHz clock. The correct absolute time is calculated by using the 100 kHz counter value as a coarse clock. The dead time is 5 microseconds (worst case for 16 bits equal to 1) plus the time for the event data. Sixteen input channels are available or the event data.

  • Page 44: Index

    INDEX Symbols PASS 4300B 8007A 8025 8901A Internal Tester BUSY 28, 38 BUSY Output 15, 24, 31, 34 LabView™ Support Cables Maintenance Agreements Flat Multiwire Maximum Time Range 23, 31 Single Twisted Pair Measured Pulse Interval (MPI) 15, 24, 28, 31, 34 Twisted-pair Multiwire MTD133 23, 28, 31...

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