Trigger Outputs - LeCroy 3377 Operator's Manual

TRIGGER OUTPUTS

Trigger Outputs in the
Common Stop Modes
36
The eight prompt OR outputs are stretched (one shots) and delayed
(pipeline delay) using digital techniques. The trigger output pulse width
and delay can be selected, in increments as small as 25 nsec. The
output pulses have a jitter with respect to the input of up to 1 clock
period. This is due to the synchronous digital one shot and delay line
implemented in the gate array chip. The trigger outputs are latched for
the duration of the MPI signal, which begins at the common STOP time.
If MPI is set to zero, no latching takes place.
The leading edge of the OR of 4 inputs asynchronously triggers a digital
one shot. The width is selected from 1 to 16 clock periods. The clock is
selected from 10, 20 and 40 MHz (25 nsec to 100 nsec period), or an
external clock which must be less than 40 MHz. The differential ECL
external clock input is on the trigger connector, pins 19 and 20. The one
shot is retriggerable after one full clock period after the input trigger. If a
second trigger arrives during an output pulse, the output pulse is
extended.
The pipeline delay is adjustable from 0 to 15 clock periods, using the
same clock as the one shot. If zero delay is selected the outputs have
the same leading edge time as the OR, but the width displays the jitter
due to the clock. If a non zero delay is selected, both the leading and
trailing edges are synchronized with the clock, not with the input.
The trigger output data path includes a transparent latch. These latches
are transparent during normal acquisition and are latched by the MPI
(measure pause interval) which has the leading edge time of the com-
mon STOP input. The outputs remain latched until the end of MPI. If the
MPI is set to 0 (no MPI) then the latches remain transparent