Clock Multiplier Selection (Fid[3:0]); Processor Warm Reset Requirements; Northbridge Reset Pins - AMD AX1800DMT3C - Athlon XP 1.53 GHz Processor Datasheet

AMD Athlon™ XP Processor Model 6 Data Sheet
Clock Multiplier
Selection (FID[3:0])
8.2

Processor Warm Reset Requirements

Northbridge Reset
Pins
46
Preliminary Information
The chipset samples the FID[3:0] signals in a chipset-specific
manner from the processor and uses this information to
determine the correct Serial Initialization Packet (SIP). The
chipset then sends the SIP information to the processor for
configuration of the AMD Athlon system bus for the clock
multiplier that determines the processor frequency indicated
by the FID[3:0] code. The SIP is sent to the processor using the
SIP protocol. This protocol uses the PROCRDY, CONNECT, and
CLKFWDRST signals, that are synchronous to SYSCLK.
For more information about FID[3:0], see "FID[3:0] Pins" on
page 70.
Serial Initialization Packet (SIP) Protocol. Refer to AMD Athlon™ and
AMD Duron™ System Bus Specification, order# 21902 for details
of the SIP protocol.
RESET# cannot be asserted to the processor without also being
asserted to the Northbridge. RESET# to the Northbridge is the
same as PCI RESET#. The minimum assertion for PCI RESET#
is one millisecond. Southbridges enforce a minimum assertion
of RESET# for the processor, Northbridge, and PCI of 1.5 to 2.0
milliseconds.
Signal and Power-Up Requirements
24309E—March 2002
Chapter 8