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24309E—March 2002
4.2
Connect and Disconnect Protocol
Connect Protocol
Chapter 4
Preliminary Information
Significant power savings of the processor only occur if the
proc essor is disconnected from the system bus by the
Northbridge while in the Halt or Stop Grant state. The
Northbridge can optionally initiate a bus disconnect upon the
receipt of a Halt or Stop Grant special cycle. The option of
disconnecting is controlled by an enable bit in the Northbridge.
If the Northbridge requires the processor to service a probe
after the system bus has been disconnected, it must first
initiate a system bus connect.
In addition to the legacy STPCLK# signal and the Halt and Stop
Grant special cycles, the AMD Athlon system bus connect
protocol includes the CONNECT, PROCRDY, and CLKFWDRST
signals and a Connect special cycle.
AMD Athlon system bus disconnects are initiated by the
Northbridge in response to the receipt of a Halt or Stop Grant.
Reconnect is initiated by the processor in response to an
interrupt for Halt or STPCLK# deassertion. Reconnect is
initiated by the Northbridge to probe the processor.
The Northbridge contains BIOS programmable registers to
enable the system bus disconnect in response to Halt and Stop
Grant special cycles. When the Northbridge receives the Halt or
Stop Grant special cycle from the processor and, if there are no
outstanding probes or data movements, the Northbridge
deasserts CONNECT a minimum of eight SYSCLK periods after
the last command sent to the processor. The processor detects
the deassertion of CONNECT on a rising edge of SYSCLK and
deasserts PROCRDY to the Northbridge. In return, the
N o r t h b r i d g e a s s e r t s C L K F W D R S T i n a n t i c i p a t i o n o f
reestablishing a connection at some later point.
Note: The Northbridge must disconnect the processor from the
AMD Athlon system bus before issuing the Stop Grant
special cycle to the PCI bus or passing the Stop Grant special
cycle to the Southbridge for systems that connect to the
Southbridge with HyperTransport™ technology.
This note applies to current chipset implementation—
alternate chipset implementations that do not require this
are possible.
Power Management
AMD Athlon™ XP Processor Model 6 Data Sheet
13
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