AMD AX1800DMT3C - Athlon XP 1.53 GHz Processor Datasheet page 28

AMD Athlon™ XP Processor Model 6 Data Sheet
STPCLK#
PROCRDY
CONNECT
CLKFWDRST
Figure 5. Exiting the Stop Grant State and Bus Connect Sequence
16
Preliminary Information
Figure 5 shows the signal sequence of events that takes the
processor out of the Stop Grant state, connects the processor to
the AMD Athlon system bus, and puts the processor into the
Working state.
The following sequence of events removes the processor from
the Stop Grant state and connects it to the system bus:
1. The Southbridge deasserts STPCLK#, informing the
processor of a wake event.
2. When the processor recognizes STPCLK# deassertion, it
exits the low-power state and asserts PROCRDY, notifying
the Northbridge to connect to the bus.
3. The Northbridge asserts CONNECT.
4. The Northbridge deasserts CLKFWDRST, synchronizing the
forwarded clocks
Northbridge.
5. The processor issues a Connect special cycle on the system
bus and resumes operating system and application code
execution.
Power Management
between the processor
24309E—March 2002
and the
Chapter 4