Intel® E7320 / E7525 Chipset - Intel SE7525RP2 Technical Manual

Intel® Server Board SE7320EP2 / Intel® Server Board SE7525RP2 TPS
Functional Architecture
3.1.2.4 DRAM ECC
The ECC used for DRAM provides Intel® x4 SDDC technology for x4 SDRAMs. DRAMs that
are x8 use the same algorithm but will not have Intel x4 SDDC technology, since at most only
four bits can be corrected with this ECC.
The method provides more ECC bits so each ECC word can correct more than a single-bit
failure. This is possible because different mathematical algorithms provide multiple-bit
correction with the right number of data bits and ECC bits. For example, a 144-bit ECC word
that consists of 128 data bits and 16 ECC bits can be used to correct up to 4-bit errors within
certain bit fields of data. These four bits must be adjacent, not random. Even though the ratio of
the ECC bits to data bits is the same as the previous example (16/128 vs. 8/64), the longer ECC
word allows for a correction and detection algorithm that is more efficient.
3.2 Intel® E7320 / E7525 Chipset
The Intel Server Boards SE7320EP2 and SE7525RP2 are designed around the Intel E7320 /
E7525 chipset. The chipset provides an integrated I/O bridge and memory controller, and a
flexible I/O subsystem core (PCI Express). This is targeted for multiprocessor systems and
standard high-volume servers. The chipset consists of two components:
MCH: Memory Control Hub. The MCH accepts access requests from the host
(processor) bus and directs those accesses to memory or to one of the PCI buses. The
MCH monitors the host bus, examining addresses for each request. Accesses may be
directed to a memory request queue for subsequent forwarding to the memory
subsystem, or to an outbound request queue for subsequent forwarding to one of the
PCI buses. The MCH also accepts inbound requests from the 6300ESB ICH. The MCH
is responsible for generating the appropriate controls to control data transfer to and from
memory.
6300ESB ICH: The 6300ESB ICH controller has several components. It provides the
interface for a 32-bit/33-MHz PCI bus and the interface for a 64-bit/66MHz PCI-X bus.
The 6300ESB ICH can be both a master and a target on that PCI bus. The 6300ESB
ICH also includes a USB 2.0 controller and an IDE controller. The 6300ESB ICH is also
responsible for much of the power management functions, with ACPI control registers
built in. The 6300ESB ICH also provides a number of GPIO pins and has the LPC bus to
support low speed legacy I/O.
The MCH and 6300ESB ICH chips provide the pathway between processor and I/O systems.
The MCH is responsible for accepting access requests from the host (processor) bus, and
directing all I/O accesses to one of the PCI buses or legacy I/O locations. If the cycle is directed
to one of the PCI Express segments, the MCH communicates with the PCI Express Devices
(add-in card, on board devices) through the PCI Express interface. If the cycle is directed to the
6300ESB ICH, the cycle is output on the MCH's 8-bit HI 1.5 bus.
The E7320 MCH supports one x8 port configuration PCI Express interface. The E7525MCH
supports one x8 port and one x16 port configuration PCI Express interface. The x8 interface is
capable of logically dividing into separate x4 interface. Each with half the bandwidth of x8
interface and fully compliant to the specification. Maximum theoretical peak bandwidth on each
x8 PCI Express interfaces of 2.5Gb/s in each direction simultaneously, for 5 Gb/s per port.
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Intel order number D24635-001
Revision 1.0