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Intel Desktop Board D865GSA Technical Product Specification
1.5.3
USB
The board supports up to eight USB 2.0 ports, supports UHCI and EHCI, and uses
UHCI- and EHCI-compatible drivers.
The ICH5 provides the USB controller for all ports. The port arrangement is as follows:
•
Four ports are implemented with stacked back panel connectors, adjacent to the
audio connectors
•
Four ports are routed to two separate front panel USB connectors
NOTE
Computer systems that have an unshielded cable attached to a USB port may not meet
FCC Class B requirements, even if no device is attached to the cable. Use shielded
cable that meets the requirements for full-speed devices.
For information about
The location of the USB connectors on the back panel
The location of the front panel USB connectors
1.5.4
IDE Support
The board provides four IDE interface connectors:
•
Two Parallel ATA IDE connectors, which support a total of four devices (two per
connector)
•
Two Serial ATA IDE connectors, which support one device per connector
1.5.4.1
Parallel ATA IDE Interfaces
The ICH5's Parallel ATA IDE controller has two independent bus-mastering Parallel ATA
IDE interfaces that can be independently enabled. The Parallel ATA IDE interfaces
support the following modes:
•
Programmed I/O (PIO): processor controls data transfer.
•
8237-style DMA: DMA offloads the processor, supporting transfer rates of up to
16 MB/sec.
•
Ultra DMA: DMA protocol on IDE bus supporting host and target throttling and
transfer rates of up to 33 MB/sec.
•
ATA-66: DMA protocol on IDE bus supporting host and target throttling and
transfer rates of up to 66 MB/sec. ATA-66 protocol is similar to Ultra DMA and is
device driver compatible.
•
ATA-100: DMA protocol on IDE bus allows host and target throttling. The ICH5's
ATA-100 logic can achieve read transfer rates up to 100 MB/sec and write transfer
rates up to 88 MB/sec.
NOTE
ATA-66 and ATA-100 are faster timings and require a specialized cable to reduce
reflections, noise, and inductive coupling.
30
Refer to
Figure 10, page 53
Figure 11, page 54
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