Performance Specifications - LSIS XBC-DP32U User Manual

Chapter 2 System Configuration

3.4 Performance specifications

3.4.1 Common performance specifications for CPU
The high performance XGB basic unit's common performance specifications for CPU are as below.
Items
Program control metho
I/O control method
Program language
Number of Basic
instructions Application
Processing speed
(Basic instruction)
Program capacity
Max. I/O points
Data area
File register
Total program
Initial task
Cyclic task
Initial I/O task
task
Internal device task Max 16
High Speed
Counter task
Operation mode
Self-diagnosis function
Program port
Back-up method
Internal consumption current
Weight
3-10
XBC- XBC-
DN32U DR28U
Cyclic execution of stored program, Time-driven interrupt,
Process-driven interrupt
Batch processing by simultaneous scan (Refresh method),
Directed by program instruction
Ladder Diagram, Instruction List
28
677
60 ㎱/step
32Kstep
(Main + Expansion 10 stages)
P P00000 ~ P2047F(32,768 point)
M M00000 ~ M2047F(32,768 point)
K K00000 ~ K8191F(131,072 point)
L L00000 ~ L4095F (65,536 point)
F F00000 ~ F2047F (32,768 point)
T 100ms, 10ms, 1ms: T0000 ~ T2047 (2,048 point)
C C000 ~ C2047 (2,048 point)
S S00.00 ~ S127.99
D D00000 ~ D19999(20000word)
U U00.00 ~ U0B.31 (384 word)
Z Z000~Z127 (128 word)
N N0000~N10239(10,240 word)
RAM area 2 block (R0 ~ R16,383)
R
FLASH area : 4 block (128Kbyte)
256
1
Max 16
Max 8
Max 8
RUN, STOP, DEBUG
Detects errors of scan time, memory, I/O and power supply
USB 1 channel
Latch area setting in basic parameter
700㎃ 990㎃
571g 630g
Specifications
XBC- XBC- XBC-
DN32UA DR28UA DN32UP
780㎃ 1,040㎃ 1,250㎃
683g 732g 673g
XBC- Remark
DR28UP
Input/Ouput
Link
Flag
Timer
Counter
Step
Data register
Analog Data
1,550㎃
722g