1. The default setting is in bold.
2. PB8 signal is supplied by VDDMMC. Make sure to provide 3.3 V on VDDMMC. Refer to
Three possibilities to force VDDMMC to 3.3 V:
1. Default configuration: Software control (without hardware modification). In this case, the user must follow
the hardware configuration described in
–
Set 3V3_SW at 3.3 V by software: 3V3_SW_ENABLE (MFX IO0) = 1 (3V3_SW = ON).
2. Hardware modification to force 3V3_SW to be always ON. If the user prefers the 3V3_SW power supply to be
always ON:
–
Remove SB34 or set MFX IO0 in high‑impedance mode (R130 pull-up resistor forces the enable of U14
LDO).
Remember:
In this configuration, the user cannot switch off the 3.3 V supply for SDIO2.
3. Hardware modification to force VDDMMC to 3.3 V (3V3_AO). If the user wants the VDDMMC MCU pin to
remain always at 3.3 V without controlling MFX IO0:
–
Remove SB14 and fit SB15 to connect this pin to the 3V3_AO power supply.
Remember:
In this configuration, the user cannot use SDIO2 at 1.8 V.
SDIO2 configuration (VDDMMC = 1V8_SW or 3V3_SW)
3V3_SW, 1V8_SW, and VDDMMC signals are set up to allow controlling various use cases with the SDIO2
interface, including power OFF sequence, automatic detection of a UHS1 SD card, and switch from 3.3 to 1.8 V.
Refer to
Section
Pin name
PD6
PD7
PG9
PG10
PG11
PG12
For the SD card 2 (SDIO2) interface, to control independently 1V8_SW, 3V3_SW, and VDDMMC, it is necessary
to control the following GPIOs with software:
•
SD_LDO_SEL (PG6)
•
3V3_SW_ENABLE (MFX IO0)
•
1V8_SW_ENABLE (MFX IO8)
Furthermore, the user must follow the hardware configuration described in
UM2662 - Rev 4
Table 14.
VDDMMC default hardware configuration for 3.3 V only functions
Signal name
OCSPI1_NCS (PG6)
3V3_SW_ENABLE (MFX IO0)
1V8_SW_ENABLE (MFX IO8)
6.5.3.
Table 15.
SDIO2 pins supplied by VDDMMC (1.8 or 3.3 V)
Setting
JP23
SB34
SB29
Table
14:
Pin function
SDIO2_CK
SDIO2_CMD
SDIO2_D0
SDIO2_D1
SDIO2_D2
SDIO2_D3
UM2662
Hardware layout and configuration
VDDMMC = '3.3 V only'
[1-2]
(2)
ON
ON
(2)
Section
6.5.5.
Table
16.
(1)
page 25/102
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