ZiLOG Z-80 SIB User Manual page 50

Bit 7=1
The channel
is
enabled
to
generate
an interrupt request
sequence every
time the
down counter reaches
a
zero-count condition.
To set this bit
to
1
in
any
of
the four
channel control registers necessitates that an
interrupt vector also
be
written to the CTC before
operation
begins,
Channel interrupts may
be
programmed
in
either counter mode
or
timer mode.
If an
updated
channel control word
is
written
to
a
channel already in
operation with
bit
7
set, the
interrupt enable selection
will not
be
retroactive
to
a
preceding zero-count
,
.
condition.
Bit
7=0
Channel interrupts disabled.
Bit 6=1
Counter mode selected. The down counter
is
decremented
by each
triggering edge
of the
external clock
(CLK/TRG)
input. The prescaler
is
not used.
Bit
6=0
Timer mode selected. The prescaler
is clocked by the
system clock
,
and the
output
of the
prescaler
in
turn,
clocks
the
down counter.
The output
of the down counter
(the
channel's ZC/TO output)
is
a
uniform pulse train
of
periods given by
the
product
t *
P *
TC
where
t is
the
period of system clock
,
P is the
prescaler factor
of 16 or 256, and TC
is
the time
constant data
word.
Bit 5=1
(Defined
for timer mode only.) Prescaler factor
is 256.
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