ZiLOG Z-80 SIB User Manual page 46

Mi-
Machine Cycle One Signal from CPU (input, active
low)
When Ml-
is
active
and the
RD- signal
is
active, the CPU
is
fetching
an
instruction from memory. When Ml-
is
active and
the lORQ- signal
is
active, the CPU
is
acknowledging
an
interrupt, alerting the CTC
to
place
an
interrupt vector on
the Z80 data bus
if it
has daisy chain priority and one of
its
channels has requested
an
interrupt.
lORQ-
Input/Output Request from CPU
(input,
active
low)
The lORQ- signal
is
used
in
conjunction with
the CE- and RD-
signals
to
transfer data and channel control words between
the Z80-CPU and the CTC. During
a
CTC
write cycle, lORQ-
and
CE- must be true and RD- false.
The CTC does not receive
a
specific write signal, instead generating
its
own internally
from the inverse
of
a
valid RD- signal.
In a
CTC read cycle,
IORQ-, CE-, and RD- must be active
to
place the contents
of
the down counter on the Z80 data bus.
If
lORQ- and Ml- are
both true,
the CPU
is
acknowledging
an interrupt request, and
the
highest-priority interrupting channel will place
its
interrupt vector
on the Z80
data bus.
RD-
Read Cycle Status from the CPU (input, active
low)
The RD- signal
is
used
in
conjunction with
the
lORQ- and CE-
signals
to
transfer data and channel control words between
the Z80-CPU and the CTC. During
a
CTC write cycle, lORQ- and
CE- must
be
true and RD- false.
The CTC does not receive
a
specific write signal, instead generating
its
own internally
from the inverse of
a
valid RD- signal.
In a
CTC read cycle,
IORQ-, CE-, and RD-
must
be active
to
place the contents of
the down counter on the Z80 data bus.
38