ZiLOG Z-80 SIB User Manual page 31

Only
a
single address
is
set aside
for
mode control
bytes, command bytes, and sync character bytes.
For
this
to be
possible, logic internal
to the
chip directs
control information
to its
proper destination based
on
the
sequence
in
which
it is
received.
Following
a
reset, the first
control code output
is
interpreted as
a
mode control.
If
the
mode control specifies synchronous
operation, then the next one
or
two
bytes
(as
determined
by the mode byte) output
as
control codes will
be
interpreted
as sync
characters
,
For
either asynchronous
or
synchronous operation,
the next byte output
as
a
control code
is
interpreted
as
a
command
,
All
subsequent bytes output
as
control codes
are
interpreted
as
commands.
There are two ways
in
which control logic
may return to
anticipating
a
mode control input;
following an
external reset signal
or
following an
internal reset command
,
Mode Control Codes
The USART interprets mode control codes
as
illustrated
in
Figures 3.6.2,2 and 3,6.2.3,
Control code bits and
1
determine whether synchronous
or
asynchronous operation
is
specified. A
non-zero
value
in
bits and
1
specifies asynchronous operation
and
defines
the
relationship between the data transfer
baud rate and receiver
or
transmitter clock
rate.
Asynchronous serial data may be received
or
transmitted
on
every clock pulse,
on every 16th clock pulse,
or on
every 64th clock pulse. A zero
in
both bits and
1
defines
the mode of operation
as
synchronous.
For synchronous and asynchronous modes, control bits
2
and
3
determine
the
number
of
data bits which will be
present
in
each data character.
For synchronous and
asynchronous modes, bits
4
and
5
deter-
mine whether there will
be
a
parity bit
in
each character,
and
if so
,
whether odd
or
even parity will
be
adopted.
Thus,
in
synchronous mode,
a
character will consist of five,
six, seven,
or
eight data bits, plus
an
optional parity
bit.
In
asynchronous mode, the data unit will consist of five,
six, seven, or eight data bits,
an
optional parity bit,
a
preceeding start
bit, plus
1, 1
1/2, or
2
trailing stop bits.
Interpretation
of
subsequent bits differs
for
synchronous
or
asynchronous modes.
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