ZiLOG Z-80 SIB User Manual page 44

TxRDY signals the processor that
the
transmit character
buffer
is
empty and that the USART can accept
a
new character
for transmission
.
RxRDY signals
the
processor that
a
completed character
is
holding
in
the
receive character buffer register
for
transfer
to the
processor.
TxE signals the processor that
the
transmit register
is
empty.
PE
is
the parity error signal indicating
to the
CPU that
the
character stored
in
the
receive character buffer was received
with
an
incorrect number of binary
"1"
bits. The PE flag
is
cleared by setting the ER bit
in
a
subsequent command
instruction,
PE being set does not inhibit USART operation.
OE
is the
receiver overrun error, OE
is set
whenever
a
byte
stored
in
the
receiver character register
is
overwritten with
a
new byte before being transferred
to the
processor. The OE
flag
is
cleared by setting the ER bit
in
a
subsequent command
instruction. OE being set does not inhibit USART operation.
FE
is
the
character framing error which indicates that
the
asynchronous mode byte stored
in the
receiver character
buffer was received with an incorrect character bit format
(stop bit), as specified by the current mode. The FE flag
is
cleared by setting
the
ER bit
in
a
subsequent command
instruction. FE being set does not inhibit USART operation.
3.7
CTC Operation
3.7,1 CTC Pin Description
D7-D0
Z80-CPU Data Bus (bi-directional, tri-state)
This bus
is
used
to
transfer
all data and
command words
between
the
Z80-CPU and
the Z80-CTC,
There are
8
bits on
this bus,
of
which
DO
is
the least significant.
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