ZiLOG Z-80 SIB User Manual page 27

Receive data
(RxD)
Composite serial data
is
received
at
this input and
converted
to
a
parallel format; sync, start/stop,
and
parity are
checked, and then the assembled byte
is
prepared
for
buffering to the Z80,
For
communications requiring
less than
8
bits per character, the extra bits are set
to
logical
"zero"
Receiver Ready
(RR)
The RR output signal indicates
to the processor that data has
been shifted into the receiver buffer from the
receiver
section and may be read. The signal
is
active high and will
be
reset when the buffer
is
read by the processor. RR can
be
activated only
if
the receiver enable
(RxE)
has been set
in
the
command register, even though
the
receiver may
be
running.
If
the
processor does
not read the receiver buffer
before
the
next character
is
shifted from the receiver
section, then
an
overrun error will
be
indicated
in
the
status buffer.
RR can
be
tested by checking bit
1
of the status register
for
polling operation
or
the RR signal can be used
to
generate
an
interrupt. On the SIB, CTCl
is
used to
receive
the
active
high RR signal from the USART
to
decrement
a
counter from
1
to
0,
and
consequently, provide
a
Z80
mode
2
interrupt
vector
Receiver Clock
(RxC-)
The receiver clock
is
the rate at which
the
incoming
character
is
received.
In the
asynchronous mode, the RxC
frequency may
be
1,
16, or 64
times the actual baud rate, but
in
the
synchronous mode,
the RxC-
frequency must equal
the
baud
rate.
Bits
and
1
in
the
mode instruction select
asynchronous
at Ix, 16x, or 64x or
synchronous operation
at
Ix the baud rate.
Unlike TxC-, data
is
sampled by the
USART
on the rising edge
of RxC-.
Since the USART will frequently be handling both
the
reception
and
transmission
for
a
given
link, the
receive
and
transmit baud rates will
be the same.
RxC- and TxC- then
require
the same
frequency and may
be
tied together and
connected
to
a
single clock source
or
baud rate generator.
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