ZiLOG Z-80 SIB User Manual page 53

Time Constant Register
D7 D6
D5 D4 D3 D2 Dl DO
TC7 TC6 TC5
TC4
TC3
TC2 TC2 TCO
MSB LSB
The Z80-CTC has been designed
to
operate with
the
Z80-CPU
programmed
for
mode
2
interrupt response. Under the
requirements of this
mode, when
a
CTC channel requests an
interrupt and
is
acknowledged,
a
16-bit pointer must
be
formed
to
obtain
a
corresponding interrupt service routine
starting address from
a
table
in
memory. The upper
8
bits of
this pointer are provided by the CPU's
I
register, and
the
lower
8
bits
of the
pointer
are
provided by the CTC
in the
form of an interrupt vector unique
to the
particular channel
that requested the interrupt.
MODE
2
INTERRUPT OPERATION
INTERRUPT
SERVICE
ROUTINE
STARTING
ADDRESS
TABLE
LOW ORDER
HIGH ORDER
Desired starting address
Pointed
to by:
I
REG
7
BITS FROM
CONTENTS
PERIPHERAL
The high order
5
bits of this interrupt vector must
be
written to the CTC
in
advance
as
part
of the
initial
programming sequence
.
To do
so
,
the CPU must
wr ite to the
I/O port
addresses corresponding to the CTC channel
0,
just
as
it
would
if a
channel control word were being written
to
that channel, except that bit of the
word being written
must contain
a
.
(As
expla
ined
above
in
Section
3.1, if
bit
of
a
word written
to
a
channel were
set to
2,
the word
would
be
interpreted
as
a
channel control word,
so
a
in
bit
signals the CTC to load the incoming word into the
interrupt vector register.) Bits
1
and
2,
however, are not
used when loading this vector. At the time when the
interrupting channel must place the interrupt vector
on the
Z80 data bus, the
interrupt control logic of the
CTC
automatically supplies
a
binary
code
in
bits
1
and
2
identifying which
of the four
CTC channels
is
to
be serviced.
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