ZiLOG Z-80 SIB User Manual page 45

CSI,CS0
Channel Select
(input,
active
high)
These pins form
a
2-bit binany address code
for
selecting
one
of the
four
independent CTC channels
for an
I/O write or
read, (See
truth table below.)
CSl cso
ChO
Chi
1
Ch2
1
Ch3
1 1
CE-
Chip Enable
(input,
active
low)
A low level
on
this pin enables the CTC
to
accept control
words, interrupt vectors,
or
time constant data words from
the Z80
data bus during
an I/O
write cycle,
or to
transmit
the
contents of the down counter
to
the CPU during an I/O
ready cycle.
In
most applications, this signal
is
decoded
from the
8
least significant bits
of the
address bus for any
of the four I/O
port addresses that
are
mapped
to the four
counter /timer channels
Clock
(phi)
System Clock
(input)
This single-phase clock
is
used by the CTC
to
synchronize
certain signals internally.
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