ZiLOG Z-80 SIB User Manual page 49

Loading
the
Channel Control Register
To load
a
channel control word,
the
CPU performs
a
normal I/O
write sequence to the
port address corresponding
to the
CTC
channel.
Two CTC input pins, namely CSO and CSl, are used
to
form
a
2-bit binary address
to
select one
of four
channels
within
the device.
In
many system architectures, these two
input pins are connected
to
address bus lines AO and Al,
respectively,
so
that the four channels
in
a
CTC device will
occupy contiguous I/O port addresses. A word written
to
a
CTC channel will
be
interpreted
as
a
channel control word,
and
loaded into
the
channel control register, with bit
being
a
logic
1.
The other seven bits of this word select
operating modes and
conditions
as
indicated
in
the
diagram
below.
Following
the
diagram,
the
meaning
of
each bit will
be
discussed
in
detail.
D7
D6
D5 D4 D3 D2 Dl DO
Interrupt
Enable
Mode Range* Slope Trigger*
Load
Time
Constant
Reset
1
*
Used
in
Timer Mode only
I
1
I
41