Operation Flow; Error Flags; Clock Error - GigaDevice Semiconductor GD32F5 Series User Manual

The 32-bit value of LFSR will be transferred into TRNG_DATA register after a sufficient
number of seeds have been sent to the LFSR.
At the same time, the analog seed and TRNG_CLK clock are monitored. When an analog
seed error or a clock error occurs, the corresponding status bit in TRNG_STAT will be set and
an interrupt will generate if the TRNGIE bit in TRNG_CTL is set.

Operation flow

10.3.1.
The following steps are recommended for using TRNG block:
1). Enable the interrupt as necessary, so that when a random number or an error occurs, an
interrupt will be generated.
2). Enable the TRNGEN bit.
3). When an interrupt occurs, check the status register TRGN_STAT, if SEIF=0, CEIF=0 and
DRDY=1, then the random value in the data register could be read.
As required by the FIPS PUB 140-2, the first random data in data register should be saved
but not be used. Every subsequent new random data should be compared to the previously
random data. The data can only be used if it is not equal to the previously one.

Error flags

10.3.2.

Clock Error

When the TRNG_CLK frequency is lower than the 1/16 of HCLK, the CECS and CEIF bit will
be set. In this case, the application should check TRNG_CLK and HCLK frequency
configurations and then clear CEIF bit. Clock error will not impact the previous random data.
Seed Error
When the analog seed is not changed or always changing during 64 TRNG_CLK periods, the
SECS and SEIF bit will be set. In this case, the random data in data register should not be
used. The application needs to clear the SEIF bit, then clear and set TRNGEN bit for restarting
the TRNG.
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