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GigaDevice Semiconductor GD32F1 0 Series User Manual

GigaDevice Semiconductor GD32F1 0 Series User Manual

Arm cortex-m3 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32F1x0

ARM

Cortex

-M3 32-bit MCU

®

®

User Manual

Revision 3.6

(Jul. 2022)

Table of Contents

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Summary of Contents for GigaDevice Semiconductor GD32F1 0 Series

Page 1 GigaDevice Semiconductor Inc. GD32F1x0 Cortex -M3 32-bit MCU ® ® User Manual Revision 3.6 (Jul. 2022)
Page 2: Table Of Contents
GD32F1x0 User Manual Table of Contents Table of Contents ......................2 List of Figures ......................17 List of Tables ........................ 24 1. System and memory architecture ................ 27 ARM Cortex-M3 processor ..................27 1.1. System architecture ....................28 1.2. Memory map ......................30 1.3.
Page 3 GD32F1x0 User Manual 2.3.10. Page erase/Program protection .................... 55 2.3.11. Security protection ........................ 56 Register definition ..................... 57 2.4. 2.4.1. Wait state register (FMC_WS) ....................57 2.4.2. Unlock key register (FMC_KEY) ................... 57 2.4.3. Option bytes unlock key register (FMC_OBKEY) ..............58 2.4.4.
Page 4 GD32F1x0 User Manual 4.3.6. AHB enable register (RCU_AHBEN) .................. 106 4.3.7. APB2 enable register (RCU_APB2EN) ................107 4.3.8. APB1 enable register (RCU_APB1EN) ................109 4.3.9. Backup domain control register (RCU_BDCTL) ..............113 4.3.10. Reset source /clock register (RCU_RSTSCK) ..............116 4.3.11.
Page 5 GD32F1x0 User Manual 6.3.8. GPIO locking function ......................145 6.3.9. GPIO single cycle toggle function ..................145 Register definition ....................146 6.4. 6.4.1. Port control register (GPIOx_CTL, x=A..D,F) ..............146 6.4.2. Port output mode register (GPIOx_OMODE, x=A..D,F) ............. 147 6.4.3. Port output speed register (GPIOx_OSPD, x=A..D,F) ............
Page 6 GD32F1x0 User Manual Register definition ....................174 8.5. 8.5.1. Interrupt flag register (DMA_INTF) ..................174 8.5.2. Interrupt flag clear register (DMA_INTC) ................174 8.5.3. Channel x control register (DMA_CHxCTL) ............... 175 8.5.4. Channel x counter register (DMA_CHxCNT) ..............177 8.5.5. Channel x peripheral base address register (DMA_CHxPADDR) ........
Page 7 GD32F1x0 User Manual 10.5.1. Status register (ADC_STAT) ....................203 10.5.2. Control register 0 (ADC_CTL0) ..................203 10.5.3. Control register 1 (ADC_CTL1) ..................206 10.5.4. Sampling time register 0 (ADC_SAMPT0) ................. 208 10.5.5. Sampling time register 1 (ADC_SAMPT1) ................. 210 10.5.6. Watchdog high threshold register (ADC_WDHT) ..............
Page 8 GD32F1x0 User Manual Comparator (CMP) .................... 233 12.1. Overview ....................... 233 12.2. Characteristics ..................... 233 12.3. Function overview ....................233 12.3.1. CMP clock and reset ......................235 12.3.2. CMP I/O configure ......................235 12.3.3. CMP operating mode ......................235 12.3.4. CMP hysteresis ........................
Page 9 GD32F1x0 User Manual 14.3.15. RTC power saving mode management ................267 14.3.16. RTC interrupts ......................... 267 14.4. Register definition ....................268 14.4.1. Time register (RTC_TIME) ....................268 14.4.2. Date register (RTC_DATE) ....................268 14.4.3. Control register (RTC_CTL) ....................269 14.4.4. Status register (RTC_STAT) ....................
Page 10 GD32F1x0 User Manual 15.4.4. Function overview ....................... 402 15.4.5. TIMERx registers(x=14) ...................... 418 General level4 timer (TIMERx, x=15,16) .............. 438 15.5. 15.5.1. Overview ..........................438 15.5.2. Characteristics ........................438 15.5.3. Block diagram ........................438 15.5.4. Function overview ....................... 439 15.5.5. TIMERx registers(x=15,16) ....................
Page 11 GD32F1x0 User Manual 17.4.3. Control register 2 (USART_CTL2) ..................503 17.4.4. Baud rate generator register (USART_BAUD) ..............506 17.4.5. Prescaler and guard time configuration register (USART_GP) .......... 506 17.4.6. Receiver timeout register (USART_RT) ................507 17.4.7. Command register (USART_CMD) ..................508 17.4.8.
Page 12 GD32F1x0 User Manual 19.2.1. SPI characteristics ......................545 19.2.2. I2S characteristics ......................545 SPI function overview ..................546 19.3. 19.3.1. SPI block diagram ....................... 546 19.3.2. SPI signal description ......................546 19.3.3. SPI clock timing and data format ..................547 19.3.4.
Page 13 GD32F1x0 User Manual 20.3.7. HDMI-CEC interrupt ......................592 Register definition ....................593 20.4. 20.4.1. Control register (CEC_CTL) ....................593 20.4.2. Configuration register (CEC_CFG) ..................594 20.4.3. Transmit data register (CEC_TDATA) ................. 595 20.4.4. Receive data register (CEC_RDATA) ................. 596 20.4.5. Interrupt Flag Register (CEC_INTF) ...................
Page 14 GD32F1x0 User Manual Function overview ....................618 22.6. 22.6.1. USB endpoints ........................618 22.6.2. Operation procedure ......................621 22.6.3. USB events and interrupts ....................624 22.6.4. Operation guide ........................625 Register definition ....................628 22.7. 22.7.1. USBD control register (USBD_CTL) ................... 628 22.7.2.
Page 15 GD32F1x0 User Manual 24.4.2. Bias trimming register for normal mode (OPA_BT) ............656 24.4.3. Bias trimming register for low power mode (OPA_LPBT) ........... 657 Programmable Current and Voltage Reference (IVREF)........ 659 25.1. Overview ....................... 659 25.2. Characteristics ..................... 659 25.3. Function overview ....................
Page 16 GD32F1x0 User Manual 26.4.16. Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) ......693 26.4.17. Filter control register (CAN_FCTL) (Just for CAN0) ............693 26.4.18. Filter mode configuration register (CAN_FMCFG) (Just for CAN0) ....... 694 26.4.19. Filter scale configuration register (CAN_FSCFG) (Just for CAN0) ......... 694 26.4.20.
Page 17: List Of Figures
GD32F1x0 User Manual List of Figures -M3 processor ............28 ® Figure 1-1. The structure of the Cortex Figure 1-2. Series system architecture of GD32F130xx and GD32F150xx devices ..... 29 Figure 1-3. Series system architecture of GD32F170xx and GD32F190xx devices ..... 30 Figure 2-1.
Page 18 GD32F1x0 User Manual Figure 12-2. CMP block diagram of GD32F190xx devices ............ 234 Figure 12-3. CMP hysteresis ....................236 Figure 13-1. Free watchdog timer block diagram ..............245 Figure 13-2. Window watchdog timer block diagram ............252 Figure 13-3. Window watchdog timer timing diagram ............253 Figure 14-1.
Page 19 GD32F1x0 User Manual Figure 15-39. Channel input capture principle ..............349 Figure 15-40. Channel output compare principle (x=0,1,2,3) ..........350 Figure 15-41. Output-compare under three modes ............... 351 Figure 15-42. Timing chart of EAPWM ..................352 Figure 15-43. Timing chart of CAPWM ..................352 Figure 15-44.
Page 20 GD32F1x0 User Manual Figure 15-83. Timing chart of internal clock divided by 1 ............ 469 Figure 15-84. Timing chart of PSC value change from 0 to 2 ..........470 Figure 15-85. Timing chart of up counting mode, PSC=0/2 ..........471 Figure 15-86.
Page 21 GD32F1x0 User Manual Figure 19-6. A typical simplex connection (Master: receive, Slave: transmit) ....551 Figure 19-7. A typical simplex connection (Master: transmit only, Slave: receive) ..551 Figure 19-8. A typical bidirectional connection ..............552 Figure 19-9. Timing diagram of write operation in Quad-SPI mode ........554 Figure 19-10.
Page 22 GD32F1x0 User Manual Figure19-41. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ......................565 Figure 19-42. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ......................565 Figure 19-43. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ......................
Page 23 GD32F1x0 User Manual Figure 26-6. 16-bit filter ......................670 Figure 26-7. 32-bit mask mode filter ..................670 Figure 26-8. 16-bit mask mode filter ..................670 Figure 26-9. 32-bit list mode filter ................... 670 Figure 26-10. 16-bit list mode filter ..................670 Figure 26-11.
Page 24: List Of Tables
GD32F1x0 User Manual List of Tables Table 1-1. Memory map of GD32F130xx and GD32F150xx devices ........31 Table 1-2. Memory map of GD32F170xx and GD32F190xx devices ........33 Table 1-3. Flash module organization ..................36 Table 1-4. Boot modes ........................ 36 Table 2-1.
Page 25 GD32F1x0 User Manual Table 15-8. Slave mode example table ................... 414 Table 15-9. TIMERx(x=14) interconnection ................417 Table 15-10. Complementary outputs controlled by parameters ........448 Table 17-1. USART important pins description ..............482 Table 17-2. Stop bits configuration ..................483 Table 17-3.
Page 26 GD32F1x0 User Manual Table 27-2. List of terms ......................698 Table 28-1. Revision history ..................... 700...
Page 27: System And Memory Architecture
GD32F1x0 User Manual System and memory architecture ® The GD32F1x0 series are 32-bit general-purpose microcontrollers based on the ARM Cortex ® -M3 processor. The Cortex ® -M3 processor includes three AHB buses known as I- Code, D-Code and System buses. All memory accesses of the Cortex ®...
Page 28: System Architecture
GD32F1x0 User Manual ® Figure 1-1. The structure of the Cortex -M3 processor Cortex-M3 processor Interrupts and Nested power control Vectored Interrupt Cortex-M3 core Controller (NVIC) Data Flash Patch Trace Port Watchpoint Breakpoint Interface Unit And Trace (FPB) (TPIU) (DWT) Serial-Wire Or JTAG Instrumentation...
Page 29: Figure 1-2. Series System Architecture Of Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual Figure 1-2. Series system architecture of GD32F130xx and GD32F150xx devices 1.2V TPIU GPIO Ports AHB2: Fma x = 72MHz POR/PDR A, B, C, D, F ARM Cortex-M3 Processor SRAM SRAM : 72MHz Controller IBus Flash : 72MHz Touch Flash Memory...
Page 30: Memory Map
GD32F1x0 User Manual Figure 1-3. Series system architecture of GD32F170xx and GD32F190xx devices 1.8V TPIU GPIO Ports AHB2: Fma x = 72MHz POR/PDR A, B, C, D, F ARM Cortex-M3 Processor SRAM SRAM : 72MHz Controller IBus Flash : 72MHz Touch Flash Memory...
Page 31: Table 1-1. Memory Map Of Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual both located in the same memory address space but in different address ranges. Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte ® address space which is the maximum address range of the Cortex -M3 since it has a 32-bit bus address width.
Page 32 GD32F1x0 User Manual Pre-defined ADDRESS Peripherals Regions 0x4001 2800 - 0x4001 2BFF Reserved 0x4001 2400 - 0x4001 27FF 0x4001 0800 - 0x4001 23FF Reserved 0x4001 0400 - 0x4001 07FF EXTI 0x4001 0000 - 0x4001 03FF SYSCFG+CMP 0x4000 C400 - 0x4000 FFFF Reserved 0x4000 C000 - 0x4000 C3FF Reserved...
Page 33: Table 1-2. Memory Map Of Gd32F170Xx And Gd32F190Xx Devices
GD32F1x0 User Manual Pre-defined ADDRESS Peripherals Regions 0x0000 0000 - 0x07FF FFFF Aliased to Flash or system memory Table 1-2. Memory map of GD32F170xx and GD32F190xx devices Pre-defined ADDRESS Peripherals Regions 0xE000 0000 - 0xE00F FFFF Cortex-M3 internal peripherals External Device 0xA000 0000 - 0xDFFF FFFF Reserved External RAM...
Page 34 GD32F1x0 User Manual Pre-defined ADDRESS Peripherals Regions 0x4000 C400 - 0x4000 FFFF Reserved 0x4000 C000 - 0x4000 C3FF I2C2 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF OPA+IVREF 0x4000 7800 - 0x4000 7BFF 0x4000 7400 - 0x4000 77FF DAC0~1 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF...
Page 35: Bit-Banding
GD32F1x0 User Manual Bit-banding 1.3.1. ® In order to reduce the time of read-modify-write operations, the Cortex -M3 processor provides a bit-banding function to perform a single atomic bit operation. The memory map includes two bit-band regions. These occupy the SRAM and Peripherals respectively. These bit-band regions map each word in an alias region of memory to a bit in a bit-band region of memory.
Page 36: On-Chip Flash Memory
GD32F1x0 User Manual when reading non-initialized locations. On-chip Flash memory 1.3.3. The devices provide up to 64 KB of on-chip flash memory. The flash memory consists of up to 64 KB main flash organized into 64 pages with 1 KB capacity per page and a 3 KB information block for the boot loader.
Page 37 GD32F1x0 User Manual According to the selected boot source, either the main flash memory (original memory space beginning at 0x0800 0000) or the system memory (original memory space beginning at 0x1FFF EC00) is aliased in the boot memory space which begins at the address 0x0000 0000. When the on-chip SRAM whose memory space is beginning at 0x2000 0000 is selected as the boot source, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register.
Page 38: System Configuration Registers (Syscfg)
GD32F1x0 User Manual 1.5. System configuration registers (SYSCFG) SYSCFG base address: 0x4001 0000 System configuration register 0 (SYSCFG_CFG0) 1.5.1. Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to the BOOT0 pin and the BOOT1_n option bit after reset) This register has to be accessed by word(32-bit).
Page 39: System Configuration Register 1 (Syscfg_Cfg1)
GD32F1x0 User Manual USART0_TX_DMA_ USART0_TX DMA request remapping enable 0: Not remap (USART0_TX DMA requests are mapped on DMA channel 1) 1: Remap (USART0_TX DMA requests are mapped on DMA channel 3) ADC_DMA_RMP ADC DMA request remapping enable 0: Not remap (ADC DMA requests are mapped on DMA channel 0) 1: Remap (ADC DMA requests are mapped on DMA channel 1) Reserved Must be kept at reset value...
Page 40 GD32F1x0 User Manual Reserved EXTI3_SS [3:0] EXTI2_SS [3:0] EXTI1_SS [3:0] EXTI0_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI3_SS[3:0] EXTI 3 sources selection X000: PA3 pin X001: PB3 pin X010: PC3 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved...
Page 41: Exti Sources Selection Register 1 (Syscfg_Extiss1)
GD32F1x0 User Manual X100: Reserved X101: PF0 pin X110: Reserved X111: Reserved EXTI sources selection register 1 (SYSCFG_EXTISS1) 1.5.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved EXTI7_SS [3:0] EXTI6_SS [3:0] EXTI5_SS [3:0] EXTI4_SS [3:0] Bits Fields...
Page 42: Exti Sources Selection Register 2 (Syscfg_Extiss2)
GD32F1x0 User Manual X011: Reserved X100: Reserved X101: PF5 pin X110: Reserved X111: Reserved EXTI4_SS[3:0] EXTI 4 sources selection X000: PA4 pin X001: PB4 pin X010: PC4 pin X011: Reserved X100: Reserved X101: PF4 pin X110: Reserved X111: Reserved EXTI sources selection register 2 (SYSCFG_EXTISS2) 1.5.5.
Page 43: Exti Sources Selection Register 3 (Syscfg_Extiss3)
GD32F1x0 User Manual X010: PC10 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved X111: Reserved EXTI9_SS[3:0] EXTI 9 sources selection X000: PA9 pin X001: PB9 pin X010: PC9 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved X111: Reserved EXTI8_SS[3:0] EXTI 8 sources selection X000: PA8 pin...
Page 44: System Configuration Register 2 (Syscfg_Cfg2)
GD32F1x0 User Manual X001: PB15 pin X010: PC15 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved X111: Reserved 11:8 EXTI14_SS[3:0] EXTI 14 sources selection X000: PA14 pin X001: PB14 pin X010: PC14 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved X111: Reserved EXTI13_SS[3:0]...
Page 45: Device Electronic Signature
GD32F1x0 User Manual Reserved SRAM_ LOCK SRAM_P LVD_ PARITY_ Reserved Reserved LOCK ERROR_ LOCK LOCK Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. SRAM_PCEF SRAM parity check error flag This bit is set by hardware when an SRAM parity check error occurs. It is cleared by software by writing 1.
Page 46: Memory Density Information
GD32F1x0 User Manual Memory density information 1.6.1. Base address: 0x1FFF F7E0 The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit). SRAM_DENSITY[15:0] FLASH_DENSITY[15:0] Bits Fields Descriptions 31:16 SRAM_DENSITY SRAM density [15:0] The value indicates the on-chip SRAM density of the device in Kbytes.
Page 47 GD32F1x0 User Manual UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7B4 The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit). UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0...
Page 48: Flash Memory Controller (Fmc)
GD32F1x0 User Manual Flash memory controller (FMC) 2.1. Overview The Flash Memory Controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time within 32K bytes while CPU executes instruction. It also provides page erase, mass erase, and word/half word program for flash memory. 2.2.
Page 49: Read Operations
GD32F1x0 User Manual The Information Block stores the bootloader - this block cannot be programmed or Note: erased by user. Read operations 2.3.2. The flash can be addressed directly as a common memory space. Any instruction fetch and the data access from the flash are through the IBUS or DBUS from the CPU. Unlock the FMC_CTL register 2.3.3.
Page 50: Mass Erase
GD32F1x0 User Manual ENDIE bit in the FMC_CTL register is set, and the ENDF in FMC_STAT register is set. If the target erasing page is being used for fetching codes or accessing data, the software may run out of control. The FMC will not provide any notification when this occurs. Additionally, the page erase operation will be ignored on protected pages.
Page 51: Figure 2-2. Process Of The Mass Erase Operation
GD32F1x0 User Manual  Write the mass erase command by setting MER bit in FMC_CTL register.  Send the mass erase command to the FMC by setting the START bit in FMC_CTL register.  Wait until all the operations have been completed by checking the value of the BUSY bit in FMC_STAT register.
Page 52: Main Flash Programming
GD32F1x0 User Manual Main flash programming 2.3.6. The FMC provides a 32-bit word/16-bit half word programming function which is used to modify the main flash memory contents. The following steps show the word programming operation register access sequence.  Unlock the FMC_CTL register if necessary. ...
Page 53: Option Bytes Erase
GD32F1x0 User Manual Figure 2-3. Process of the word programming operation Start Is the LK bit 0 Unlock the FMC_CTL Is the BUSY bit 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit 0 Finish Option bytes erase 2.3.7.
Page 54: Option Bytes Programming
GD32F1x0 User Manual When the operation is executed successfully, an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL register is set, and the ENDF in FMC_STAT register is set. The end of this operation is indicated by the ENDF bit in the FMC_STAT register. Option bytes programming 2.3.8.
Page 55: Page Erase/Program Protection
GD32F1x0 User Manual Address Name Description [6]: SRAM_PARITY_CHECK 0: Enable sram parity check 1: Disable sram parity check [5]: VDDA_VISOR 0: Disable V monitor 1: Enable V monitor [4]: BOOT1_n 0: BOOT1 bit is 1 1: BOOT1 bit is 0 [3]: Reserved [2]: nRST_STDBY 0: Generate a reset instead of entering standby mode...
Page 56: Security Protection
GD32F1x0 User Manual by set OB_WP [15:0]. Table 2-3. OB_WP bit for pages protected OB_WP bit pages protected OB_WP[0] page 0 ~ page 3 OB_WP[1] page 4 ~ page 7 OB_WP[2] page 8 ~ page 11 OB_WP[14] page 56 ~ page 59 OB_WP[15] page 60 ~ page 63 Security protection...
Page 57: Register Definition
GD32F1x0 User Manual 2.4. Register definition FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved WSCNT[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. WSCNT[2:0] Wait state counter register These bits set and reset by software.
Page 58: Option Bytes Unlock Key Register (Fmc_Obkey)
GD32F1x0 User Manual Write KEY[31:0] with key to unlock FMC_CTL register. Option bytes unlock key register (FMC_OBKEY) 2.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). OBKEY[31:16] OBKEY[15:0] Bits Fields Descriptions 31:0 OBKEY[31:0] FMC_CTL option bytes operation unlock registers These bits are only be written by software Write OBKEY[31:0] with key to unlock option bytes command in FMC_CTL...
Page 59: Control Register (Fmc_Ctl)
GD32F1x0 User Manual software can clear it by writing 1. Reserved Must be kept at reset value. PGERR Program error flag bit When programming to the flash while it is not 0xFFFF, this bit is set by hardware. The software can clear it by writing 1. Reserved Must be kept at reset value.
Page 60: Address Register (Fmc_Addr)
GD32F1x0 User Manual This bit is set by hardware when right sequence written to FMC_OBKEY register. This bit can be cleared by software. Reserved Must be kept at reset value. FMC_CTL lock bit This bit is cleared by hardware when right sequent written to FMC_KEY register. This bit can be set by software.
Page 61: Option Bytes Status Register (Fmc_Obstat)
GD32F1x0 User Manual ADDR[15:0] Bits Fields Descriptions 31:0 ADDR[31:0] Flash command address bits These bits are set by software. ADDR bits are the address of flash erase command Option bytes status register (FMC_OBSTAT) 2.4.7. Address offset: 0x1C Reset value: 0xXXXX XX0X This register has to be accessed by word(32-bit).
Page 62: Wait State Enable Register (Fmc_Wsen)
GD32F1x0 User Manual Reserved OB_WP[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 OB_WP[15:0] Store OB_WP[15:0] of option bytes block after system reset 0: Protection active 1: Unprotected Wait state enable register (FMC_WSEN) 2.4.9. For GD32F130xx and GD32F150xx devices Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 63: Product Id Register (Fmc_Pid)
GD32F1x0 User Manual Reserved Reserved BPEN WSEN Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. BPEN FMC bit program enable register This bit set and reset by software. 0: No effect, write page must check if the flash is “FF” 1: Write page do not check if the flash is FF.
Page 64: Power Management Unit (Pmu)
GD32F1x0 User Manual Power management unit (PMU) 3.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32F1x0 series. The Power management unit (PMU), provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 65: Figure 3-1. Power Supply Overview Of Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual Figure 3-1. Power supply overview of GD32F130xx and GD32F150xx devices Backup Domain Power Switch 3.3V LXTAL BPOR WKUP0 WKUPR BKP PAD WKUP1 PC13 WKUPN NRST WKUPF SLEEPING FWDGT Cortex-M3 SLEEPDEEP HXTAL POR/PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain...
Page 66: Backup Domain
GD32F1x0 User Manual Figure 3-2. Power supply overview of GD32F170xx and GD32F190xx devices Backup Domain Power Switch LXTAL BPOR WKUP0 WKUPR BKP PAD WKUP1 PC13 WKUPN NRST WKUPF SLEEPING FWDGT Cortex-M3 SLEEPDEEP HXTAL POR/PDR AHB IPs APB IPs 1.8V Domain 1.8V Domain Domain IRC8M...
Page 67: Dda
GD32F1x0 User Manual the RTC timer wakeup event. After entering the power saving mode for a certain amount of time, the RTC alarm will wake up the device when the time match event occurs. The details Real-time clock(RTC). of the RTC configuration and operation will be described in the When the Backup domain is supplied by V pin is connected to V ), the following...
Page 68: Figure 3-3. Waveform Of The Por/Pdr
GD32F1x0 User Manual Figure 3-3. Waveform of the POR/PDR shows the relationship between the supply voltage and the power reset signal. V indicates the threshold of power on reset, while V means the threshold of power down reset. For GD32F130xx and GD32F150xx devices, V configurable.
Page 69: 1.2V Power Domain For Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual Figure 3-4. Waveform of LVD threshold LVD threshold 100mV hyst LVD output Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply is implemented to achieve better performance of analog circuits.
Page 70: Power Saving Modes
GD32F1x0 User Manual Power saving modes 3.3.6. After a system reset or a power reset, the GD32F1x0 MCU operates at full function and all power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, PCLK2) or gating the clocks of the unused peripherals.
Page 71: Table 3-1. Power Saving Mode Summary
GD32F1x0 User Manual Table 5-4. EXTI EXTI_PD register) and and related peripheral flags must be reset, refer to source of GD32F130xx and GD32F150xx devices Table 5-5. EXTI source of GD32F170xx and GD32F190xx devices If not, the program will skip the entry process of Deep-sleep mode to continue to execute the following procedure.
Page 72: Register Definition
GD32F1x0 User Manual Mode Sleep Deep-sleep Standby Any event (or Any event(or interrupt when FWDGT reset interrupt when SEVONPEND is 1) from EXTI WKUP0 pin SEVONPEND is for WFE. WKUP1 pin 1) for WFE. IRC8M wakeup time Wakeup None LDO wakeup time added if Power on sequence Latency LDO is in low power mode...
Page 73 GD32F1x0 User Manual 011: 2.5V 100: 2.6V 101: 2.7V 110: 2.8V 111: 2.9V LVDEN Low Voltage Detector Enable 0: Disable Low Voltage Detector 1: Enable Low Voltage Detector Note: When LVD_LOCK bit is set to 1 in the SYSCFG_CFG2 register, LVDEN and LVDT[2:0] are read only.
Page 74 GD32F1x0 User Manual 31:9 Reserved Must be kept at reset value. BKPWEN Backup Domain Write Enable Disable write access to the registers in Backup domain 1: Enable write access to the registers in Backup domain After reset, any write access to the registers in Backup domain is ignored. This bit has to be set to enable write access to these registers.
Page 75: Power Control/Status Register (Pmu_Cs)
GD32F1x0 User Manual Power control/status register (PMU_CS) 3.4.2. Address offset: 0x04 Reset value: 0x0000 0000 (not reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved WUPEN1 WUPEN0 Reserved LVDF STBF Bits Fields Descriptions 31:10 Reserved...
Page 76 GD32F1x0 User Manual 1: Wakeup event occurred from the WKUP pin or the RTC wakeup event including RTC Tamper event, RTC alarm event，RTC Time Stamp event This bit is cleared only by a POR/PDR or by setting the WURST bit in the PMU_CTL register.
Page 77: Reset And Clock Unit (Rcu)
GD32F1x0 User Manual Reset and clock unit (RCU) 4.1. Reset control unit (RCTL) Overview 4.1.1. GD32F1x0 reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power on reset, known as a cold reset, resets the full system except the backup domain during a power up.
Page 78: Clock Control Unit (Cctl)
GD32F1x0 User Manual A system reset pulse generator guarantees low level pulse duration of 20 μs for each reset source (external or internal reset). Figure 4-1. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V or V power on, if both supplies have...
Page 79: Figure 4-2. Clock Tree Of Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual Figure 4-2. Clock tree of GD32F130xx and GD32F150xx devices CK_ LXTAL CK_CEC (to CEC) ÷ 244 CECSEL USBD CK_USB Prescaler (to USB) ÷ 1,1.5,2,2.5 CK_I2S (to I2S) CK_FMC SCS[1:0] FMC enable (to FMC) (by hardware) HCLK CK_IRC8M AHB enable (to AHB bus,Cortex-M3,SRAM,DMA) 8 MHz...
Page 80: Figure 4-3. Clock Tree Of Gd32F170Xx And Gd32F190Xx Devices
GD32F1x0 User Manual Figure 4-3. Clock tree of GD32F170xx and GD32F190xx devices CK_LXTAL CK_CEC (to CEC) ÷ 244 CECSEL CK_I2S (to I2S) CK_FMC SCS[1:0] FMC enable (to FMC) (by hardware) HCLK CK_IRC8M AHB enable (to AHB bus,Cortex-M3,SRAM,DMA) 8 MHz CK_CST ×2,3,4 CK_PLL CK_SYS...
Page 81: Characteristics
GD32F1x0 User Manual If the APB prescaler is 1, the timer clock frequencies are set to AHB frequency divide by 1. Otherwise, they are set to the AHB frequency divide by half of APB prescaler. Characteristics 4.2.2.  3 to 25 MHz high speed crystal oscillator (HXTAL) for GD32F130xx and GD32F150xx devices or 4 to 32 MHz high speed crystal oscillator (HXTAL) for GD32F170xx and GD32F190xx devices.
Page 82 GD32F1x0 User Manual Select external clock bypass mode by setting the HXTALBPS and HXTALEN bits in the control register 0, RCU_CTL0. The CK_HXTAL is equal to the external clock which drives the OSCIN pin. Internal 8 MHz RC oscillator (IRC8M) The internal 8 MHz RC oscillator, IRC8M, has a fixed frequency of 8 MHz and is the default clock source selection for the CPU when the device is powered up.
Page 83 GD32F1x0 User Manual be generated if the related interrupt enable bit, IRC28MSTBIE, in the Interrupt register, RCU_INT, is set when the IRC28M becomes stable. Low Speed Crystal Oscillator (LXTAL) The low speed crystal or ceramic resonator oscillator, which has a frequency of 32,768 Hz, produces a low power but highly accurate clock source for the real time clock circuit.
Page 84: Table 4-1. Clock Source Select
GD32F1x0 User Manual For GD32F130xx and GD32F150xx devices The clock output capability of GD32F130xx is ranging from 32 kHz to 48 MHz, and the clock output capability of GD32F150xx is ranging from 32 kHz to 72 MHz. There are several clock signals can be selected via the CK_OUT clock source selection bits, CKOUTSEL, in the configuration register 0 (RCU_CFG0).
Page 85: Table 4-3. Core Domain Voltage Selected In Deep-Sleep Mode
GD32F1x0 User Manual Deep-sleep mode clock control When the MCU is in deep-sleep mode, the HDMI CEC or USART0 can wake up the MCU, when their clock is provided by LXTAL clock and LXTAL clock is enable. If the HDMI CEC or USART0 clock is selected IRC8M clock in deep-sleep mode, they have capable of open IRC8M clock or close IRC8M clock, which used to the HDMI CEC or USART0 to wake up the deep-sleep mode.
Page 86: Register Definition
GD32F1x0 User Manual 4.3. Register definition RCU base address: 0x4002 1000 Control register 0 (RCU_CTL0) 4.3.1. Address offset: 0x00 Reset value: 0x0000 XX83 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALB HXTALST HXTALE Reserved PLLSTB PLLEN...
Page 87: Configuration Register 0 (Rcu_Cfg0)
GD32F1x0 User Manual HXTALBPS External crystal oscillator (HXTAL) clock bypass mode enable The HXTALBPS bit can be written only if the HXTALEN is 0. 0: Disable the HXTAL bypass mode. 1: Enable the HXTAL bypass mode in which the HXTAL output clock is equal to the input clock.
Page 88 GD32F1x0 User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). PLLPRE PLLDV CKOUTDIV[2:0] PLLMF[4] CKOUTSEL[2:0] USBDPSC[1:0] PLLMF[3:0] PLLSEL ADCPSC[1:0] APB2PSC[2:0] APB1PSC[2:0] AHBPSC[3:0] SCSS[1:0] SCS[1:0] Bits Fields Descriptions PLLDV The CK_PLL divide by 1 or 2 for CK_OUT 0: CK_PLL divide by 2 for CK_OUT 1: CK_PLL divide by 1 for CK_OUT 30:28...
Page 89 GD32F1x0 User Manual 11: (CK_PLL / 2) selected 21:18 PLLMF[3:0] PLL multiply factor These bits and bit 27 of RCU_CFG0 are written by software to define the PLL multiplication factor. 00000: (PLL source clock x 2) 00001: (PLL source clock x 3) 00010: (PLL source clock x 4) 00011: (PLL source clock x 5) 00100: (PLL source clock x 6)
Page 90 GD32F1x0 User Manual 1: (CK_HXTAL / 2) clock selected PLLSEL PLL clock source selection Set and reset by software to control the PLL clock source. 0: (CK_IRC8M / 2) selected as PLL source clock 1: HXTAL selected as PLL source clock 15:14 ADCPSC[1:0] ADC clock prescaler selection...
Page 91 GD32F1x0 User Manual 11: reserved SCS[1:0] System clock switch Set by software to select the CK_SYS source. Because the change of CK_SYS has inherent latency, software should read SCSS to confirm whether the switching is complete or not. The switch will be forced to IRC8M when leaving Deep-sleep and Standby mode or by HXTAL clock monitor when the HXTAL failure is detected and the HXTAL is selected as the clock source of CK_SYS or PLL.
Page 92 GD32F1x0 User Manual 26:24 CKOUT0SEL[2:0] CKOUT0 clock source selection Set and reset by software. 000: No clock selected 001: Internal 28MHz RC oscillator clock selected 010: Internal 40K RC oscillator clock selected 011: External Low Speed oscillator clock selected 100: System clock selected 101: Internal 8MHz RC Oscillator clock selected 110: External High Speed oscillator clock selected 111: (CK_PLL / 2) or CK_PLL selected depend on PLLDV...
Page 93 GD32F1x0 User Manual 11101: (PLL source clock x 30) 11110: (PLL source clock x 31) 11111: (PLL source clock x 32) Note: The PLL output frequency must not exceed 72 MHz. PLLPREDV HXTAL divider for PLL source clock selection. This bit is the same bit as bit HXTALPREDV[0] from RCU_CFG1.
Page 94: Interrupt Register (Rcu_Int)
GD32F1x0 User Manual 1100: (CK_SYS / 64) selected 1101: (CK_SYS / 128) selected 1110: (CK_SYS / 256) selected 1111: (CK_SYS / 512) selected SCSS[1:0] System clock switch status Set and reset by hardware to indicate the clock source of system clock. 00: Select CK_IRC8M as the CK_SYS source 01: Select CK_HXTAL as the CK_SYS source 10: Select CK_PLL as the CK_SYS source...
Page 95 GD32F1x0 User Manual 1: Reset CKMIF flag Reserved Must be kept at reset value. IRC14MSTBIC IRC14M stabilization interrupt clear Write 1 by software to reset the IRC14MSTBIF flag. 0: Not reset IRC14MSTBIF flag 1: Reset IRC14MSTBIF flag PLLSTBIC PLL stabilization interrupt clear Write 1 by software to reset the PLLSTBIF flag.
Page 96 GD32F1x0 User Manual 1: Enable the HXTAL stabilization interrupt IRC8MSTBIE IRC8M stabilization interrupt clear Set and reset by software to enable/disable the IRC8M stabilization interrupt 0: Disable the IRC8M stabilization interrupt 1: Enable the IRC8M stabilization interrupt LXTALSTBIE LXTAL stabilization interrupt clear LXTAL stabilization interrupt enable/disable control 0: Disable the LXTAL stabilization interrupt 1: Enable the LXTAL stabilization interrupt...
Page 97 GD32F1x0 User Manual 0: No IRC8M stabilization interrupt generated 1: IRC8M stabilization interrupt generated LXTALSTBIF LXTAL stabilization interrupt flag Set by hardware when the External 32,768 Hz crystal oscillator clock is stable and the LXTALSTBIE bit is set. Reset by software when setting the LXTALSTBIC bit. 0: No LXTAL stabilization interrupt generated 1: LXTAL stabilization interrupt generated IRC40KSTBIF...
Page 98 GD32F1x0 User Manual PLLSTBIC PLL stabilization interrupt clear Write 1 by software to reset the PLLSTBIF flag. 0: Not reset PLLSTBIF flag 1: Reset PLLSTBIF flag HXTALSTBIC HXTAL stabilization interrupt clear Write 1 by software to reset the HXTALSTBIF flag. 0: Not reset HXTALSTBIF flag 1: Reset HXTALSTBIF flag IRC8MSTBIC...
Page 99 GD32F1x0 User Manual 0: Disable the LXTAL stabilization interrupt 1: Enable the LXTAL stabilization interrupt IRC40KSTBIE IRC40K stabilization interrupt enable IRC40K stabilization interrupt enable/disable control 0: Disable the IRC40K stabilization interrupt 1: Enable the IRC40K stabilization interrupt CKMIF HXTAL clock stuck interrupt flag Set by hardware when the HXTAL clock is stuck.
Page 100: Apb2 Reset Register (Rcu_Apb2Rst)
GD32F1x0 User Manual 1: LXTAL stabilization interrupt generated IRC40KSTBIF IRC40K stabilization interrupt flag Set by hardware when the Internal 40kHz RC oscillator clock is stable and the IRC40KSTBIE bit is set. Reset by software when setting the IRC40KSTBIC bit. 0: No IRC40K stabilization clock ready interrupt generated 1: IRC40K stabilization interrupt generated APB2 reset register (RCU_APB2RST) 4.3.4.
Page 101: Apb1 Reset Register (Rcu_Apb1Rst)
GD32F1x0 User Manual Reserved Must be kept at reset value. SPI0RST SPI0 Reset This bit is set and reset by software. 0: No reset 1: Reset the SPI0 TIMER0RST TIMER0 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER0 Reserved Must be kept at reset value.
Page 102 GD32F1x0 User Manual CECRST HDMI CEC reset This bit is set and reset by software. 0: No reset 1: Reset hdmi cec unit DACRST DAC reset This bit is set and reset by software. 0: No reset 1: Reset DAC unit PMURST Power control reset This bit is set and reset by software.
Page 103 GD32F1x0 User Manual 1: Reset SPI1 13:12 Reserved Must be kept at reset value. WWDGTRST Window watchdog timer reset This bit is set and reset by software. 0: No reset 1: Reset window watchdog timer 10:9 Reserved Must be kept at reset value. TIMER13RST TIMER13 timer reset This bit is set and reset by software.
Page 104 GD32F1x0 User Manual Bits Fields Descriptions OPAIVREFRST OPA and IVREF reset This bit is set and reset by software. 0: No reset 1: Reset OPA unit CECRST HDMI CEC reset This bit is set and reset by software. 0: No reset 1: Reset hdmi cec unit DACRST DAC reset...
Page 105 GD32F1x0 User Manual This bit is set and reset by software. 0: No reset 1: Reset USART1 Reserved Must be kept at reset value. SPI2RST SPI2 reset This bit is set and reset by software. 0: No reset 1: Reset SPI2 SPI1RST SPI1 reset This bit is set and reset by software.
Page 106: Ahb Enable Register (Rcu_Ahben)
GD32F1x0 User Manual This bit is set and reset by software. 0: No reset 1: Reset TIMER1 timer AHB enable register (RCU_AHBEN) 4.3.6. Address offset: 0x14 Reset value: 0x0000 0014 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved TSIEN Reserved...
Page 107: Apb2 Enable Register (Rcu_Apb2En)
GD32F1x0 User Manual 0: Disabled GPIO port B clock 1: Enabled GPIO port B clock PAEN GPIO port A clock enable This bit is set and reset by software 0: Disabled GPIO port A clock 1: Enabled GPIO port A clock 16:7 Reserved Must be kept at reset value.
Page 108 GD32F1x0 User Manual USART0 TIMER0E CFGCMP Reserved Reserved SPI0EN Reserved ADCEN Reserved Bits Fields Descriptions 31:19 Reserved Must be kept at reset value. TIMER16EN TIMER16 timer clock enable This bit is set and reset by software 0: Disabled TIMER16 timer clock 1: Enabled TIMER16 timer clock TIMER15EN TIMER15 timer clock enable...
Page 109: Apb1 Enable Register (Rcu_Apb1En)
GD32F1x0 User Manual CFGCMPEN System configuration and comparator clock enable This bit is set and reset by software. 0: Disabled System configuration and comparator clock 1: Enabled System configuration and comparator clock APB1 enable register (RCU_APB1EN) 4.3.8. For GD32F130xx and GD32F150xx devices Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit).
Page 110 GD32F1x0 User Manual I2C1EN I2C1 clock enable This bit is set and reset by software. 0: Disabled I2C1 clock 1: Enabled I2C1 clock I2C0EN I2C0 clock enable This bit is set and reset by software. 0: Disabled I2C0 clock 1: Enabled I2C0 clock 20:18 Reserved Must be kept at reset value.
Page 111 GD32F1x0 User Manual Reserved Must be kept at reset value. TIMER2EN TIMER2 timer clock enable This bit is set and reset by software. 0: Disabled TIMER2 timer clock 1: Enabled TIMER2 timer clock TIMER1EN TIMER1 timer clock enable This bit is set and reset by software. 0: Disabled TIMER1 timer clock 1: Enabled TIMER1 timer clock For GD32F170xx and GD32F190xx devices...
Page 112 GD32F1x0 User Manual 1: Enabled Power interface clock Reserved Must be kept at reset value. CAN1EN CAN1 clock enable This bit is set and reset by software. 0: Disabled CAN1 clock 1: Enabled CAN1 clock CAN0EN CAN0 clock enable This bit is set and reset by software. 0: Disabled CAN0 clock 1: Enabled CAN0 clock 24:23...
Page 113: Backup Domain Control Register (Rcu_Bdctl)
GD32F1x0 User Manual 1: Enabled Window watchdog timer clock Reserved Must be kept at reset value. SLCDEN SLCD clock enable This bit is set and reset by software. 0: Disabled SLCD clock 1: Enabled SLCD clock TIMER13EN TIMER13 timer clock enable This bit is set and reset by software.
Page 114 GD32F1x0 User Manual LXTALBP LXTALST RTCEN Reserved RTCSRC[1:0] Reserved LXTALDRI[1:0] LXTALEN Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. BKPRST Backup domain reset This bit is set and reset by software. 0: No reset 1: Resets Backup domain RTCEN RTC clock enable This bit is set and reset by software.
Page 115 GD32F1x0 User Manual 0: Disable LXTAL 1: Enable LXTAL For GD32F170xx and GD32F190xx devices Address offset: 0x20 Reset value: 0x0000 0018, reset by Backup domain Reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Note: The LXTALEN, LXTALBPS, RTCSRC and RTCEN bits of the backup domain control register (BDCTL) are only reset after a backup domain reset.
Page 116: Reset Source /Clock Register (Rcu_Rstsck)
GD32F1x0 User Manual Set and reset by software. Backup domain reset reset this value. 00: lower driving capability 01: medium low driving capability 10: medium high driving capability 11: higher driving capability (reset value) Note: The LXTALDRI is not in bypass mode. LXTALBPS LXTAL bypass mode enable Set and reset by software.
Page 117 GD32F1x0 User Manual WWDGTRSTF Window watchdog timer reset flag Set by hardware when a window watchdog timer reset generated. Reset by writing 1 to the RSTFC bit. 0: No window watchdog reset generated 1: Window watchdog reset generated FWDGTRSTF Free watchdog timer reset flag Set by hardware when a free watchdog timer generated.
Page 118: Ahb Reset Register (Rcu_Ahbrst)
GD32F1x0 User Manual 22:2 Reserved Must be kept at reset value. IRC40KSTB IRC40K stabilization Set by hardware to indicate if the IRC40K output clock is stable and ready for use. 0: IRC40K is not stable 1: IRC40K is stable IRC40KEN IRC40K enable Set and reset by software.
Page 119: Configuration Register 1 (Rcu_Cfg1)
GD32F1x0 User Manual This bit is set and reset by software. 0: No reset GPIO port C 1: Reset GPIO port C PBRST GPIO port B reset This bit is set and reset by software. 0: No reset GPIO port B 1: Reset GPIO port B PARST GPIO port A reset...
Page 120: Configuration Register 2 (Rcu_Cfg2)
GD32F1x0 User Manual 1001: HXTAL input to PLL divided by 10 1010: HXTAL input to PLL divided by 11 1011: HXTAL input to PLL divided by 12 1100: HXTAL input to PLL divided by 13 1101: HXTAL input to PLL divided by 14 1110: HXTAL input to PLL divided by 15 1111: HXTAL input to PLL divided by 16 Configuration register 2 (RCU_CFG2)
Page 121 GD32F1x0 User Manual For GD32F170xx and GD32F190xx devices Address offset: 0x30 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). IRC28MD Reserved Reserved ADCSEL Reserved CECSEL Reserved USART0SEL[1:0] Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. IRC28MDIV CK_IRC28M divider 2 or not This bit is set and reset by software.
Page 122: Control Register 1 (Rcu_Ctl1)
GD32F1x0 User Manual Control register 1 (RCU_CTL1) 4.3.14. For GD32F130xx and GD32F150xx devices Address offset: 0x34 Reset value: 0x0000 XX80 where X is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved IRC14MS IRC14ME IRC14MCALIB[7:0] IRC14MADJ[4:0] Reserved Bits Fields Descriptions...
Page 123: Configuration Register 3 (Rcu_Cfg3) Of Gd32F170Xx And Gd32F190Xx Devices
GD32F1x0 User Manual IRC28MS IRC28ME IRC28MCALIB[7:0] IRC28MADJ[4:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:8 IRC28MCALIB[7:0] Internal 28MHz RC oscillator calibration value register These bits are load automatically at power on. IRC28MADJ[4:0] Internal 28MHz RC oscillator clock trim adjust value These bits are set by software.
Page 124: Apb1 Additional Enable Register (Rcu_Addapb1En)
GD32F1x0 User Manual see bits 2:0 of RCU_CFG3 for CK_OUT1 0: The CK_OUT1 is divided by 1 1: The CK_OUT1 is divided by 2 2: The CK_OUT1 is divided by 3 … 63: The CK_OUT1 is divided by 64 Reserved Must be kept at reset value.
Page 125: Voltage Key Register (Rcu_Vkey)
GD32F1x0 User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved I2C2RST Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. I2C2RST I2C2 unit reset This bit is set and reset by software 0: Not reset I2C2 unit 1: Reset I2C2 unit Voltage key register (RCU_VKEY) 4.3.18.
Page 126: Power Down Voltage Select Register (Rcu_Pdvsel) Of Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual Reserved DSLPVS[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. DSLPVS[2:0] Deep-sleep mode voltage select These bits is set and reset by software 000 : The core voltage is 1.2V in Deep-sleep mode 001 : The core voltage is 1.1V in Deep-sleep mode 010 : The core voltage is 1.0V in Deep-sleep mode 011 : The core voltage is 0.9V in Deep-sleep mode 100~111 : Reserved...
Page 127 GD32F1x0 User Manual Reset value: 0x0000 0000. Only after write 0x1A2B3C4D to the RCU_VKEY, the RCU_PDVSEL register can be written. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved PDRVS Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. PDRVS Power down voltage select This bit is set and reset by software...
Page 128: Interrupt/Event Controller (Exti)
GD32F1x0 User Manual Interrupt/event controller (EXTI) Overview 5.1. Cortex-M3 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processor core. You can read the Technical Reference Manual of Cortex-M3 for more details about NVIC.
Page 129: Table 5-1. Nvic Exception Types In Cotrex-M3
GD32F1x0 User Manual Table 5-1. NVIC exception types in Cotrex-M3 Exception Vector Priority (a) Vector Address Description Type Number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access Programmable 0x0000_0014 BusFault...
Page 130: Table 5-3. Interrupt Vector Table Of Gd32F170Xx And Gd32F190Xx Devices
GD32F1x0 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number IRQ 15 TIMER1 global interrupt 0x0000_007C IRQ 16 TIMER2 global interrupt 0x0000_0080 IRQ 17 TIMER5 and DAC global interrupt 0x0000_0084 IRQ 18 Reserved 0x0000_0088 TIMER13 global interrupt 0x0000_008C IRQ 19 TIMER14 global interrupt 0x0000_0090...
Page 131 GD32F1x0 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number IRQ 4 RCU global interrupt 0x0000_0050 IRQ 5 EXTI Line0-1 interrupt 0x0000_0054 IRQ 6 EXTI Line2-3 interrupt 0x0000_0058 IRQ 7 EXTI Line4-15 interrupt 0x0000_005C TSI global interrupt 0x0000_0060 IRQ 8 DMA Channel0 global interrupt 0x0000_0064...
Page 132: External Interrupt And Event (Exti) Block Diagram
GD32F1x0 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number IRQ 47 SLCD 0x0000_00FC IRQ 48 DMA Channe5-6 global interrupt 0x0000_0100 0x0000_0104- IRQ 49-50 65-66 Reserved 0x0000_0108 SPI2 global interrupt 0x0000_010C IRQ 51 0x0000_0110- IRQ52-69 68-85 Reserved 0x0000_0154 IRQ70 CAN1_TX 0x0000_0158...
Page 133: External Interrupt And Event Function Overview
GD32F1x0 User Manual External interrupt and Event function overview 5.5. The EXTI contains up to 23 independent edge detectors and generates 28 interrupt requests or events to the processor. The EXTI has three trigger types: rising edge, falling edge and both edges.
Page 134: Table 5-5. Exti Source Of Gd32F170Xx And Gd32F190Xx Devices
GD32F1x0 User Manual Software may also trigger EXTI interrupts or events following these steps: Enable interrupts or events by setting related EXTI_INTEN or EXTI_EVEN bits. Set SWIEVx bits in EXTI_SWIEV register. The related PD bits will be set immediately and thus, trigger interrupts or events. Software should response to these interrupts, and clear related PDx bits.
Page 135 GD32F1x0 User Manual EXTI Line Number Source Attrubute PA4 / PB4 / PC4 / PF4 External PA5 / PB5 / PC5 / PF5 External PA6 / PB6 / PC6 / PF6 External PA7 / PB7 / PC7 / PF7 External PA8 / PB8 / PC8 External PA9 / PB9 / PC9...
Page 136: Register Definition
GD32F1x0 User Manual Register definition 5.6. EXTI base address: 0x4001 0400 Interrupt Enable register (EXTI_INTEN) 5.6.1. Address offset: 0x00 Reset value: 0x0F90 0000 This register has to be accessed by word(32-bit). Reserved INTEN27 INTEN26 INTEN25 INTEN24 INTEN23 INTEN22 INTEN21 INTEN20 INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8...
Page 137: Rising Edge Trigger Enable Register (Exti_Rten)
GD32F1x0 User Manual Rising edge trigger enable register (EXTI_RTEN) 5.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RTEN22 RTEN21 Reserved RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7 RTEN6...
Page 138: Software Interrupt Event Register (Exti_Swiev)
GD32F1x0 User Manual FTEN15 FTEN14 FTEN13 FTEN12 FTEN11 FTEN10 FTEN9 FTEN8 FTEN7 FTEN6 FTEN5 FTEN4 FTEN3 FTEN2 FTEN1 FTEN0 Bits Fields Descriptions 31: 23 Reserved Must be kept at reset value. 22: 21 FTENx Falling edge trigger enable (x=21,22) 0: Falling edge of Linex is invalid 1: Falling edge of Linex is valid as an interrupt/event request Reserved Must be kept at reset value.
Page 139: Pending Register (Exti_Pd)
GD32F1x0 User Manual 19: 0 SWIEVx Interrupt/Event software trigger (x=0,19) 0: Deactivate the EXTIx software interrupt/event request 1: Activate the EXTIx software interrupt/event request Pending register (EXTI_PD) 5.6.6. Address offset: 0x14 Reset value: undefined This register has to be accessed by word(32-bit). Reserved PD22 PD21...
Page 140: General-Purpose I/Os (Gpio)
GD32F1x0 User Manual General-purpose I/Os (GPIO) Overview 6.1. There are up to 55 general purpose I/O pins, (GPIO), named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0, PF1, PF4 ~ PF7 for the device to implement logic input/output functions.
Page 141: Gpio Pin Configuration
GD32F1x0 User Manual Table 6-1. GPIO configuration table PAD TYPE CTLn PUDn Floating GPIO Pull-up INPUT Pull-down Floating Push-pull Pull-up Pull-down GPIO OUTPUT Floating Open-drain Pull-up Pull-down Floating AFIO Pull-up INPUT Pull-down Floating Push-pull Pull-up Pull-down AFIO OUTPUT Floating Open-drain Pull-up Pull-down ANALOG...
Page 142: Alternate Functions (Af)
GD32F1x0 User Manual ports are configured into the input floating mode that input disabled without Pull-Up(PU)/Pull- Down(PD) resistors. But the Serial-Wired Debug pins are in AF PU/PD mode after reset: PA14: SWCLK in AF pull-down mode PA13: SWDIO in AF pull-up mode The GPIO pins can be configured as inputs or outputs.
Page 143: Output Configuration
GD32F1x0 User Manual I/O Port bit. Figure 6-2. Basic structure of Input configuration V dd Alternate Function Input protect I / O pin Input driver Input Read Status Register Output configuration 6.3.5. When GPIO pin is configured as output:  The schmitt trigger input is activated.
Page 144: Analog Configuration
GD32F1x0 User Manual Analog configuration 6.3.6. When GPIO pin is used as analog configuration:  The weak pull-up and pull-down resistors are disabled.  The output buffer is disabled.  The schmitt trigger input is de-activated.  Read access to the port input status register gets the value “0”. Figure 6-4.
Page 145: Gpio Locking Function
GD32F1x0 User Manual Figure 6-5. Basic structure of Alternate function configuration Output driver Alternate Function Output protect I / O pin Alternate Function Input Input driver GPIO locking function 6.3.8. The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL, GPIOx_OMODE, GPIOx_OSPD, GPIOx_PUD, GPIOx_AFSELy(y=0,1).
Page 146: Register Definition
GD32F1x0 User Manual 6.4. Register definition GPIOA base address: 0x4800 0000 GPIOB base address: 0x4800 0400 GPIOC base address: 0x4800 0800 GPIOD base address: 0x4800 0C00 GPIOF base address: 0x4800 1400 Port control register (GPIOx_CTL, x=A..D,F) 6.4.1. Address offset: 0x00 Reset value: 0x2800 0000 for port A;...
Page 147: Port Output Mode Register (Gpiox_Omode, X=A
GD32F1x0 User Manual 19:18 CTL9[1:0] Pin 9 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 17:16 CTL8[1:0] Pin 8 configuration bits These bits are set and cleared by software. Refer to CTL0[1:0] description 15:14 CTL7[1:0] Pin 7 configuration bits These bits are set and cleared by software.
Page 148 GD32F1x0 User Manual Reserved OM15 OM14 OM13 OM12 OM11 OM10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value OM15 Pin 15 output mode bit These bits are set and cleared by software. Refer to OM0 description OM14 Pin 14 output mode bit These bits are set and cleared by software.
Page 149: Port Output Speed Register (Gpiox_Ospd, X=A
GD32F1x0 User Manual Refer to OM0 description Pin 5 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 4 output mode bit These bits are set and cleared by software. Refer to OM0 description Pin 3 output mode bit These bits are set and cleared by software.
Page 150 GD32F1x0 User Manual Refer to OSPD0[1:0] description 27:26 OSPD13[1:0] Pin 13 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0 ] description 25:24 OSPD12[1:0] Pin 12 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 23:22 OSPD11[1:0]...
Page 151: Port Pull-Up/Down Register (Gpiox_Pud, X=A
GD32F1x0 User Manual OSPD1[1:0] Pin 1 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description OSPD0[1:0] Pin 0 output max speed bits These bits are set and cleared by software. x0: Output max speed 2M (reset value) 01: Output max speed 10M 11: Output max speed 50M Port pull-up/down register (GPIOx_PUD, x=A..D,F)
Page 152: Port Input Status Register (Gpiox_Istat, X=A
GD32F1x0 User Manual Refer to PUD0[1:0] description 19:18 PUD9[1:0] Pin 9 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 17:16 PUD8[1:0] Pin 8 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUD0[1:0] description 15:14 PUD7[1:0]...
Page 153: Port Output Control Register (Gpiox_Octl, X=A
GD32F1x0 User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT9 ISTAT8 ISTAT7 ISTAT6 ISTAT5 ISTAT4 ISTAT3 ISTAT2 ISTAT1 ISTAT0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 ISTATy[15:0] Port input status (y=0..15)
Page 154: Port Configuration Lock Register (Gpiox_Lock, X=A, B)
GD32F1x0 User Manual CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7 BOP6 BOP5 BOP4 BOP3 BOP2 BOP1 BOP0 Bits Fields Descriptions 31:16 Port Clear bit y(y=0..15) These bits are set and cleared by software. 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit 15:0...
Page 155: Alternate Function Selected Register0 (Gpiox_Afsel0, X=A, B, C)
GD32F1x0 User Manual 0: Port configuration not locked 1: Port configuration locked Alternate function selected register0 (GPIOx_AFSEL0, x=A, B, C) 6.4.9. Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). SEL7[3:0] SEL6[3:0] SEL5[3:0] SEL4[3:0] SEL3[3:0]...
Page 156: Alternate Function Selected Register1 (Gpiox_Afsel1, X=A,B,C)
GD32F1x0 User Manual 0000: AF0 selected (reset value) 0001: AF1 selected 0010: AF2 selected 0011: AF3 selected 0100: AF4 selected (Port A,B only) 0101: AF5 selected (Port A,B only) 0110: AF6 selected (Port A,B only) 0111: AF7 selected (Port A,B only) 1000: Reserved 1001: AF9 selected (Port A,B only) (For GD32F170xx and GD32F190xx devices) 1010: Reserved...
Page 157: Bit Clear Register (Gpiox_Bc, X=A
GD32F1x0 User Manual These bits are set and cleared by software. Refer to SEL8[3:0] description 11:8 SEL10[3:0] Pin 10 alternate function selected These bits are set and cleared by software. Refer to SEL8[3:0] description SEL9[3:0] Pin 9 alternate function selected These bits are set and cleared by software.
Page 158: Port Bit Toggle Register (Gpiox_Tg, X=A
GD32F1x0 User Manual 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit Port bit toggle register (GPIOx_TG, x=A..D,F) (Only for GD32F170xx and 6.4.12. GD32F190xx devices) Address offset: 0x2C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved TG15 TG14...
Page 159: Cyclic Redundancy Checks Management Unit (Crc)
GD32F1x0 User Manual Cyclic redundancy checks management unit (CRC) 7.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 32/16/8 bit CRC code within fixed polynomial.
Page 160: Function Overview
GD32F1x0 User Manual Figure 7-1. Block Diagram of CRC management unit Data Input Input Data Register (32 bit) CRC Management Unit Fixed polynomial 0x4C11DB7 Interface Data Output Output Data Register (32 bit) Data Access Free Purpose Register (8 bit) 7.3. Function overview ...
Page 161 GD32F1x0 User Manual 1) byte reverse: 32-bit data is divided into 4 groups and reverse implement in group inside. Reversed data: 0x2C6AB3F7 2)half-word reverse: 32-bit data is divided into 2 groups and reverse implement in group inside. Reversed data: 0x6A2CF7B3 3)word reverse: 32-bit data is divided into 1 groups and reverse implement in group inside.
Page 162: Register Definition
GD32F1x0 User Manual 7.4. Register definition CRC base address: 0x4002 3000 Data Register (CRC_DATA) 7.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word(32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] CRC calculation result bits Software write and read.
Page 163: Control Register (Crc_Ctl)
GD32F1x0 User Manual These bits are unrelated with CRC calculation. This byte can be used for any goals by any other peripheral. The CRC_CTL register will generate no effect to the byte. Control Register (CRC_CTL) 7.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 164 GD32F1x0 User Manual IDATA [15:0] Bits Fields Descriptions 31:0 IDATA[31:0] Configurable initial CRC data value When RST bit in CRC_CTL asserted, CRC_DATA will be programmed to this value.
Page 165: Direct Memory Access Controller (Dma)
GD32F1x0 User Manual Direct memory access controller (DMA) 8.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 166: Block Diagram
GD32F1x0 User Manual 8.3. Block diagram Figure 8-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state &...
Page 167: Table 8-1. Dma Transfer Operation
GD32F1x0 User Manual Table 8-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 168: Peripheral Handshake
GD32F1x0 User Manual The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register.  If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –...
Page 169: Address Generation
GD32F1x0 User Manual – Software priority: Four levels, including low, medium, high and ultra-high by configuring the PRIO bits in the DMA_CHxCTL register. – For channels with equal software priority level, priority is given to the channel with lower channel number. Address generation 8.4.4.
Page 170: Interrupt
GD32F1x0 User Manual 4. Confi gure the PRIO bits in the DMA_CHxCTL register to set the channel software priority. 5. Configure the memory and peripheral transfer width, memory and peripheral address generation algorithm in the DMA_CHxCTL register. 6. Configure the enable bit for full transfer finish interrupt, half transfer finish interrupt, transfer error interrupt in the DMA_CHxCTL register.
Page 171: Dma Request Mapping
GD32F1x0 User Manual DMA request mapping 8.4.9. Several requests from peripherals may be mapped to one DMA channel. They are logically ORed before entering the DMA. For details, see the following Figure 8-4. DMA request mapping. The request of each peripheral can be independently enabled or disabled by programming the registers of the corresponding peripheral.
Page 172: Figure 8-4. Dma Request Mapping
GD32F1x0 User Manual Figure 8-4. DMA request mapping ADC(1) Hardware TIMER1_CH2 TIMER16_CH0(1) priority Channel 0 TIMER16_UP(1) ADC(2) SPI0_RX USART0_TX(1) I2C0_TX TIMER0_CH0 Channel 1 TIMER1_UP high TIMER2_CH2 TIMER16_CH0(2) TIMER16_UP(2) SPI0_TX USART0_RX(1) I2C0_RX TIMER0_CH1 TIMER1_CH1 TIMER2_CH3 Channel 2 TIMER2_UP TIMER5_UP DAC0 TIMER15_CH0(1) TIMER15_UP(1) SPI1_RX USART0_TX(2)
Page 173 GD32F1x0 User Manual Table 8-3. DMA requests for each channel Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 ● ● ● ● ● ADC(1) ADC(2) ● SPI/I2S SPI/I2S0_RX SPI/I2S0_TX SPI1_RX SPI1_TX SPI2_RX SPI2_TX USART0_TX(2) USART0_RX(2) ●...
Page 174: Register Definition
GD32F1x0 User Manual 8.5. Register definition DMA base address: 0x4002 0000 Interrupt flag register (DMA_INTF) 8.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved ERRIF6 HTFIF6 FTFIF6 GIF6 ERRIF5 HTFIF5 FTFIF5 GIF5 ERRIF4 HTFIF4 FTFIF4...
Page 175: Channel X Control Register (Dma_Chxctl)
GD32F1x0 User Manual This register has to be accessed by word(32-bit). Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0 GIFC0 Bits Fields Descriptions...
Page 176 GD32F1x0 User Manual Software set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level Software set and cleared 00: Low 01: Medium 10: High 11: Ultra high These bits can not be written when CHEN is ‘1’.
Page 177: Channel X Counter Register (Dma_Chxcnt)
GD32F1x0 User Manual Transfer direction Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’. ERRIE Enable bit for channel error interrupt Software set and cleared 0: Disable the channel error interrupt 1: Enable the channel error interrupt...
Page 178: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32F1x0 User Manual is read-only, and decreases after each DMA transfer. If the register is zero, no transaction can be issued whether the channel is enabled or not. Once the transmission of the channel is complete, the register can be reloaded automatically by the previously programmed value if the channel is configured in circular mode.
Page 179 GD32F1x0 User Manual 31:0 MADDR[31:0] Memory base address These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored. Access is automatically aligned to a half word address. When MWIDTH in the DMA_CHxCTL register is 10 (32-bit), the two LSBs of these bits are ignored.
Page 180: Debug (Dbg)
GD32F1x0 User Manual Debug (DBG) 9.1. Overview The GD32F1x0 series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the ARM CoreSight module together with a daisy chained standard TAP controller. Debug and trace functions are integrated into the ARM Cortex-M3.
Page 181: Debug Hold Function Overview
GD32F1x0 User Manual 9.3. Debug hold function overview Debug support for power saving mode 9.3.1. When STB_HOLD bit in DBG control register 0 (DBG_CTL0) is set and entering the standby mode, the clock of AHB bus and system clock are provided by CK_IRC8M, and the debugger can debug in standby mode.
Page 182: Dbg Registers
GD32F1x0 User Manual 9.4. DBG registers DBG base address: 0xE004 2000 ID code register (DBG_ID) 9.4.1. Address: 0xE004 2000 This register has to be accessed by word(32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits can only be read by software, These bits are unchanged constant. Control register 0(DBG_CTL0) 9.4.2.
Page 183 GD32F1x0 User Manual 26:20 Reserved Must be kept at reset value TIMER5_HOLD TIMER5 hold bit This bit is set and reset by software. 0: no effect 1: hold the TIMER5 counter for debug when core is halted Reserved Must be kept at reset value I2C2_HOLD I2C2 hold bit This bit is set and reset by software.
Page 184 GD32F1x0 User Manual 1: hold the FWDGT counter clock for debug when core is halted STB_HOLD Standby mode hold bit This bit is set and reset by software. 0: no effect 1: in the standby mode, the clock of AHB bus and system clock are provided by CK_IRC8M, a system reset generated when exiting standby mode.
Page 185 GD32F1x0 User Manual Reserved Must be kept at reset value TIMER5_HOLD TIMER5 hold bit This bit is set and reset by software. 0: no effect 1: hold the TIMER5 counter for debug when core is halted Reserved Must be kept at reset value I2C2_HOLD I2C2 hold bit This bit is set and reset by software.
Page 186: Control Register 1 (Dbg_Ctl1)
GD32F1x0 User Manual 1: hold the WWDGT counter clock for debug when core is halted FWDGT_HOLD FWDGT hold bit This bit is set and reset by software. 0: no effect 1: hold the FWDGT counter clock for debug when core is halted STB_HOLD Standby mode hold bit This bit is set and reset by software.
Page 187 GD32F1x0 User Manual This bit is set and reset by software. 0: no effect 1: hold the TIMER15 counter for debug when core is halted TIMER14_HOLD TIMER14 hold bit This bit is set and reset by software. 0: no effect 1: hold the TIMER14 counter for debug when core is halted 15:11 Reserved...
Page 188: Analog To Digital Converter (Adc)
GD32F1x0 User Manual Analog to digital converter (ADC) 10.1. Overview A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels, 2 internal channels and the battery voltage (V ) channel.
Page 189: Pins And Internal Signals
GD32F1x0 User Manual  ≤V ≤V Channel input range: V For GD32F170xx and GD32F190xx devices:  High performance. ADC sampling rsolution: 12-bit, 10-bit, 8-bit, or 6-bit. Foreground calibration function. Programmable sampling time. Data storage mode: the most significant bit and the least significant bit. DMA support.
Page 190: Table 10-1. Adc Internal Input Signals
GD32F1x0 User Manual Table 10-1. ADC internal input signals Internal signal name Description Internal temperature sensor output voltage SENSE Internal voltage reference output voltage REFINT pin input voltage divided by 2 Table 10-2. ADC input pins definition of GD32F130xx and GD32F150xx devices Name Description Analog power supply equal to V...
Page 191: Function Overview
GD32F1x0 User Manual 10.4. Function overview Figure 10-1. ADC module block diagram of GD32F130xx and GD32F150xx devices Trig select DMA request Routine channels Interrupt Interrupt Channel Mangement generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Routine data registers ADC_IN15 SAR ADC 12-bit （16 bits）...
Page 192: Foreground Calibration Function
GD32F1x0 User Manual Figure 10-2. ADC module block diagram of GD32F170xx and GD32F190xx devices Trig select DMA request Routine channels Interrupt Interrupt Channel Mangement generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Routine data registers ADC_IN15 Over SAR ADC 6~12-bit （16 bits）...
Page 193: Dual Clock Domain Architecture
GD32F1x0 User Manual Dual clock domain architecture 10.4.2. The ADC sub-module, with exception of the APB interface block, is feed by an ADC clock, which can be asynchronous and independent from the APB clock. Application can reduce PLCK frequency for low power operation while still keeping optimum ADC performance.
Page 194: Figure 10-4. Continuous Operation Mode
GD32F1x0 User Manual register are reset. Configure RSQ0 with the analog channel number. Configure ADC_SAMPTx register. Configure ETERC and ETSRC bits in the ADC_CTL1 register if it is needed. Set the SWRCST bit, or generate an external trigger for the routine sequence. Wait the EOC flag to be set.
Page 195: Figure 10-5. Scan Operation Mode, Continuous Disable
GD32F1x0 User Manual Scan operation mode The scan operation mode will be enabled when SM bit in the ADC_CTL0 register is set. In this mode, the ADC performs conversion on all channels with a specific routine sequence specified in the ADC_RSQ0~ADC_RSQ2 registers. When the ADCON has been set high, the ADC samples and converts specified channels one by one in routine sequence till the end of sequence, once the corresponding software trigger or external trigger is active.
Page 196: Conversion Result Threshold Monitor Function
GD32F1x0 User Manual the ADC_CTL0 register. When the corresponding software trigger or external trigger is active, samples converts next channels configured ADC_RSQ0~ADC_RSQ2 registers until all the channels of routine sequence are done. The EOC will be set after every circle of the routine sequence. An interrupt will be generated if the EOCIE bit is set.
Page 197: Sample Time Configuration
GD32F1x0 User Manual resolution. Figure 10-8. Data storage mode of 12-bit resolution Routine channel data D11 D10 DAL=0 D11 D10 DAL=1 Figure 10-9. Data storage mode of 10-bit resolution Figure 10-10. Data storage mode of 8-bit resolution Figure 10-11. Data storage mode of 6-bit resolution Routine channel data DAL=0 DAL=1...
Page 198: External Trigger Configuration
GD32F1x0 User Manual External trigger configuration 10.4.9. The conversion of routine sequence can be triggered by rising edge of external trigger inputs. The external trigger source of routine sequence is controlled by the ETSRC [2:0] bits in the ADC_CTL1 register. Table 10-4.
Page 199: Battery Voltage Monitoring
GD32F1x0 User Manual the channel. Enable the temperature sensor by setting the TSVREN bit in the ADC control register 1 (ADC_CTL1). Start the ADC conversion by setting the ADCON bit or by the triggers. Read the internal temperature sensor output voltage(V ), and get the temperature temperature with the following equation:...
Page 200: On-Chip Hardware Oversampling
GD32F1x0 User Manual 10.5 375ns 429ns 304ns 357ns 232ns 286ns On-chip hardware oversampling 10.4.15. This chacteristic applies to GD32F170xx and GD32F190xx devices. The on-chip hardware oversampling circuit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit.
Page 201: Table 10-6. Maximum Output Results Vs N And M (Grayed Values Indicates Truncation)
GD32F1x0 User Manual example of the processing, from a raw 20-bit accumulated data to the final 16-bit result. Figure 10-13. Numerical example with 5-bits shift and rounding Table 10-6. Maximum output results vs N and M (Grayed values indicates truncation) gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF.
Page 202 GD32F1x0 User Manual  Analog watchdog. The oversampling configuration can only be changed when ADCON is reset. Make sure configuring the oversampling before setting ADCON to 1.
Page 203: Register Definition
GD32F1x0 User Manual 10.5. Register definition ADC base address: 0x4001 2400 Status register (ADC_STAT) 10.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved STRC Reserved rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:5 Reserved...
Page 204 GD32F1x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved RWDEN Reserved DISNUM [2:0] Reserved DISRC Reserved WDSC Reserved WDEIE EOCIE WDCHSEL[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. RWDEN Routine channel analog watchdog enable 0: Analog watchdog routine channel disable...
Page 205 GD32F1x0 User Manual WDCHSEL [4:0] Analog watchdog channel select 00000: ADC channel0 00001: ADC channel1 00010: ADC channel2 …… 01111: ADC channel15 10000: ADC channel16 10001: ADC channel17 10010: ADC channel18 Other values are reserved. Note: ADC analog inputs Channel16, Channel17 and Channel 18 are internally connected to the temperature sensor, to V and to V analog inputs.
Page 206: Control Register 1 (Adc_Ctl1)
GD32F1x0 User Manual Reserved Must be kept at reset value. DISRC Discontinuous mode on routine sequence 0: Discontinuous operation mode disable 1: Discontinuous operation mode enable Reserved Must be kept at reset value. WDSC When in scan mode, analog watchdog is effective on a single channel 0: All channels have analog watchdog function 1: A single channel has analog watchdog function Scan mode...
Page 207 GD32F1x0 User Manual Reserved VBATEN TSVREN SWRCST Reserved ETERC ETSRC[2:0] Reserved Reserved Reserved Reserved RSTCLB ADCON Bits Fields Descriptions 31:25 Reserved Must be kept at reset value VBATEN This bit is set/cleared by software to enable/disable the V channel. 0: V channel disabled 1: V channel enabled...
Page 208: Sampling Time Register 0 (Adc_Sampt0)
GD32F1x0 User Manual 1: DMA request enable Reserved Must be kept at reset value RSTCLB Reset calibration This bit is set by software and cleared by hardware after the calibration registers are initialized. 0: Calibration register initialize done. 1: Initialize calibration register start ADC calibration 0: Calibration done 1: Calibration start...
Page 209 GD32F1x0 User Manual 14:12 SPT14[2:0] Refer to SPT10[2:0] description 11:9 SPT13[2:0] Refer to SPT10[2:0] description SPT12[2:0] Refer to SPT10[2:0] description SPT11[2:0] Refer to SPT10[2:0] description SPT10[2:0] Channel sampling time 000: channel sampling time is 1.5 cycles 001: channel sampling time is 7.5 cycles 010: channel sampling time is 13.5 cycles 011: channel sampling time is 28.5 cycles 100: channel sampling time is 41.5 cycles...
Page 210: Sampling Time Register 1 (Adc_Sampt1)
GD32F1x0 User Manual SPT12[2:0] Refer to SPT10[2:0] description SPT11[2:0] Refer to SPT10[2:0] description SPT10[2:0] Channel sampling time 000: channel sampling time is 1.5 cycles 001: channel sampling time is 7.5 cycles 010: channel sampling time is 13.5 cycles 011: channel sampling time is 28.5 cycles 100: channel sampling time is 41.5 cycles 101: channel sampling time is 55.5 cycles 110: channel sampling time is 71.5 cycles...
Page 211: Watchdog High Threshold Register (Adc_Wdht)
GD32F1x0 User Manual 000: channel sampling time is 1.5 cycles 001: channel sampling time is 7.5 cycles 010: channel sampling time is 13.5 cycles 011: channel sampling time is 28.5 cycles 100: channel sampling time is 41.5 cycles 101: channel sampling time is 55.5 cycles 110: channel sampling time is 71.5 cycles 111: channel sampling time is 239.5 cycles Note: For GD32F130xx and GD32F150xx devices, the channel 0 and channel 18...
Page 212: Routine Sequence Register 0 (Adc_Rsq0)
GD32F1x0 User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 WDLT[11:0] Low threshold for analog watchdog These bits define the low threshold for the analog watchdog. Routine sequence register 0 (ADC_RSQ0) 10.5.8. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 213: Routine Sequence Register 2 (Adc_Rsq2)
GD32F1x0 User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value 29:25 RSQ11[4:0] Refer to RSQ0[4:0] description 24:20 RSQ10[4:0] Refer to RSQ0[4:0] description 19:15 RSQ9[4:0] Refer to RSQ0[4:0] description 14:10 RSQ8[4:0] Refer to RSQ0[4:0] description RSQ7[4:0] Refer to RSQ0[4:0] description RSQ6[4:0] Refer to RSQ0[4:0] description Routine sequence register 2 (ADC_RSQ2)
Page 214: Oversampling Control Register (Adc_Ovsampctl)
GD32F1x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved RDATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 RDATA[15:0] Routine channel data These bits contain the conversion result from routine channel, which is read only. Oversampling control register (ADC_OVSAMPCTL) 10.5.12.
Page 215 GD32F1x0 User Manual 0001: Shift 1-bit 0010: Shift 2-bits 0011: Shift 3-bits 0100: Shift 4-bits 0101: Shift 5-bits 0110: Shift 6-bits 0111: Shift 7-bits 1000: Shift 8-bits Other codes reserved. Note: The software allows this bit to be written only when ADCON = 0 (this ensures that no conversion is in progress).
Page 216: Digital-To-Analog Converter (Dac)
GD32F1x0 User Manual Digital-to-analog converter (DAC) Overview 11.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 217: Function Overview
GD32F1x0 User Manual Figure 11-1. DAC block diagram DAC control register DTSELx[2:0] DDMA ENx DBOFFx DTENx SWT Rx TIMER5_TRGO TIMER2_TRGO TIMER14_TRGO TIMER1_TRGO Buff EXTI_9 DAC_ Control logic 12-bit 12-bit 12-bit VDDA VSSA Table 11-1. DAC I/O description Name Description Signal type Analog power supply Power Ground for analog power supply...
Page 218: Dac Data Configuration
GD32F1x0 User Manual DAC data configuration 11.3.3. Depending on the selected configuration mode, the data has to be written in the specified register as described below:  Single DAC, there are three possibilities right alignment 8-bit: DHx[11:4] bits are stored into DACx_R8DH [7:0] bits right alignment 12-bit: DHx[11:0] bits are stored into DACx_R12DH [11:0] bits left alignment 12-bit: DHx[11:0] bits are stored into DACx_L12DH [15:4] bits The data can be shifted and stored into the DHx(Data Holding Register x, that are internal...
Page 219: Dac Workflow
GD32F1x0 User Manual The TIMERx_TRGO signals are generated from the timers, while the software trigger can be generated by setting the SWTRx bit in the DAC_SWT register. DAC workflow 11.3.5. If the external trigger enabled by setting the DTENx bit in DAC_CTL register, the DAC holding data is transferred to the DAC output data (DACx_DO) register when the selected trigger events.
Page 220 GD32F1x0 User Manual channels at the same time. For the two DACs and these special registers, several possible conversion modes are possible. The conversion mode in the case of only use one DAC channel, still can operate through independent DHx registers. All modes are described in the paragraphs below.
Page 221: Register Definition
GD32F1x0 User Manual Register definition 11.4. DAC base address: 0x4000 7400 Control register (DAC_CTL) 11.4.1. For GD32F150xx devices Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved DDUDRIE DDMAEN Reserved Reserved DTSEL0[2:0] DTEN0 DBOFF0 DEN0...
Page 222 GD32F1x0 User Manual DTEN0 DAC0 trigger enable This bit is set and cleared by software to enable/disable DAC0 trigger. 0: DAC0 trigger disabled 1: DAC0 trigger enabled DBOFF0 DAC0 output buffer turn off This bit is set and cleared by software to enable/disable DAC0 output buffer. 0: DAC0 output buffer turns on to reduce the output impedance and improve the driving capability 1: DAC0 output buffer turn off...
Page 223 GD32F1x0 User Manual trigger DAC1. 000: TIMER5 TRGO event 001: TIMER2 TRGO event 010: Reserved 011: TIMER14 TRGO event 100: TIMER1 TRGO event 101: Reserved 110: External line9 111: Software trigger DTEN1 DAC1 trigger enable This bit is set and cleared by software to enable/disable DAC1 trigger. 0: DAC1 trigger disabled 1: DAC1 trigger enabled DBOFF1...
Page 224: Software Trigger Register (Dac_Swt)
GD32F1x0 User Manual 111: Software trigger DTEN0 DAC0 trigger enable This bit is set and cleared by software to enable/disable DAC0 trigger. 0: DAC0 trigger disabled 1: DAC0 trigger enabled DBOFF0 DAC0 output buffer turn off This bit is set and cleared by software to enable/disable DAC0 output buffer. 0: DAC0 output buffer turns on to reduce the output impedance and improve the driving capability 1: DAC0 output buffer turn off...
Page 225: Dac0 12-Bit Right-Aligned Data Holding Register (Dac0_R12Dh)
GD32F1x0 User Manual This register has to be accessed by word (32-bit). Reserved Reserved SWTR1 SWTR0 Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SWTR1 DAC1 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled SWTR0 DAC0 software trigger, cleared by hardware 0: Software trigger disabled...
Page 226: Dac0 8-Bit Right-Aligned Data Holding Register (Dac0_R8Dh)
GD32F1x0 User Manual This register has to be accessed by word(32-bit). Reserved DAC0_DH[11:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data. These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value.
Page 227: Dac1 12-Bit Left-Aligned Data Holding Register (Dac1_L12Dh) Of Gd32F190Xx Devices
GD32F1x0 User Manual Reserved Reserved DAC1_DH[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DAC1_DH[11:0] DAC1 12-bit right-aligned data. These bits specify the data that is to be converted by DAC1. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) of 11.4.7.
Page 228: Dac Concurrent Mode 12-Bit Right-Aligned Data Holding Register (Dacc_R12Dh) Of
GD32F1x0 User Manual Reserved Reserved DAC1_DH[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. DAC1_DH[7:0] DAC1 8-bit right-aligned data. These bits specify the data that is to be converted by DAC1. DAC concurrent mode 12-bit right-aligned data holding register 11.4.9.
Page 229: Gd32F190Xx Devices
GD32F1x0 User Manual This register has to be accessed by word(32-bit). DAC1_DH[11:0] Reserved DAC0_DH[11:0] Reserved Bits Fields Descriptions 31:20 DAC1_DH[11:0] DAC1 12-bit left-aligned data These bits specify the data that is to be converted by DAC1. 19:16 Reserved Must be kept at reset value. 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data...
Page 230: Dac0 Data Output Register (Dac0_Do)
GD32F1x0 User Manual DAC0 data output register (DAC0_DO) 11.4.12. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved DAC0_DO [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DAC0_DO [11:0] DAC0 output data These bits, which are read-only, reflect the data that is being converted by DAC0.
Page 231 GD32F1x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved DDUDR0 Reserved rc_w1 Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. DDUDR0 DAC0 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred 1: DMA underrun error condition occurred (the frequency of the current selected trigger that is driving DAC conversion is higher than the DMA service capability rate)
Page 232 GD32F1x0 User Manual This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred 1: DMA underrun error condition occurred (the frequency of the current selected trigger that is driving DAC conversion is higher than the DMA service capability rate) 12:0 Reserved Must be kept at reset value...
Page 233: Comparator (Cmp)
GD32F1x0 User Manual Comparator (CMP) Overview 12.1. The general purpose comparators, CMP0 and CMP1, can work either standalone (all terminal are available on I/Os) or together with the timers. Characteristics 12.2. Rail-to-rail comparators.  Configurable hysteresis.  Configurable speed and consumption. ...
Page 234: Figure 12-1. Cmp Block Diagram Of Gd32F150Xx Devices
GD32F1x0 User Manual Figure 12-1. CMP block diagram of GD32F150xx devices Note: V is 1.2V. REFINT Figure 12-2. CMP block diagram of GD32F190xx devices Note: V is 1.2V. REFINT...
Page 235: Cmp Clock And Reset
GD32F1x0 User Manual CMP clock and reset 12.3.1. The CMP clock is synchronous with the PCLK. The CMP share common reset and clock enable bits with SYSCFG. CMP I/O configure 12.3.2. These pins must be configured in analog mode before they are selected as CMPs inputs. Considering pin definitions in Datasheet, the CMP output must be connected to corresponding alternate I/Os.
Page 236: Cmp Register Write Protection
GD32F1x0 User Manual Figure 12-3. CMP hysteresis CMP_IP CMP_IM+V hyst CMP_IM CMP_IM-V hyst CMP_OUT CMP register write protection 12.3.5. The CMP control and status register (CMP_CS) can be protected from writing by setting CMPxLK bit to 1. The CMP_CS register, including the CMPxLK bit will be read-only, and can only be reset by the MCU reset.
Page 237: Register Definition
GD32F1x0 User Manual 12.4. Register definition CMP base address: 0x4001 001C Control/status register (CMP_CS) 12.4.1. For GD32F150xx devices Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). CMP1LK CMP1O CMP1HST[1:0] CMP1PL CMP1OSEL[2:0] WNDEN CMP1MSEL[2:0] CMP1M Reserved CMP1EN...
Page 238 GD32F1x0 User Manual 000: No selection 001: TIMER 0 break input 010: TIMER 0 channel0 Input capture 011: TIMER 0 OCPRE_CLR input 100: TIMER1 channel3 input capture 101: TIMER1 OCPRE_CLR input 110: TIMER2 channel0 input capture 111: TIMER2 OCPRE_CLR input WNDEN Window mode enable This bit is used to disconnect the CMP1_IP input of CMP1 from PA3 and connect it...
Page 239 GD32F1x0 User Manual This bit is a copy of CMP0 output state, which is read only. 0: Non-inverting input below inverting input and the output is low 1: Non-inverting input above inverting input and the output is high 13:12 CMP0HST[1:0] CMP0 hysteresis These bits are used to control the hysteresis level.
Page 240 GD32F1x0 User Manual 11: Very-low speed/ ultra-low power CMP0SW CMP0 switch This bit is used to closes a switch between CMP0 non-inverting input on PA0 and PA4 (DAC0) I/O. 0: Switch open 1: Switch closed CMP0EN CMP0 enable 0: CMP0 disabled 1: CMP0 enabled For GD32F190xx devices Address offset: 0x00...
Page 241 GD32F1x0 User Manual This bit is used to select the polarity of CMP1 output. 0: Output is not inverted 1: Output is inverted 26:24 CMP1OSEL[2:0] CMP1 output selection These bits are used to select the destination of the CMP1 output. 000: No selection 001: TIMER0 break input 010: TIMER0 channel0 Input capture...
Page 242 GD32F1x0 User Manual This bit allows to have all control bits of CMP0 as read-only. It can only be set once by software cleared by a system reset. 0: CMP_CS[15:0] bits are read-write 1: CMP_CS[15:0] bits are read-only CMP0O CMP0 output This bit is a copy of CMP0 output state, which is read only.
Page 243 GD32F1x0 User Manual CMP0M[1:0] CMP0 mode These bits are used to control the operating mode. 00: High speed / full power 01: Medium speed / medium power 10: Low speed / low power 11: Very-low speed / ultra-low power CMP0SW CMP0 switch This bit is used to closes a switch between CMP0 non-inverting input on PA0 and PA4 (DAC0) I/O.
Page 244: Watchdog Timer (Wdgt)
GD32F1x0 User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 245: Figure 13-1. Free Watchdog Timer Block Diagram
GD32F1x0 User Manual Figure 13-1. Free watchdog timer block diagram The free watchdog timer is enabled by writing the value 0xCCCC in the control register (FWDGT_CTL), and the counter starts counting down. When the counter reaches the value 0x000, a reset is generated. The counter can be reloaded by writing the value 0xAAAA to the FWDGT_CTL register at any time.
Page 246: Table 13-1. Min / Max Fwdgt Timeout Period At 40 Khz (Irc40K)
GD32F1x0 User Manual Table 13-1. Min / max FWDGT timeout period at 40 kHz (IRC40K) Min timeout (ms) Max timeout (ms) PSC[2:0] Prescaler divider RL[11:0]= RL[11:0]= bits 0x000 0xFFF 1 / 4 0.025 409.525 1 / 8 0.025 819.025 1 / 16 0.025 1638.025 1 / 32...
Page 247: Register Definition
GD32F1x0 User Manual Register definition 13.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CMD[15:0] Write only.
Page 248 GD32F1x0 User Manual bit in the FWDGT_STAT register is set and the value read from this register is invalid. 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until...
Page 249 GD32F1x0 User Manual Status register (FWDGT_STAT) Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Watchdog counter window value update When a write operation to FWDGT_WND register ongoing, this bit is set and the value read from FWDGT_WND register is invalid.
Page 250 GD32F1x0 User Manual operation is performed while the counter is greater than the value stored in this register. The WUD bit in the FWDGT_STAT register must be reset in order to be able to change the reload value. These bits are write protected. Write 0x5555 in the FWDGT_CTL register before writing these bits.
Page 251: Window Watchdog Timer (Wwdgt)
GD32F1x0 User Manual Window watchdog timer (WWDGT) 13.2. Overview 13.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions.After the window watchdog timer starts, the value of downcounter reduce progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit becomes cleared).
Page 252: Figure 13-2. Window Watchdog Timer Block Diagram
GD32F1x0 User Manual Figure 13-2. Window watchdog timer block diagram The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. Whenever window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F, it implies that the CNT[6] bit should be set.
Page 253: Figure 13-3. Window Watchdog Timer Timing Diagram
GD32F1x0 User Manual Figure 13-3. Window watchdog timer timing diagram CNT[6:0] Start Start 0x7F Write CNT 0x3F CNT[6]=0 cause a reset Write WWDGT_CTL when CNT>WIN cause a reset Calculate the WWDGT timeout by using the formula below. ×4096 ×2 × ( CNT [ 5:0 ] +1 ) (ms) (13-1) WWDGT PCLK1...
Page 254: Register Definition
GD32F1x0 User Manual Register definition 13.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 255 GD32F1x0 User Manual EWIE Early wakeup interrupt enable. If the bit is set, an interrupt occurs when the counter reaches 0x40. It can be cleared by a hardware reset or software reset by setting the WWDGTRST bit of the RCU module. A write operation of 0 has no effect. PSC[1:0] Prescaler.
Page 256: Real-Time Clock(Rtc)
GD32F1x0 User Manual Real-time clock(RTC) Overview 14.1. The RTC provides a time which includes hour/minute/second/sub-second and a calendar including year/month/day/week day. The time and calendar are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjustment for daylight saving time.
Page 257: Function Overview
GD32F1x0 User Manual Function overview 14.3. Block diagram 14.3.1. Figure 14-1. Block diagram of RTC ALARM 0 Alarm-0 Flag Output Block Diagram Selection Logic 512Hz RTC_CALIB RTC_OUT RTC_REFIN RTC_ALARM ck_spre (Default 1 Hz) IRC40K 15-bit 7-bit ck_apre Digital (Default 256 Hz) Asynchronous Synchronous HXTAL/2~31...
Page 258: Shadow Registers Introduction
GD32F1x0 User Manual In the RTC unit, there are two prescalers used for implementing the calendar and other functions. One prescaler is a 7-bit asynchronous prescaler and the other is a 15-bit synchronous prescaler. Asynchronous prescaler is mainly used for reducing power consumption.
Page 259: Rtc Initialization And Configuration
GD32F1x0 User Manual RTC initialization and configuration 14.3.5. RTC register write protection BKPWEN bit in the PMU_CTL register is cleared in default, so writing to RTC registers needs setting BKPWEN bit ahead of time. After power-on reset, most of RTC registers are write protected. Unlocking this protection is the first step before writing to them.
Page 260: Calendar Reading
GD32F1x0 User Manual next second comes. Alarm function operation process To avoid unexpected alarm assertion and metastable state, alarm function has an operation flow: Disable Alarm (by resetting ALRM0EN in RTC_CTL) Set the Alarm registers needed(RTC_ALRM0TD/RTC_ALRM0SS) Enable Alarm function (by setting ALRM0EN in the RTC_CTL) Calendar reading 14.3.6.
Page 261: Resetting The Rtc
GD32F1x0 User Manual Especially that software must clear RSYNF bit and wait it asserted before reading calendar register after wakeup from power saving mode. Reading calendar registers under BPSHAD=1 When BPSHAD=1, RSYNF is cleared and maintains as 0 by hardware so reading calendar registers does not care about RSYNF bit.
Page 262: Rtc Reference Clock Detection
GD32F1x0 User Manual an offset (in a fraction of a second) with the remote clock, RTC unit provides a function named shift function to remove this offset and thus make second precision higher. RTC_SS register indicates the fraction of a second in binary format and is down counting when RTC is running.
Page 263: Rtc Smooth Digital Calibration
GD32F1x0 User Manual When reference detection function is running while the external reference clock is removed (no reference clock edge found in 3 ck_apre window), the calendar updating still can be performed by LXTAL clock only. If the reference clock is recovered later, detection function will use 7 ck_apre window to identify the reference clock and use 3 ck_apre window to adjust the 1Hz clock (ck_spre) edge.
Page 264 GD32F1x0 User Manual FACTOR_A<3. When the FACTOR_A is less than 3, the FACTOR_S value should be set to a value less than the nominal value. Assuming that RTC clock frequency is nominal 32.768 KHz, the corresponding FACTOR_S should be set as following rule: FACTOR_A = 2: 2 less than nominal FACTOR_S (8189 with 32.768 KHz) FACTOR_A = 1: 4 less than nominal FACTOR_S (16379 with 32.768 KHz) FACTOR_A = 0: 8 less than nominal FACTOR_S (32759 with 32.768 KHz)
Page 265: Time-Stamp Function
GD32F1x0 User Manual Time-stamp function 14.3.11. Time-stamp function is performed on RTC_TS pin and is enabled by control bit TSEN. When a time-stamp event occurs on RTC_TS pin, the calendar value will be saved in time- stamp registers (RTC_DTS/RTC_TTS/RTC_SSTS) and the time-stamp flag (TSF) is set to 1 by hardware.
Page 266: Calibration Clock Output
GD32F1x0 User Manual Edge detection mode on tamper input detection When FLT bit is set to 0x0, the tamper detection is set to edge detection mode and TPxEG bit determines the rising edge or falling edge is the detecting edge. When tamper detection is under edge detection mode, the internal pull-up resistors on the tamper detection input pin are deactivated.
Page 267: Rtc Power Saving Mode Management
GD32F1x0 User Manual function will directly output the content of alarm flag in RTC_STAT. The OPOL bit in RTC_CTL can configure the polarity of the alarm output which means that the RTC_ALARM output is the opposite of the corresponding flag bit or not. RTC power saving mode management 14.3.15.
Page 268: Register Definition
GD32F1x0 User Manual Register definition 14.4. RTC base address: 0x4000 2800 Time register (RTC_TIME) 14.4.1. Address offset: 0x00 System reset: 0x0000 0000 when BPSHAD = 0. Not affected when BPSHAD = 1. This register is write protected and can only be written in initialization state. This register has to be accessed by word(32-bit).
Page 269: Control Register (Rtc_Ctl)
GD32F1x0 User Manual This register is write protected and can only be written in initialization state. This register has to be accessed by word(32-bit). Reserved YRT[3:0] YRU[3:0] DOW[2:0] MONT MONU[2:0] Reserved DAYT[1:0] DAYU[3:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:20 YRT[3:0] Year tens in BCD code...
Page 270 GD32F1x0 User Manual 31:24 Reserved Must be kept at reset value COEN Calibration output enable 0: Disable calibration output 1: Enable calibration output 22:21 OS[1:0] Output selection This bit is used for selecting flag source to output 0x0: Disable output RTC_ALARM 0x1: Enable alarm0 flag output 0x2: Reserved 0x3: Reserved...
Page 271: Status Register (Rtc_Stat)
GD32F1x0 User Manual 1: Enable time-stamp function 10:9 Reserved Must be kept at reset value ALRM0EN Alarm-0 function enable 0: Disable alarm function 1: Enable alarm function Reserved Must be kept at reset value Clock System 0: 24-hour format 1: 12-hour format Note: Can only be written in initialization state BPSHAD Shadow registers bypass control...
Page 272 GD32F1x0 User Manual 31:17 Reserved Must be kept at reset value SCPF Smooth calibration pending flag Set to 1 by hardware when software writes to RTC_HRFC without entering initialization mode and set to 0 by hardware when smooth calibration configuration is taken into account.
Page 273: Prescaler Register (Rtc_Psc)
GD32F1x0 User Manual 0:Shadow register are not yet synchronized 1:Shadow register are synchronized Year configuration mark Set by hardware if the year field of calendar date register is not the default value 0. 0:Calendar has not been initialized 1:Calendar has been initialized SOPF Shift function operation pending flag 0:No shift operation is pending...
Page 274: Alarm 0 Time And Date Register (Rtc_Alrm0Td)
GD32F1x0 User Manual Alarm 0 time and date register (RTC_ALRM0TD) 14.4.6. Address offset: 0x1C System reset: not effect Backup domain reset: 0x0000 0000 This register is write protected and can only be written in initialization state. This register has to be accessed by word(32-bit). MSKD DOWS DAYT[1:0]...
Page 275: Write Protection Key Register (Rtc_Wpk)
GD32F1x0 User Manual 1:Mask second field SCT[2:0] Second tens in BCD code SCU[3:0] Second units in BCD code Write protection key register (RTC_WPK) 14.4.7. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved WPK[7:0] Bits...
Page 276: Shift Function Control Register (Rtc_Shiftctl)
GD32F1x0 User Manual Shift function control register (RTC_SHIFTCTL) 14.4.9. Address offset: 0x2C System reset: not effect Backup domain reset: 0x0000 0000 This register is writing protected and can only be wrote when SOPF=0. This register has to be accessed by word(32-bit). Reserved Reserved SFS[14:0]...
Page 277: Date Of Time Stamp Register (Rtc_Dts)
GD32F1x0 User Manual Reserved MNT[2:0] MNU[3:0] Reserved SCT[2:0] SCU[3:0] Bits Fields Descriptions 31:23 Reserved Must be kept at reset value AM/PM mark 0:AM or 24-hour format 1:PM 21:20 HRT[1:0] Hour tens in BCD code 19:16 HRU[3:0] Hour units in BCD code Reserved Must be kept at reset value 14:12...
Page 278: Sub Second Of Time Stamp Register (Rtc_Ssts)
GD32F1x0 User Manual Reserved Must be kept at reset value DAYT[1:0] Day tens in BCD code DAYU[3:0] Day units in BCD code Sub second of time stamp register (RTC_SSTS) 14.4.12. Address offset: 0x38 Backup domain reset: 0x0000 0000 System reset: no effect This register will record the calendar date when TSF is set to 1.
Page 279: Tamper Register (Rtc_Tamp)
GD32F1x0 User Manual FREQI Increase RTC frequency by 488.5PPM 0: No effect 1: One RTCCLK pulse is inserted every 2 pulses. This bit should be used in conjunction with CMSK bit. If the input clock frequency is 32.768KHz, the number of RTCCLK pulses added during 32s calibration window is (512 * FREQI) - CMSK CWND8 Frequency compensation window 8 second selected...
Page 280 GD32F1x0 User Manual Only valid when LXTAL is disabled and PC15MDE=1,PC15 output this bit data. PC14MDE PC14 Mode 0:No effect 1:Force PC14 to push-pull output if LXTAL is disable PC14VAL PC14 Value Only valid when LXTAL is disabled and PC14MDE=1,PC14 output this bit data. PC13MDE PC13 Mode 0:No effect...
Page 281: Alarm 0 Sub Second Register (Rtc_Alrm0Ss)
GD32F1x0 User Manual 0x1: Sample once every 16384 RTCCLK(2Hz if RTCCLK=32.768KHz) 0x2: Sample once every 8192 RTCCLK(4Hz if RTCCLK=32.768KHz) 0x3: Sample once every 4096 RTCCLK(8Hz if RTCCLK=32.768KHz) 0x4: Sample once every 2048 RTCCLK(16Hz if RTCCLK=32.768KHz) 0x5: Sample once every 1024 RTCCLK(32Hz if RTCCLK=32.768KHz) 0x6: Sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) 0x7: Sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) TPTS...
Page 282: Backup Registers (Rtc_Bkpx) (X=0
GD32F1x0 User Manual Backup domain reset: 0x0000 0000 System reset: no effect This register is write protected and can only be wrote when ALRM0EN=0 or INITM=1. This register has to be accessed by word(32-bit). Reserved MSKSSC[3:0] Reserved Reserved SSC[14:0] Bits Fields Descriptions 31:28...
Page 283 GD32F1x0 User Manual This register has to be accessed by word(32-bit). DATA[31:16] DATA[15:0] Bits Fields Descriptions 31:0 DATA[31:0] Data These registers can be wrote or read by software. The content remains valid even in power saving mode because they can powered-on by V .
Page 284: Timer (Timerx)
GD32F1x0 User Manual Timer (TIMERx) Table 15-1. Timers (TIMERx) are devided into six sorts TIMER TIMER0 TIMER1/2 TIMER13 TIMER14 TIMER15/16 TIMER5 TYPE Advanced General-L0 General-L2 General-L3 General-L4 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit 32-bit(TIMER1) Counter 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit(TIMER2)
Page 285: Advanced Timer (Timerx,X=0)
GD32F1x0 User Manual 15.1. Advanced timer (TIMERx,x=0) Overview 15.1.1. The advanced timer module (TIMER0) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The advanced timer has a 16-bit counter that can be used as an unsigned counter.
Page 286: Block Diagram
GD32F1x0 User Manual Block diagram 15.1.3. Figure 15-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 15-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN ITI0 ITI1 ITI2...
Page 287: Figure 15-2. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual [2:0] in the TIMERx_SMCFG register, details as follows. When the SMC [2:0] bits are set to 0x4, 0x5 or 0x6, the internal clock CK_TIMER is the counter prescaler driving clock source. Figure 15-2. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse...
Page 288: Figure 15-3. Timing Chart Of Psc Value Change From 0 To 2
GD32F1x0 User Manual event. Figure 15-3. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 289: Figure 15-4. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F1x0 User Manual Timing chart of up counting mode, PSC=0/2 Figure 15-4. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Timing chart of up counting mode Figure 15-5.
Page 290: Figure 15-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32F1x0 User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter the counter will start counting down from the counter-reload value again and an underflow event will be generated.
Page 291: Figure 15-7. Timing Chart Of Down Counting Mode, Change Timerx_Car On The Go
GD32F1x0 User Manual Timing chart of down counting mode Figure 15-7. , change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE)
Page 292 GD32F1x0 User Manual Figure 15-8. Center-aligned counter timechart TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured by the TIMERx_CREP register.
Page 293: Figure 15-9. Repetition Counter Timing Chart Of Center-Aligned Counting Mode
GD32F1x0 User Manual If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow. If the next update event occurs on overflow after writing an odd number to CREP, then the subsequent update events will be generated on the overflow.
Page 294: Figure 15-11. Repetition Counter Timing Chart Of Down Counting Mode
GD32F1x0 User Manual Repetition counter timing chart of down counting mode Figure 15-11. TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 295: Figure 15-12. Channel Input Capture Principle
GD32F1x0 User Manual Channel input capture principle Figure 15-12. Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Counter Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 296: Figure 15-13. Channel Output Compare Principle (With Complementary Output
GD32F1x0 User Manual and DMA request will be asserted or not based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN. Direct generation: A DMA request or interrupt is generated by setting CHxG directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 297: Figure 15-15. Output-Compare Under Three Modes
GD32F1x0 User Manual If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNE=1 (the output of CHx_ON is enabled).
Page 298 GD32F1x0 User Manual Figure 15-15. Output-compare under three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 299: Figure 15-16. Eapwm Timechart
GD32F1x0 User Manual Figure 15-16. EAPWM timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Figure 15-17. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal...
Page 300: Table 15-2. Complementary Outputs Controlled By Parameters
GD32F1x0 User Manual The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07. In these modes, the OxCPRE signal level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content.
Page 301 GD32F1x0 User Manual Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_ON=OxCPRE⊕ CHx_O = LOW CHxNP CHx_O output disable. CHx_ON output enable CHx_O=OxCPRE⊕CHxP CHx_ON = LOW CHx_O output enable CHx_ON output disable. CHx_ON=(!OxCPRE)⊕ CHx_O=OxCPRE⊕CHxP CHxNP CHx_O output enable CHx_ON output enable CHx_O = CHxP CHx_ON = CHxNP CHx_O output disable.
Page 302: Figure 15-18. Channel Output Complementary Pwm With Dead-Time Insertion
GD32F1x0 User Manual CHx_ON signal is always the inactive value. Channel output complementary PWM with dead-time insertion Figure 15-18. CHxVAL CxOPRE CHx_O CHx_ON Deadtime Corner case Deadtime > pulse width Pulse width CHx_O Deadtime CHx_ON Deadtime Break mode In this mode, the output CHx_O and CHx_ON are controlled by the POEN, IOS and ROS bits in the TIMERx_CCHP register, ISOx and ISOxN bits in the TIMERx_CTL1 register and cannot be set both to active level when break occurs.
Page 303: Figure 15-19. Output Behavior In Response To A Break(The Break High Active)
GD32F1x0 User Manual Figure 15-19. Output behavior in response to a break(The break high active) BRKIN OxCPRE = ISOx CHx_O CHxEN: 1 CHxNEN: 1 CHxP : 0 CHxNP : 0 = ISOxN ISOx = ~ISOxN CHx_ON = ISOx CHx_O CHxEN: 1 CHxNEN: 0 CHxP: 0 CHxNP : 0 = ISOxN...
Page 304: Figure 15-20. Example Of Counter Operation In Encoder Interface Mode
GD32F1x0 User Manual "-" means "no counting"; "X" means impossible. Note: Figure 15-20. Example of counter operation in encoder interface mode Figure 15-21. Example of encoder interface mode with CI0FE0 polarity inverted Hall sensor function Hall sensor is generally used to control BLDC Motor; advanced timer can support this function. Figure 15-22.
Page 305 GD32F1x0 User Manual And TIMER_out need have functions of complementary and Dead-time, so only advanced timer can be chosen. Else, based on the timers’ internal connection relationship, pair’s timers can be selected. For example: TIMER_in (TIMER0) -> TIMER_out (TIMER7 ITI0) TIMER_in (TIMER1) ->...
Page 306: Figure 15-23. Hall Sensor Timing Between Two Timers
GD32F1x0 User Manual Figure 15-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_I N CH1_IN CH2_IN CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead -time) CH0_O CH0_O N CH1_O CH1_ON CH2_O CH2_O N Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode,...
Page 307: Figure 15-24. Restart Mode
GD32F1x0 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 110: CI1FE1 the trigger source, be used by configuring 111: ETIFP configure the ETP for ETFC and prescaler can polarity selection and be used by configuring inversion. ETPSC. Restart mode The counter will be TRGS[2:0] =...
Page 308: Figure 15-26. Event Mode
GD32F1x0 User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Event mode ETPSC = 1, ETI is The counter will TRGS[2:0] ETP = 0, the polarity of divided by 2. =3’b111 start to count when ETI does not change. ETFC = 0, ETI does not a rising edge of ETIFP is selected.
Page 309: Figure 15-27. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32F1x0 User Manual Figure 15-27. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 Timers interconnection Timer can be configured as interconnection, that is, one timer which operate in the master mode outputs TRGO signal to control another timer which operate in the slave mode, TRGO include reset evevt, start evevt, update evevt, capture/compare pulse evevt, compare evevt.
Page 310: Table 15-5. Input Trigger Of Timer0
GD32F1x0 User Manual Table 15-5. Input trigger of Timer0 shows the input trigger. Table 15-5. Input trigger of Timer0 Slave ITI0(TRGS = 000) ITI1(TRGS = 001) ITI2(TRGS = 010) ITI3(TRGS = 011) TIMER TIMER14 TIMER1 TIMER2 reserved TIMER0 Note: ‘-’ means no interconnection. Other interconnection examples: TIMER2 as prescaler for TIMER0 We configure TIMER2 as a prescaler for TIMER0.
Page 311: Figure 15-29. Triggering Timer0 With Enable Of Timer2
GD32F1x0 User Manual Figure 15-29. Triggering TIMER0 with Enable of TIMER2 TIMER2 TIMER_CK CNT_REG TIMER0 TRGIF CNT_REG Using an external trigger to start 2 timers synchronously We configure the start of TIMER0 is triggered by the enable of TIMER2, and TIMER2 is triggered by its CI0 input rises edge.
Page 312: Figure 15-30. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32F1x0 User Manual Figure 15-30. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input TIMER2 TIMER_CK TRGIF CNT_REG TIMER0 TRGIF CNT_CK CNT_REG Timer DMA mode Timer DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Corresponding DMA request bit should be asserted to enable DMA request for internal interrupt event.
Page 313: Timerx Registers(X=0)
GD32F1x0 User Manual TIMERx registers(x=0) 15.1.5. TIMER0 base address: 0x4001 2C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 314 GD32F1x0 User Manual After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode. 0: Single pulse mode disable.
Page 315 GD32F1x0 User Manual Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit ISO2...
Page 316 GD32F1x0 User Manual The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in channel0, a TRGO trigger signal is output.
Page 317 GD32F1x0 User Manual SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] OCRC SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level . 1: ETI is active at falling edge or low level .
Page 318 GD32F1x0 User Manual 4’b0010 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected together.
Page 319 GD32F1x0 User Manual 011: Quadrature decoder mode 2.The counter counts on both CI0FE0 and CI1FE1 edge, while the direction depends on each other. 100: Restart Mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input. 101: Pause Mode.
Page 320 GD32F1x0 User Manual 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable...
Page 321 GD32F1x0 User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description...
Page 322 GD32F1x0 User Manual Refer to CH0IF description Channel 2 ‘s capture/compare interrupt flag CH2IF Refer to CH0IF description Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs.
Page 323 GD32F1x0 User Manual can occur if enabled. 0: No generate a trigger event 1: Generate a trigger event CMTG Channel commutation event generation This bit is set by software and cleared by hardware automatically. When this bit is set, channel’s capture/compare control registers (CHxEN, CHxNEN and CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1).
Page 324 GD32F1x0 User Manual CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control...
Page 325 GD32F1x0 User Manual 010: Clear the channel output. O0CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH0CV. 011: Toggle on match. O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV. 100: Force low.
Page 326 GD32F1x0 User Manual Note: When CH0MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register. Input capture mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0]...
Page 327 GD32F1x0 User Manual 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges CH0MS[1:0] Channel 0 mode selection Same as Output compare mode Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C...
Page 328 GD32F1x0 User Manual is selected through TRGS bits in TIMERx_SMCFG register. CH2COMCEN Channel 2 output compare clear enable. When this bit is set, if the ETIFP signal is detected as high level, the O2CPRE signal will be cleared. 0: Channel 2 output compare clear disable 1: Channel 2 output compare clear enable CH2COMCTL[2:0] Channel 2 compare output control...
Page 329 GD32F1x0 User Manual When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM1 or PWM2 mode. The output channel will treat an active edge on the trigger input as a compare match, and CH2_O is set to the compare level independently from the result of the comparison.
Page 330 GD32F1x0 User Manual 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 331 GD32F1x0 User Manual Refer to CH0NP description CH2NEN Channel 2 complementary output enable Refer to CH0NEN description CH2P Channel 2 capture/compare function polarity Refer to CH0P description CH2EN Channel 2 capture/compare function enable Refer to CH0EN description CH1NP Channel 1 complementary output polarity Refer to CH0NP description CH1NEN Channel 1 complementary output enable...
Page 332 GD32F1x0 User Manual [CH0NP==1, CH0P==0]: Reserved. [CH0NP==1, CH0P==1]: CIxFE0’s falling and rising edge are both the active signal for capture or trigger operation in slave mode. And CIxFE0 will be not inverted. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10.
Page 333 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 334 GD32F1x0 User Manual This bit-filed specifies the update event generation rate. Each time the repetition counter counting down to zero, an update event is generated. The update rate of the shadow registers is also affected by this bit-filed when these shadow registers are enabled.
Page 335 GD32F1x0 User Manual 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 336 GD32F1x0 User Manual 31:16 Reserved Must be kept at reset value 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 337 GD32F1x0 User Manual 0: BRKIN input active low 1; BRKIN input active high BRKEN Break enable This bit can be set to enable the BRKIN and CCS clock failure event inputs. 0: Break inputs disabled 1; Break inputs enabled This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00.
Page 338 GD32F1x0 User Manual DTCFG[7:5] The duration of dead-time 3’b0xx DTCFG[7:0] * t DTS_CK 3’b10x (64+ DTCFG[5:0]) * t DTS_CK 3’b110 (32+ DTCFG[4:0]) * t DTS_CK 3’b111 (32+ DTCFG[4:0]) * t DTS_CK Note: 1. t is the period of DTS_CK which is configured by CKDIV[1:0] in DTS_CK TIMERx_CTL0.
Page 339 GD32F1x0 User Manual Reserved DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Page 340 GD32F1x0 User Manual...
Page 341: General Level0 Timer (Timerx, X=1, 2)
GD32F1x0 User Manual 15.2. General level0 timer (TIMERx, x=1, 2) Overview 15.2.1. The general level0 timer module (TIMER1, 2) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 342: Function Overview
GD32F1x0 User Manual Figure 15-31. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Trigger processor Input logic PSC_CLK Trigger Selector&Counter Polarity selection TIMER_CK Quadrate Decoder DMA REQ/ACK...
Page 343: Figure 15-32. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual Timing chart of internal clock divided by 1 Figure 15-32. CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111(external clock mode 0). External input pin source The TIMER_CK, driven counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CI0/TIMERx_CI1.
Page 344: Figure 15-33. Timing Chart Of Psc Value Change From 0 To 2
GD32F1x0 User Manual Timing chart of PSC value change from 0 to 2 Figure 15-33. TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 345: Figure 15-35. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F1x0 User Manual Timing chart of up counting mode, PSC=0/2 Figure 15-34. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Timing chart of up counting mode Figure 15-35.
Page 346: Figure 15-36. Timing Chart Of Down Counting Mode, Psc=0/2
GD32F1x0 User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter will start counting down from the counter-reload value. The update event is generated at each counter underflow.
Page 347: Figure 15-37. Timing Chart Of Down Counting Mode, Change Timerx_Car On The Go
GD32F1x0 User Manual Timing chart of down counting mode Figure 15-37. , change TIMERx_CAR on the go. TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE)
Page 348 GD32F1x0 User Manual behavior for different clock frequencies when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 15-38. Center-aligned counter timechart TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear...
Page 349: Figure 15-39. Channel Input Capture Principle
GD32F1x0 User Manual principle Figure 15-39. Channel input capture Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 350: Figure 15-40. Channel Output Compare Principle (X=0,1,2,3)
GD32F1x0 User Manual and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins.
Page 351: Figure 15-41. Output-Compare Under Three Modes
GD32F1x0 User Manual  Set the shadow enable mode by CHxCOMSEN.  Set the output mode (set/clear/toggle) by CHxCOMCTL.  Select the active polarity by CHxP.  Enable the output by CHxEN. Step3: Interrupt/DMA-request enables configuration by CHxIE/CxCDE. Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. The TIMERx_CHxCV can be changed onging to meet the expected waveform.
Page 352: Figure 15-43. Timing Chart Of Capwm
GD32F1x0 User Manual The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by 2*TIMERx_CHxCV. Figure 15-43. Timing chart of CAPWM shows the CAPWM output and interrupts waveform. In up counting mode, if the value of TIMERx_CHxCV is greater than the value of TIMERx_CAR, the output will be always inactive in PWM mode 0 (CHxCOMCTL=3’b110).
Page 353: Table 15-6. Timerx(X=1,2) Interconnection
GD32F1x0 User Manual Channel output prepare signal As is shown in Figure 15-40. Channel output compare principle (x=0,1,2,3) when TIMERx is configured in compare match output mode,a middle signal which is OxCPRE signal (Channel x output prepare signal) will be generated before the channel outputs signal. The OxCPRE signal type is defined by configuring the CHxCOMCTL bit.
Page 354 GD32F1x0 User Manual Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB; Of course, you have to enable a DMA request which will be asserted by some internal interrupt event. When the interrupt event was asserted, TIMERx will send a request to DMA, which is configured to M2P mode and PADDR is TIMERx_DMATB, then DMA will access the TIMERx_DMATB.
Page 355: Timerx Registers(X=1, 2)
GD32F1x0 User Manual TIMERx registers(x=1, 2) 15.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS Bits...
Page 356 GD32F1x0 User Manual can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode.
Page 357 GD32F1x0 User Manual Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 358 GD32F1x0 User Manual Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] OCRC SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level .
Page 359 GD32F1x0 User Manual After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level. The filtering capability configuration is as follows: EXTFC[3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111...
Page 360 GD32F1x0 User Manual 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high. 001: Quadrature decoder mode 0. The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level.
Page 361 GD32F1x0 User Manual CH2DEN Channel 2 capture/compare DMA request enable 0: disabled 1: enabled CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved...
Page 362 GD32F1x0 User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH3IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag Refer to CH0OF description CH2OF Channel 2 over capture flag...
Page 363 GD32F1x0 User Manual mode, this flag is set when a compare event occurs. 0: No Channel 1 interrupt occurred 1: Channel 1 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG)
Page 364 GD32F1x0 User Manual 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high. 0: No generate a channel 1 capture or compare event 1: Generate a channel 1 capture or compare event This bit can be set by software, and cleared by hardware automatically.
Page 365 GD32F1x0 User Manual 00: Channel 1 is programmed as output mode 01: Channel 1 is programmed as input mode, IS1 is connected to CI1FE1 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS. Note: When CH1MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 366 GD32F1x0 User Manual pulse mode (when SPM=1) This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 367 GD32F1x0 User Manual CH0CAPFLT [3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear.
Page 368 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH3COMCEN Channel 3 output compare clear enable Refer to CH0COMCEN description 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable...
Page 369 GD32F1x0 User Manual 110: PWM mode 0. When counting up, O2CPRE is high when the counter is smaller than TIMERx_CH2CV, and low otherwise. When counting down, O2CPRE is low when the counter is larger than TIMERx_CH2CV, and high otherwise. 111: PWM mode 1. When counting up, O2CPRE is low when the counter is smaller than TIMERx_CH2CV, and high otherwise.
Page 370 GD32F1x0 User Manual 31:16 Reserved Must be kept at reset value 15:12 CH3CAPFLT[3:0] Channel 3 input capture filter control Refer to CH0CAPFLT description 11:10 CH3CAPPSC[1:0] Channel 3 input capture prescaler Refer to CH0CAPPSC description CH3MS[1:0] Channel 3 mode selection Same as Output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control The CI2 input signal can be filtered by digital filter and this bit-field configure the...
Page 371 GD32F1x0 User Manual Same as output compare mode Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CH3NP Reserved CH3P CH3EN CH2NP Reserved CH2P CH2EN CH1NP Reserved CH1P CH1EN CH0NP Reserved...
Page 372 GD32F1x0 User Manual Refer to CH0EN description CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit should be keep reset value. When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0.
Page 373 GD32F1x0 User Manual CNT[15:0] Bits Fields Descriptions 31:0 CNT[31:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Counter register (TIMERx_CNT) (x=2) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CNT[15:0] Bits...
Page 374 GD32F1x0 User Manual value of this bit-filed will be loaded to the corresponding shadow register at every update event. Counter auto reload register (TIMERx_CAR) (x=1) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). CARL[31:16] CARL[15:0] Bits...
Page 375 GD32F1x0 User Manual This register has to be accessed by word(32-bit). CH0VAL[31:16] CH0VAL[15:0] Bits Fields Descriptions 31:0 CH0VAL[31:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 376 GD32F1x0 User Manual This register has to be accessed by word(32-bit). CH1VAL[31:16] CH1VAL[15:0] Bits Fields Descriptions 31:0 CH1VAL[31:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 377 GD32F1x0 User Manual This register has to be accessed by word(32-bit). CH2VAL[31:16] CH2VAL[15:0] Bits Fields Descriptions 31:0 CH2VAL[31:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 378 GD32F1x0 User Manual This register has to be accessed by word(32-bit). CH3VAL[31:16] CH3VAL[15:0] Bits Fields Descriptions 31:0 CH3VAL[31:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 379 GD32F1x0 User Manual This register has to be accessed by word(32-bit). Reserved Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed is defined the number of DMA will access(R/W) the register of TIMERx_DMATB Reserved Must be kept at reset value.
Page 380 GD32F1x0 User Manual Configuration register (TIMERx_CFG) of GD32F170xx and GD32F190xx devices Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CHVSEL Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CHVSEL Write CHxVAL register selection This bit-field set and reset by software.
Page 381: General Level2 Timer (Timerx, X=13)
GD32F1x0 User Manual 15.3. General level2 timer (TIMERx, x=13) Overview 15.3.1. The general level2 timer module (TIMER 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 382: Function Overview
GD32F1x0 User Manual configuration of the general level2 timer. Figure 15-44. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update compare, PWM,and mixed modes...
Page 383: Figure 15-45. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual Timing chart of internal clock divided by 1 Figure 15-45. CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 384: Figure 15-47. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F1x0 User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow.
Page 385: Figure 15-48. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F1x0 User Manual Timing chart of up counting mode Figure 15-48. , change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE)
Page 386: Figure 15-49. Channel Input Capture Principle
GD32F1x0 User Manual Channel principle Figure 15-49. input capture Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 387 GD32F1x0 User Manual and DMA request will be asserted or not based on the configuration of CHxIE in TIMERx_DMAINTEN. Direct generation: An interrupt is generated by setting CHxG directly. The channel input capture function can be also used for pulse period measurement from signals on the TIMERx_CHx pins.
Page 388: Figure 15-51. Output-Compare Under Three Modes
GD32F1x0 User Manual Step3: Interrupt/DMA-request enables configuration by CHxIE. Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. The TIMERx_CHxCV can be changed onging to meet the expected waveform. Step5: Start the counter by configuring CEN to 1. Figure 15-51. Output-compare under three modes show the three compare modes toggle/set/clear.
Page 389 GD32F1x0 User Manual Figure 15-52. PWM mode timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF Channel output prepare signal As is shown in Figure 15-50. Channel output compare principle when TIMERx is configured in compare match output mode,a middle signal which is OxCPRE signal (Channel x output prepare signal) will be generated before the channel outputs signal.
Page 390: Timerx Registers(X=13)
GD32F1x0 User Manual TIMERx registers(x=13) 15.3.5. TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 391 GD32F1x0 User Manual registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
Page 392 GD32F1x0 User Manual Reserved Reserved CH0OF Reserved. CH0IF UPIF rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
Page 393 GD32F1x0 User Manual 31:2 Reserved Must be kept at reset value. Channel 0’s capture or compare event generation CH0G This bit is set by software in order to generate a capture or compare event in channel 0, it is automatically cleared by hardware. When this bit is set, the CH1IF flag is set, the corresponding interrupt or DMA request is sent if enabled.
Page 394 GD32F1x0 User Manual 011: Toggle on match. O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV. 100: Force low. O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise.
Page 395 GD32F1x0 User Manual Input capture mode: Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CH0CAPFLT[3:0] Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit-field configure the filtering capability. Basic principle of digital filter: continuously sample the CI0 input signal according to and record the number of times of the same level of the signal.
Page 396 GD32F1x0 User Manual This register has to be accessed by word(32-bit). Reserved Reserved.. CH0NP Reserved CH0P CH0EN Bits Fields Descriptions 31:4 Reserved Must be kept at reset value CH0NP Channel 0 complementary output polarity When channel 0 is configured in output mode, this bit specifies the complementary output signal polarity.
Page 397 GD32F1x0 User Manual 0: Channel 0 disabled 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value.
Page 398 GD32F1x0 User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
Page 399 GD32F1x0 User Manual Channel input remap register(TIMERx_IRMP) Address offset: 0x50 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CI0_RMP[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CI0_RMP[1:0] Channel 0 input remap 00: Channel 0 input is connected to GPIO(TIMER13_CH0) 01: Channel 0 input is connected to the RTCCLK 10: Channel 0 input is connected to HXTAL/32 clock...
Page 400 GD32F1x0 User Manual write access ignored 0: No effect Reserved Must be kept at reset value...
Page 401: General Level3 Timer (Timerx, X=14)
GD32F1x0 User Manual 15.4. General level3 timer (TIMERx, x=14) Overview 15.4.1. The general level3 timer module (TIMER14) is a two-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 402 GD32F1x0 User Manual Figure 15-53. General level3 timer block diagram CH0_IN Input Logic Synchronizer&Filter Edge selector Prescaler CH1_IN &Edge Detector ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter Trigger processor TIMERx_TRGO PSC_CLK Trigger Selector&Counter TIMER_CK DMA REQ/ACK DMA controller TIMERx_CH0 TIMERx_CH1 TIMERx_TG TIMERx_UP req en/direct req set...
Page 403: Figure 15-54. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual Timing chart of internal clock divided by 1 Figure 15-54. CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG  SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin TIMERx_CH0/TIMERx_CH1.
Page 404: Figure 15-55. Timing Chart Of Psc Value Change From 0 To 2
GD32F1x0 User Manual Timing chart of PSC value change from 0 to 2 Figure 15-55. TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 405: Figure 15-56. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F1x0 User Manual Timing chart of up counting mode, PSC=0/2 Figure 15-56. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Timing chart of up counting mode Figure 15-57.
Page 406: Figure 15-58. Repetition Counter Timing Chart Of Up Counting Mode
GD32F1x0 User Manual Update event (from overflow/underflow) rate configuration The rate of update events generation (from overflow and underflow events) can be configured by the TIMERx_CREP register. Counter repetition is used to generator update event or updates the timer registers only after a given number (N+1) of cycles of the counter, where N is CREP in TIMERx_CREP register.
Page 407: Figure 15-59. Channel Input Capture Principle
GD32F1x0 User Manual Channel input capture principle Figure 15-59. Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 408: Figure 15-50. Channel Output Compare Principle
GD32F1x0 User Manual Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register (TIMERx_CHCTL0) and set capture on rising edge.
Page 409: Figure 15-62. Output-Compare Under Three Modes
GD32F1x0 User Manual output of CHx_ON is enabled): If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(high) level. When CH0_O and CH0_ON are output at the same time, the specific outputs of CH0_O and CH0_ON are related to the relevant bits (ROS, IOS, POE and DTCFG bits) in the TIMERx_CCHP register.
Page 410: Figure 15-63. Pwm Mode Timechart
GD32F1x0 User Manual Figure 15-62. Output-compare under three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 411 GD32F1x0 User Manual Figure 15-63. PWM mode timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 412: Table 15-7. Complementary Outputs Controlled By Parameters
GD32F1x0 User Manual Table 15-7. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable: CHx_O = ISOx CHx_ON = ISOxN CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable.
Page 413: Figure 15-64. Complementary Output With Dead-Time Insertion
GD32F1x0 User Manual state at the same time. When the channel (x) match (TIMERx counter = CHxVAL) occurs, OxCPRE will be toggled because under PWM0 mode. At point A in the Figure 15-64. Complementary output with dead-time insertion. CHx_O signal remains at the low value until the end of the deadtime delay, while CHx_ON will be cleared at once.
Page 414: Figure 15-65. Output Behavior In Response To A Break(The Break High Active)
GD32F1x0 User Manual state, and then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the ISOx and ISOxN bits after a dead-time. When a break occurs, the BRKIF bit in the TIMERx_INTF register is set. If BRKIE is 1, an interrupt generated.
Page 415: Figure 15-66. Restart Mode
GD32F1x0 User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection 111: Reserved Restart mode TRGS[2:0]=3’b0 The counter can For ITI0, no polarity For the ITI0, no filter and be clear and ITI0 is the selector can be used. prescaler can be used.
Page 416: Figure 15-68. Event Mode
GD32F1x0 User Manual Source Mode Selection Polarity Selection Filter and Prescaler Selection Figure 15-68. Event mode Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event.
Page 417: Table 15-9. Timerx(X=14) Interconnection
GD32F1x0 User Manual Figure 15-69. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 Timers interconnection Refer to Advanced timer (TIMERx, x=0) Table 15-9. TIMERx(x=14) interconnection ITI2(TRGS = ITI3(TRGS = Slave TIMER ITI0(TRGS = 000) ITI1(TRGS = 001) 010) 011) TIMER14 TIMER1 TIMER2 Reserved Reserved...
Page 418 GD32F1x0 User Manual TIMERx registers(x=14) 15.4.5. TIMER14 base address: 0x4001 4000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields Descriptions 31:10 Reserved Must be kept at reset value CKDIV[1:0]...
Page 419 GD32F1x0 User Manual UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 420 GD32F1x0 User Manual The CH0_O output changes after a dead-time if CH0_ON is implemented. This bit can be modified only when PROT [1:0] bits in TIMERx_CCHP register is 00. Reserved Must be kept at reset value MMC[2:0] Master mode control These bits control the selection of TRGO signal, which is sent in master mode to slave timers for synchronization function.
Page 421 GD32F1x0 User Manual After these bits have been written, they are updated based when commutation event coming. When a channel does not have a complementary output, this bit has no effect. Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 422 GD32F1x0 User Manual 010: Reserved 011: Reserved 100: Restart Mode. The counter is reinitialized and an update event is generated on the rising edge of the selected trigger input. 101: Pause Mode. The trigger input enables the counter clock when it is high and disables the counter clock when it is low.
Page 423 GD32F1x0 User Manual 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled CMTIE commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE...
Page 424 GD32F1x0 User Manual When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set. This flag is cleared by software. 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved Must be kept at reset value.
Page 425 GD32F1x0 User Manual This register has to be accessed by word(32-bit). Reserved Reserved BRKG TRGG CMTG Reserved CH1G CH0G Bits Fields Descriptions 31:8 Reserved Must be kept at reset value BRKG Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 426 GD32F1x0 User Manual 1: Generate a channel 1 capture or compare event Update event generation This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, else (down counting) it takes the auto-reload value.
Page 427 GD32F1x0 User Manual through TRGS bits in TIMERx_SMCFG register. Reserved Must be kept at reset value. CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits.
Page 428 GD32F1x0 User Manual 0: Channel 0 output quickly compare disable. 1: Channel 0 output quickly compare enable. CH0MS[1:0] Channel 0 I/O mode selection This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH0EN bit in TIMERx_CHCTL2 register is reset).).
Page 429 GD32F1x0 User Manual 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 430 GD32F1x0 User Manual output signal polarity. 0: Channel 0 complementary output high level is active level 1: Channel 0 complementary output low level is active level When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0.
Page 431 GD32F1x0 User Manual Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 432 GD32F1x0 User Manual CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 433 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 434 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable The bit can be set to 1 by: - Write 1 to this bit - If OAEN is set to 1, this bit is set to 1 at the next update event.. The bit can be cleared to 0 by: - Write 0 to this bit - Valid fault input...
Page 435 GD32F1x0 User Manual Idle mode off-state configure When POEN bit is reset, this bit specifies the output state for the channels which has been configured in output mode. 0: When POEN bit is reset, the channel output signals (CHx_O/CHx_ON) are disabled.
Page 436 GD32F1x0 User Manual Reserved Reserved DMATC[4:0] Reserved DMATA [4:0] Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:8 DMATC [4:0] DMA transfer count This filed is defined the number of DMA will access(R/W) the register of TIMERx_DMATB Reserved Must be kept at reset value.
Page 437 GD32F1x0 User Manual Configuration register (TIMERx_CFG) of GD32F170xx and GD32F190xx devices Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CHVSEL OUTSEL Bits Fields Descriptions 31:2 Reserved Must be kept at reset value CHVSEL Write CHxVAL register selection This bit-field set and reset by software.
Page 438: Figure 15-70. General Level4 Timer Block Diagram
GD32F1x0 User Manual 15.5. General level4 timer (TIMERx, x=15,16) Overview 15.5.1. The general level4 timer module (TIMER15,TIMER16) is a one-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. The general level4 timer has a 16-bit counter that can be used as an unsigned counter.
Page 439 GD32F1x0 User Manual Figure 15-70. General level4 timer block diagram Input Logic Synchronizer&Filter CH0_IN Edge selector Prescaler &Edge Detector CK_TIMER TIMERx_CHxCV Counter PSC_CLK Counter Control TIMER_CK DMA REQ/ACK TIMERx_CH0 TIMERx_UP DMA controller req en/direct req set Register /Interrupt APB BUS Output Logic Interrupt CH0_O...
Page 440: Figure 15-71. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual Timing chart of internal clock divided by 1 Figure 15-71. CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 441: Figure 15-73. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F1x0 User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again and an overflow event will be generated.
Page 442: Figure 15-74. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F1x0 User Manual Timing chart of up counting mode Figure 15-74. , change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE)
Page 443: Figure 15-75. Repetition Counter Timing Chart Of Up Counting Mode
GD32F1x0 User Manual Repetition counter timing chart of up counting mode Figure 15-75. TIMER_CK PSC_CLK 97 98 99 0 98 99 0 98 99 CNT_REG 98 99 0 98 99 0 98 99 0 Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2...
Page 444: Figure 15-76. Channel Input Capture Principle
GD32F1x0 User Manual Channel input capture principle Figure 15-76. Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 445: Figure 15-77. Output-Compare Under Three Modes
GD32F1x0 User Manual Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly.  Channel output compare function The channel input capture function, the TIMERx can generate timed pulses with programmable position, polarity, duration and frequency. When the counter matches the value in the CHxVAL register of an output compare channel, the channel (n) output can be set, cleared, or toggled based on CHxCOMCTL.
Page 446: Figure 15-78. Pwm Mode Timechart
GD32F1x0 User Manual Figure 15-77. Output-compare under three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 447 GD32F1x0 User Manual Figure 15-78. PWM mode timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 448: Table 15-10. Complementary Outputs Controlled By Parameters
GD32F1x0 User Manual Table 15-10. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable: CHx_O = ISOx CHx_ON = ISOxN CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable.
Page 449: Figure 15-79. Channel Output Complementary Pwm With Dead-Time Insertion
GD32F1x0 User Manual state at the same time. When the channel (x) match (TIMERx counter = CHxVAL) occurs, OxCPRE will be toggled because under PWM0 mode. At point A in the Figure 15-79. Channel output complementary PWM with dead-time insertion CHx_O signal remains at the low value until the end of the deadtime delay, while CHx_ON will be cleared at once.
Page 450: Figure 15-80. Output Behavior In Response To A Break(The Break High Active)
GD32F1x0 User Manual output else the enable output remains high. The complementary outputs are first put in reset state, and then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the ISOx and ISOxN bits after a dead-time. When a break occurs, the BRKIF bit in the TIMERx_INTF register is set.
Page 451: Figure 15-81. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32F1x0 User Manual state which the OxCPRE signal will change to, as the compare match event occurs without taking the comparison result into account. The CHxCOMFEN bit is available only when the output channel is configured to operate in the PWM0 or PWM1 output mode and the trigger source is derived from the trigger signal.
Page 452 GD32F1x0 User Manual TIMERx registers(x=15,16) 15.5.5. TIMER15 base address: 0x4001 4400 TIMER16 base address: 0x4001 4800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CKDIV[1:0] ARSE Reserved UPDIS Bits Fields...
Page 453 GD32F1x0 User Manual The counter generates an overflow or underflow event UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values. These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 454 GD32F1x0 User Manual can be modified only when PROT [1:0] bits in TIMERx_CCHP register is 00. Reserved Must be kept at reset value DMAS DMA request source selection 0: DMA request of channel x is sent when capture/compare event occurs. 1: DMA request of channel x is sent when update event occurs.
Page 455 GD32F1x0 User Manual UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CMTIE Commutation interrupt enable 0: disabled 1: enabled Reserved Must be kept at reset value CH0IE Channel 0 capture/compare interrupt enable 0: disabled...
Page 456 GD32F1x0 User Manual 1: Over capture interrupt occurred Reserved Must be kept at reset value. BRKIF Break interrupt flag When the break input is inactive, the bit is set by hardware. When the break input is inactive, the bit can be cleared by software. 0: No active level break has been detected.
Page 457 GD32F1x0 User Manual 31:8 Reserved Must be kept at reset value BRKG Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POEN bit is cleared and BRKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 458 GD32F1x0 User Manual CH0COM CH0COM Reserved CH0COMCTL[2:0] Reserved CH0MS[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:7 Reserved Must be kept at reset value CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE.
Page 459 GD32F1x0 User Manual 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 460 GD32F1x0 User Manual 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 461 GD32F1x0 User Manual complementary output in channel0. 0: Channel 0 complementary output disabled 1: Channel 0 complementary output enabled CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the output signal polarity. 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity.
Page 462 GD32F1x0 User Manual 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved PSC[15:0] Bits...
Page 463 GD32F1x0 User Manual Counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved CREP[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. CREP[7:0] Counter repetition value This bit-filed specifies the update event generation rate.
Page 464 GD32F1x0 User Manual Complementary channel protection register (TIMERx_CCHP) Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved POEN OAEN BRKP BRKEN PROT[1:0] DTCFG[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value POEN Primary output enable The bit can be set to 1 by:...
Page 465 GD32F1x0 User Manual is 00. Run mode off-state configure When POEN bit is set, this bit specifies the output state for the channels which has a complementary output and has been configured in output mode. 0: When POEN bit is set, the channel output signals (CHx_O/CHx_ON) are disabled.
Page 466 GD32F1x0 User Manual TIMERx_CTL0. 2. This bit can be modified only when PROT [1:0] bit-filed in TIMERx_CCHP register is 00. DMA configuration register (TIMERx_DMACFG) Address offset: 0x48 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved DMATC[4:0] Reserved...
Page 467 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC.
Page 468: Figure 15-82. Basic Timer Block Diagram
GD32F1x0 User Manual 15.6. Basic timer (TIMERx, x=5) The basic timer is only available on GD32F150/190 series. Overview 15.6.1. The basic timer module (TIMER5) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 469: Figure 15-83. Timing Chart Of Internal Clock Divided By 1
GD32F1x0 User Manual The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER used to drive the counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. Timing chart of internal clock divided by 1 Figure 15-83.
Page 470: Figure 15-84. Timing Chart Of Psc Value Change From 0 To 2
GD32F1x0 User Manual Timing chart of PSC value change from 0 to 2 Figure 15-84. TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction.
Page 471: Figure 15-85. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F1x0 User Manual Timing chart of up counting mode, PSC=0/2 Figure 15-85. TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Timing chart of up counting mode Figure 15-86.
Page 472 GD32F1x0 User Manual Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event. Once the timer is set to operate in the single pulse mode, it is necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter, then the CEN bit keeps at a high state until the update event occurs or the CEN bit is written to 0 by software.
Page 473 GD32F1x0 User Manual TIMERx registers(x=5) 15.6.5. TIMER5 base address: 0x4000 1000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved ARSE Reserved UPDIS Bits Fields Descriptions 31:8 Reserved Must be kept at reset value ARSE Auto-reload shadow enable...
Page 474 GD32F1x0 User Manual The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized. Counter enable 0: Counter disable 1: Counter enable...
Page 475 GD32F1x0 User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled Reserved...
Page 476 GD32F1x0 User Manual 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically.
Page 477 GD32F1x0 User Manual Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock.
Page 478: Figure 16-1. Ifrp Output Timechart 1
GD32F1x0 User Manual Infrared ray port (IFRP) 16.1. Overview Infrared ray port (IFRP) is used to control infrared light LED, and send out infrared data to implement infrared ray remote control. There is no register in this module, which is controlled by TIMER15 and TIMER16. You can improve the module's output to high current capacity by set the GPIO pin to Fast Mode.
Page 479: Figure 16-2. Ifrp Output Timechart 2
GD32F1x0 User Manual Note: IFRP_OUT has one APB clock delay from TIMER16_CH0. Figure 16-2. IFRP output timechart 2 TIMER16_CH0 TIMER15_CH0 IFRP_OUT Note: Carrier (TIMER15_CH0)’s duty cycle can be changed, and IFRP_OUT has inverted relationship with TIMER16_CH0 when TIMER15_CH0 is high. Figure 16-3.
Page 480 GD32F1x0 User Manual Universal synchronous asynchronous receiver transmitter (USART) Overview 17.1. The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator produces a dedicated wide range baudrate clock for the USART transmitter and receiver.
Page 481 GD32F1x0 User Manual Checks parity of received data byte –  LIN break generation and detection  IrDA support  Synchronous mode and transmitter clock output for synchronous transmission  ISO 7816-3 compliant smartcard interface – Character mode (T=0) – Block mode (T=1) Direct and inverse convention –...
Page 482: Figure 17-1. Usart Module Block Diagram
GD32F1x0 User Manual Table 17-1. USART important pins description Type Description Input Receive Data Output I/O (single- Transmit Data. high level When enabled but wire/smartcard mode) nothing to be transmitted Output Serial clock for synchronous communication nCTS Input Clear to send in Hardware flow control mode nRTS Output Request to send in Hardware flow control mode...
Page 483: Figure 17-2. Usart Character Frame (8 Bits Data And 1 Stop Bit)
GD32F1x0 User Manual Figure 17-2. USART character frame (8 bits data and 1 stop bit) In transmission and reception, the number of stop bits can be configured by the STB[1:0] bits in the USART_CTL1 register. Table 17-2. Stop bits configuration STB[1:0] stop bit length (bit) usage description...
Page 484 GD32F1x0 User Manual For example, when oversampled by 16: Get USARTDIV by caculating the value of USART_BUAD: If USART_BUAD=0x21D, then INTDIV=33 (0x21), FRADIV=13 (0xD). USARTDIV=33+13/16=33.81. Get the value of USART_BUAD by calculating the value of USARTDIV: If USARTDIV=30.37, then INTDIV=30 (0x1E). 16*0.37=5.92, the nearest integer is 6, so FRADIV=6 (0x6).
Page 485: Figure 17-3. Usart Transmit Procedure
GD32F1x0 User Manual Figure 17-3. USART transmit procedure It is necessary to wait for the TC bit asserted before disabling the USART or entering the power saving mode. The TC bit can be cleared by writing 1 to TCC bit in USART_INTC register.
Page 486: Figure 17-4. Oversampling Method Of A Receive Frame Bit (Osb=0)
GD32F1x0 User Manual (NERR) status will be generated for the frame. An interrupt is generated, If the receive DMA is enabled and the ERRIE bit in USART_CTL2 register is set. If the OSB bit in USART_CTL2 register is set, the receiver gets only one sample to evaluate a bit value. In this situation, no noisy error will be detected.
Page 487: Figure 17-5. Configuration Step When Using Dma For Usart Transmission
GD32F1x0 User Manual Figure 17-5. Configuration step when using DMA for USART transmission Clear the TC bit in USART_STAT Set the address of USART_TDATA as the DMA destination address Set the address of data in internal sram as the DMA source address Set the number of data as the DMA transfer number Set other configurations of DMA,...
Page 488: Figure 17-6. Configuration Step When Using Dma For Usart Reception
GD32F1x0 User Manual Figure 17-6. Configuration step when using DMA for USART reception Set the address of USART_RDATA as the DMA source address Set the address of the buffer in internal sram as the DMA destination address Set the number of data as the DMA transfer number Set other configurations of DMA, interrupt enable, priority, etc...
Page 489: Figure 17-8. Hardware Flow Control
GD32F1x0 User Manual RTS flow control USART receiver can receive data only when the nRTS signal is low, and the signal does not go high until the data frame reception is finished. The next reception occurs when the nRTS signal goes low again. The signal keeps high when the receive register is full. CTS flow control If the TBE bit in USART_STAT is ‘0’...
Page 490: Figure 17-9. Break Frame Occurs During Idle State
GD32F1x0 User Manual RX pin, the hardware clears the RWU bit and exits the mute mode. When wake up at an idle frame, the IDLEF bit in USART_STAT is not set. When the WM bit of in USART_CTL0 register is set, the MSB bit of a frame is detected as the address flag.
Page 491: Figure 17-10. Break Frame Occurs During A Frame
GD32F1x0 User Manual Break frame occurs during a frame Figure 17-10. frame1 frame0 frame2 RX pin 1 frame time FERR data0 data1 data2 USART_RDATA LBDF Synchronous mode 17.3.9. The USART can be used for full-duplex synchronous serial communications only in master mode, by setting the CKEN bit in USART_CTL1.
Page 492: Figure 17-12. 8-Bit Format Usart Synchronous Waveform (Clen=1)
GD32F1x0 User Manual Figure 17-12. 8-bit format USART synchronous waveform (CLEN=1) IrDA SIR ENDEC mode 17.3.10. The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be reset in IrDA mode.
Page 493: Figure 17-14. Irda Data Modulation
GD32F1x0 User Manual Because the IrDA is a half-duplex protocol, the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block. Figure 17-14. IrDA data modulation Normal Start Stop tx frame TX pin RX pin Normal rx...
Page 494: Figure 17-15. Iso7816-3 Frame Format
GD32F1x0 User Manual Figure 17-15. ISO7816-3 frame format T=0 mode Comparing to the time in normal operation, the transmission time from transmit shift register to the TX pin is delayed half baud clock, and the TC flag assertion time delayed a certain value wrote in the guard time register.
Page 495 GD32F1x0 User Manual characters, the USART_RT register must be programmed to the CWT (character wait time) - 11 value, which is expressed in baudtime units, after the reception of the first character (RBNE interrupt). The USART signals to the software through the RT flag and interrupt (when RTIE bit is set), if the smartcard doesn’t send a new character in less than the CWT period after the end of the previous character.
Page 496: Table 17-3. Usart Interrupt Requests
GD32F1x0 User Manual In the ModBus/ASCII mode, the end of a block is recognized by a specific (CR/LF) character sequence. The USART manages this mechanism using the character match function by programming the LF ASCII code in the ADDR field and activating the address match interrupt (AMIE=1).
Page 497: Figure 17-16. Usart Interrupt Mapping Diagram
GD32F1x0 User Manual Interrupt event Event flag Enable Control bit Character match AMIE Receiver timeout error RTIE End of block EBIE Wakeup from deep-sleep mode WUIE All of the interrupt events are ORed together before being sent to the interrupt controller, so the USART can only generate a single interrupt request to the controller at any given time.
Page 498 GD32F1x0 User Manual 17.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 Control register 0 (USART_CTL0) 17.4.1. Address offset: 0x00 Reset value: 0x0000_0000 This register has to be accessed by word (32-bit). Reserved EBIE RTIE DEA[4:0] DED[4:0] OVSMOD AMIE...
Page 499 GD32F1x0 User Manual 1: Oversampling by 8. This bit must be kept cleared in LIN, IrDA and smartcard modes. This bit field cannot be written when the USART is enabled (UEN=1). AMIE ADDR match interrupt enable. 0: ADDR match interrupt is disabled. 1: ADDR match interrupt is enabled.
Page 500 GD32F1x0 User Manual IDLEIE IDLE line detected interrupt enable. 0: IDLE line detected interrupt disabled. 1: An interrupt will occur whenever the IDLEF bit is set in USART_STAT. Transmitter enable. 0: Transmitter is disabled. 1: Transmitter is enabled. Receiver enable 0: Receiver is disabled.
Page 501 GD32F1x0 User Manual This bit field cannot be written when both reception (REN=1) and USART (UEN=1) are enabled. RTEN Receiver timeout enable 0: Receiver timeout function disabled. 1: Receiver timeout function enabled. This bit is reserved in USART1. 22:20 Reserved Must be kept at reset value.
Page 502 GD32F1x0 User Manual 0: CK pin disabled 1: CK pin enabled This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved in USART1. Clock polarity 0: Steady low value on CK pin outside transmission window in synchronous mode. 1: Steady high value on CK pin outside transmission window in synchronous mode.
Page 503 GD32F1x0 User Manual Control register 2 (USART_CTL2) 17.4.3. Address offset: 0x08 Reset value: 0x0000_0000 This register has to be accessed by word (32-bit). Reserved WUIE WUM[1:0] SCRTNUM[2:0] Reserved DDRE OVRD CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE Bits Fields...
Page 504 GD32F1x0 User Manual Driver enable polarity mode 0: DE signal is active high 1: DE signal is active low This bit field cannot be written when the USART is enabled (UEN=1). Driver enable mode This bit is used to activate the external transceiver control, through the DE signal, which is output on the RTS pin.
Page 505 GD32F1x0 User Manual 1: RTS hardware flow control enabled, data can be requested only when there is space in the receive buffer This bit field cannot be written when the USART is enabled (UEN=1). DENT DMA enable for transmission 0: DMA mode is disabled for transmission 1: DMA mode is enabled for transmission DENR DMA enable for reception...
Page 506 GD32F1x0 User Manual Baud rate generator register (USART_BAUD) 17.4.4. Address offset: 0x0C Reset value: 0x0000_0000 This register has to be accessed by word (32-bit). This register cannot be written when the USART is enabled (UEN=1). Reserved BRR [15:4] BRR[3:0] Bits Fields Descriptions 31:16...
Page 507 GD32F1x0 User Manual In IrDA Low-power mode, the division factor is the prescaler value. 00000000: Reserved - do not program this value. 00000001: divides the source clock by 1. 00000010: divides the source clock by 2. In IrDA normal mode, 00000001: can be set this value only.
Page 508 GD32F1x0 User Manual to 1, the block length counter is reset. 23:0 RT[23:0] Receiver timeout threshold These bits are used to specify receiver timeout value in terms of number of baud clocks. In standard mode, the RTF flag is set if no new start bit is detected for more than the RT value after the last received character.
Page 509 GD32F1x0 User Manual Status register (USART_STAT) 17.4.8. Address offset: 0x1C Reset value: 0x0000_00C0 This register has to be accessed by word (32-bit). Reserved Reserved CTSF LBDF RBNE IDLEF ORERR NERR FERR PERR Bits Fields Descriptions 31:23 Reserved Must be kept at reset value. Receive enable acknowledge flag.
Page 510 GD32F1x0 User Manual when wakeup on IDLEIE mode is selected. Send break flag 0: No break character is transmitted. 1: Break character will be transmitted. This bit indicates that a send break character was requested. Set by software, by writing 1 to the SBKCMD bit in the USART_CMD register. Cleared by hardware during the stop bit of break transmission.
Page 511 GD32F1x0 User Manual 1: A change occurred on the nCTS status line. An interrupt will occur if the CTSIE bit is set in USART_CTL2. Set by hardware when the nCTS input toggles. Cleared by writing 1 to CTSC bit in USART_INTC register. LBDF LIN break detected flag .
Page 512 GD32F1x0 User Manual 0: No overrun error is detected. 1: Overrun error is detected. An interrupt will occur if the RBNEIE bit is set in USART_CTL0. In multibuffer communication, an interrupt will occur if the ERRIE bit is set in USART_CTL2. Set by hardware when the word in the receive shift register is ready to be transferred into the USART_RDATA register while the RBNE bit is set.
Page 513 GD32F1x0 User Manual Bits Fields Descriptions 31:21 Reserved Must be kept at reset value. Wakeup from deep-sleep mode clear Writing 1 to this bit clears the WUF bit in the USART_STAT register. This bit is reserved in USART1. 19:18 Reserved Must be kept at reset value ADDR match clear Writing 1 to this bit clears the AMF bit in the USART_STAT register.
Page 514 GD32F1x0 User Manual Receive data register (USART_RDATA) 17.4.10. Offset: 0x24 Reset value: Undefined This register has to be accessed by word (32-bit). Reserved Reserved RDATA[8:0] Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. RDATA[8:0] Receive data value The received data character is contained in these bits.
Page 515 GD32F1x0 User Manual...
Page 516: Figure 18-1. I2C Module Block Diagram
GD32F1x0 User Manual Inter-integrated circuit interface (I2C) 18.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard-mode and fast-mode as well as CRC calculation and checking, SMBus (system management bus) and PMBus (power management bus).
Page 517: Table 18-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32F1x0 User Manual Figure 18-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register SMBA/Rxframe Control Registers Timing and Control Logic Txframe Status Flags DMA/ Interrupts Table 18-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) Term Description...
Page 518: Figure 18-2. Data Validation
GD32F1x0 User Manual devices (CMOS, NMOS, bipolar) that can be connected to the I2C-bus, the voltage levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V Data validation 18.3.2. The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the SDA line can only change when the clock signal on the SCL line is LOW (see Figure 18-2.
Page 519: Figure 18-4. Clock Synchronization
GD32F1x0 User Manual held LOW by the master with the longest LOW period. Masters with shorter LOW period enter a HIGH wait-state during this time. Figure 18-4. Clock synchronization CLK1 CLK2 Arbitration 18.3.5. Arbitration, like synchronization, is part of the protocol where more than one master is used in the system.
Page 520: Figure 18-6. I2C Communication Flow With 7-Bit Address
GD32F1x0 User Manual if General Call is enabled by software, the I2C slave always responds to a General Call Address (0x00). The I2C block supports both 7-bit and 10-bit address modes. An I2C master always initiates or ends a transfer using START or STOP signal and it’s also responsible for SCL clock generation.
Page 521 GD32F1x0 User Manual mode), the following software procedure should be followed if users wish to transmit data in slave transmitter mode: First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing. After enabled and configured, I2C operates in its default slave state and waits for START signal followed by address on I2C bus.
Page 522: Figure 18-10. Programming Model For Slave Receiving (10-Bit Address Mode)
GD32F1x0 User Manual Figure 18-9. Programming model for slave transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND...
Page 523: Figure 18-11. Programming Model For Master Transmitting (10-Bit Address Mode)
GD32F1x0 User Manual After the last byte is received, RBNE is set. Software reads the last byte. STPDET bit is set when I2C detects a STOP signal on I2C bus and software reads I2C_STAT0 and then writes I2C_CTL0 to clear the STPDET bit. Figure 18-10.
Page 524 GD32F1x0 User Manual Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty. Software now writes the first byte data to I2C_DATA register, but the TBE will not be cleared because the byte written in I2C_DATA is moved to internal shift register immediately.
Page 525 GD32F1x0 User Manual Figure 18-11. Programming model for master transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND...
Page 526 GD32F1x0 User Manual reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA. After the 7-bit or 10-bit address has been sent, the I2C hardware sets the ADDSEND bit and software should clear the ADDSEND bit by reading I2C_STAT0 and then I2C_STAT1. If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out.
Page 527: Figure 18-12. Programming Model For Master Receiving Using Solution A (10-Bit Address Mode)
GD32F1x0 User Manual Figure 18-12. Programming model for master receiving using Solution A (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master...
Page 528: Figure 18-13. Programming Model For Master Receiving Mode Using Solution B (10-Bit Address Mode)
GD32F1x0 User Manual If the address is in 10-bit format, software should then set START bit again to generate a repeated START signal on I2C bus and SBSEND is set after the repeated START is sent out. Software should clear the SBSEND bit by reading I2C_STAT0 and writing header to I2C_DATA.
Page 529 GD32F1x0 User Manual address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address...
Page 530 GD32F1x0 User Manual When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register. If this bit is set, the software is required to be quick enough to serve the TBE, RBNE and BTC status, otherwise, overflow or underflow situation might occur.
Page 531 GD32F1x0 User Manual related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). SMBus protocol Each message transmission on SMBus follows the format of one of the defined SMBus protocols. The SMBus protocols are a subset of the data transfer formats defined in the I2C specifications.
Page 532: Table 18-2. Event Status Flags
GD32F1x0 User Manual a less common "Host Notify Protocol", providing similar notifications which is based on the I2C multi-master mode but it can pass more data. SMBus programming flow The programming flow for SMBus is similar to normal I2C. In order to use SMBus mode, the application should configure several SMBus specific registers, respond to some SMBus specific flags and implement the upper protocols described in SMBus specification.
Page 533: Table 18-3. Error Flags
GD32F1x0 User Manual GD32F170/F190 series) SAM_V mode rxframe pin falling edge is detected (only for GD32F170/F190 series) SAM_V mode txframe pin rising edge is detected (only for GD32F170/F190 series) SAM_V mode txframe pin falling edge is detected (only for GD32F170/F190 series) Table 18-3.
Page 534 GD32F1x0 User Manual 18.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 I2C2 base address: 0x4000 C000 (only for GD32F170/F190 series) Control register 0 (I2C_CTL0) 18.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved PECTRA SRESET Reserved...
Page 535 GD32F1x0 User Manual byte. 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte. ACKEN Whether or not to send an ACK This bit is set and cleared by software and cleared by hardware when I2CEN=0.
Page 536 GD32F1x0 User Manual I2CEN I2C peripheral enable 0: I2C is disabled 1: I2C is enabled Control register 1 (I2C_CTL1) 18.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word (32-bit). Reserved Reserved DMALST DMAON BUFIE EVIE...
Page 537 GD32F1x0 User Manual I2CCLK[6:0] I2C peripheral clock frequency I2CCLK[6:0] should be the frequency of input APB1 clock in MHz which is at least 0000000 - 0000001: Not allowed 0000010 - 1001000: 2 MHz~72MHz 1001001 - 1111111: Not allowed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than 2MHz.
Page 538 GD32F1x0 User Manual Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled 1: Dual-Address mode is enabled Transfer buffer register (I2C_DATA) 18.4.5.
Page 539 GD32F1x0 User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0. 0: SMBA pin not pulled down (device mode) or no Alert detected (host mode) 1: SMBA pin pulled down and Alert address received (device mode) or Alert detected (host mode) SMBTO...
Page 540 GD32F1x0 User Manual This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, writing I2C_DATA won’t clear TBE (refer to Programming Model for detail). 0: I2C_DATA is not empty 1: I2C_DATA is empty, software can write RBNE...
Page 541 GD32F1x0 User Manual mode, address has been sent and receives the ACK from slave. SBSEND START signal is sent out in master mode This bit is set by hardware and cleared by reading I2C_STAT0 and writing I2C_DATA. 0: No START signal sent 1: START signal sent Transfer status register 1 (I2C_STAT1) 18.4.7.
Page 542 GD32F1x0 User Manual Reserved Must be kept at reset value. Transmitter or receiver This bit indicates whether the I2C is a transmitter or a receiver. It is cleared by hardware after a STOP or a START signal or I2CEN=0 or LOSTARB=1. 0: Receiver 1: Transmitter I2CBSY...
Page 543 GD32F1x0 User Manual In fast speed mode if DTCY=0: =CLKC*T =2*CLKC*T high PCLK1 PCLK1 In fast speed mode if DTCY=1: =9*CLKC*T =16*CLKC*T high PCLK1 PCLK1 Note: If DTCY is 0, when PCLK1 is an integral multiple of 3, the baud rate will be more accurate.
Page 544 GD32F1x0 User Manual Rxframe rise flag, cleared by software by writing 0 Rxframe fall flag, cleared by software by writing 0 Txframe rise flag, cleared by software by writing 0 Txframe fall flag, cleared by software by writing 0 11:10 Reserved Must be kept at reset value.
Page 545 GD32F1x0 User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 19.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 546: Figure 19-1. Block Diagram Of Spi For Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual 19.3. SPI function overview SPI block diagram 19.3.1. Figure 19-1. Block diagram of SPI for GD32F130xx and GD32F150xx devices SYSCLK Clock Generator Control Registers TxRx Control Logic MOSI TX Buffer MISO Shift Register RX Buffer Figure 19-2. Block diagram of SPI for GD32F170xx and GD32F190xx devices SYSCLK MOSI TXBuffer...
Page 547: Table 19-2. Quad-Spi Signal Description
GD32F1x0 User Manual Pin name Direction Description Master: data reception line Slave: data transmission line MISO Master with bidirectional mode: not used Slave with bidirectional mode: data transmission and reception line. Master: data transmission line Slave: data reception line MOSI Master with bidirectional mode: data transmission and reception line.
Page 548: Figure 19-3. Spi Timing Diagram In Normal Mode
GD32F1x0 User Manual Figure 19-3. SPI timing diagram in normal mode sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI D[3] D[0] D[1] D[2] D[4] D[5] D[6] D[7] LF=1 FF16=0 D[2] MISO D[1] D[5] D[6] D[7] D[0] D[3]...
Page 549: Table 19-3. Nss Function In Slave Mode
GD32F1x0 User Manual Table 19-3. NSS function in slave mode Mode Register configuration Description MSTMOD = 0 SPI slave gets NSS level from NSS Slave hardware NSS mode SWNSSEN = 0 pin. SPI slave NSS level is determined by MSTMOD = 0 the SWNSS bit.
Page 550: Table 19-5. Spi Operation Modes
GD32F1x0 User Manual Mode Register configuration Description SWNSSEN = 1 software NSS mode. SWNSS = 1 NSSDRV: Don’t care SPI operation modes 19.3.5. Table 19-5. SPI operation modes Mode Description Register configuration Data pin usage MSTMOD = 1 RO = 0 MOSI: transmission Master full-duplex BDEN = 0...
Page 551: Figure 19-5. A Typical Full-Duplex Connection
GD32F1x0 User Manual Mode Description Register configuration Data pin usage BDEN = 1 BDOEN = 1 MSTMOD = 0 Slave reception with RO = 0 MOSI: not used bidirectional connection BDEN = 1 MISO: reception BDOEN = 0 Figure 19-5. A typical full-duplex connection Figure 19-6.
Page 552: Figure 19-8. A Typical Bidirectional Connection
GD32F1x0 User Manual Figure 19-8. A typical bidirectional connection SPI initialization sequence Before transmiting or receiving data, application should follow the SPI initialization sequence described below: If master mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate, otherwise, ignore this step.
Page 553 GD32F1x0 User Manual In master mode, software should write the next data into SPI_DATA register before the transmission of current data frame is completed if it desires to generate continuous transmission. Reception sequence After the last valid sample clock, the incoming data will be moved from shift register to the reception buffer and RBNE will be set.
Page 554: Figure 19-9. Timing Diagram Of Write Operation In Quad-Spi Mode
GD32F1x0 User Manual The operation flow for transmitting in quad mode: 1. Configure clock prescaler, clock polarity, phase, etc. in SPI_CTL0 and SPI_CTL1 based on application requirements. 2. Set QMOD bit in SPI_QCTL register and then enable SPI by setting SPIEN in SPI_CTL0. 3.
Page 555: Figure 19-10. Timing Diagram Of Read Operation In Quad-Spi Mode
GD32F1x0 User Manual Figure 19-10. Timing diagram of read operation in Quad-SPI mode Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D1[6] D0[6] D0[2] D1[2] D1[7] D0[7]...
Page 556 GD32F1x0 User Manual DMA function 19.3.6. The DMA frees the application from data writing and reading process during transfer, to improve the system efficiency. DMA function in SPI is enabled by setting DMATEN and DMAREN bits in SPI_CTL1 register. To use DMA function, application should first configure DMA modules correctly, then configure SPI module according to the initialization sequence, at last enable SPI.
Page 557: Table 19-6. Spi Interrupt Requests
GD32F1x0 User Manual  Reception buffer not empty flag (RBNE) This bit is set when reception buffer is not empty, which means that one data is received and stored in the reception buffer, and software can read the data by reading the SPI_DATA register.
Page 558: Figure 19-11. Block Diagram Of I2S
GD32F1x0 User Manual 19.4. I2S function overview I2S block diagram 19.4.1. Figure 19-11. Block diagram of I2S SYSCLK I2S_MCK SPI_SCK / I2S_CK SPI_NSS / I2S_WS 16 bits TX Buffer SPI_MOSI / I2S_SD 16 bits RX Buffer There are five sub modules to support I2S function, including control registers, clock generator, master control logic, slave control logic and shift register.
Page 559: Figure 19-12. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F1x0 User Manual signal indicates the channel side. For PCM standard, the I2S_WS signal indicates frame synchronization information. The data length and the channel length are configured by the DTLEN bit and CHLEN bit in the SPI_I2SCTL register. Since the channel length must be greater than or equal to the data length, four packet types are available.
Page 560: Figure 19-15. I2S Phillips Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32F1x0 User Manual Figure 19-15. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD When the packet type is 32-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame.
Page 561: Figure 19-19. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32F1x0 User Manual Figure 19-19. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit data 16-bit 0 I2S_SD When the packet type is 16-bit data packed in 32-bit frame, only one write or read operation the transmission of to or from the SPI_DATA register is needed to complete a frame.
Page 562: Figure 19-24. Msb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32F1x0 User Manual Figure 19-24. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 24-bit data 8-bit 0 I2S_SD Figure 19-25. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS...
Page 563: Figure 19-29. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=1)
GD32F1x0 User Manual Figure 19-29. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 8-bit 0 24-bit data I2S_SD When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete the transmission of a frame.
Page 564: Figure 19-33. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=1)
GD32F1x0 User Manual (DTLEN=00, CHLEN=0, CKPL=0) Figure 19-33. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) Figure 19-34. PCM standard short frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 frame 2 32-bit data Figure 19-35. PCM standard short frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 frame 2...
Page 565: Figure 19-38. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32F1x0 User Manual Figure 19-38. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 19-39. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) The timing diagrams for each configuration of the long frame synchronization mode are shown below.
Page 566: Figure 19-44. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32F1x0 User Manual (DTLEN=10, CHLEN=1, CKPL=1) Figure 19-44. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 19-45. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 frame 2 13 bits 24-bit data 8-bit 0 Figure 19-46.
Page 567: Figure 19-48. Block Diagram Of I2S Clock Generator
GD32F1x0 User Manual I2S clock 19.4.4. Figure 19-48. Block diagram of I2S clock generator 8-bit I2SCLK Configurable I2S_MCK MCKOEN Divider MCKOEN DIV4 CHLEN Frequency dividing ratio = DIV * 2 + OF I2S_CK DIV2 The block diagram of I2S clock generator is shown as Figure 19-48.
Page 568: Figure 19-49. I2S Initialization Sequence
GD32F1x0 User Manual are four available operation modes, including master transmission mode, master reception mode, slave transmission mode, and slave reception mode. The direction of I2S interface signals for each operation mode is shown in the Table 19-9. Direction of I2S interface signals for each operation mode.
Page 569 GD32F1x0 User Manual Figure 19-49. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD...
Page 570 GD32F1x0 User Manual TBEIE bit in the SPI_CTL1 register is set. At the beginning, the transmission buffer is empty (TBE is high) and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmission buffer to the shift register (TBE goes high) immediately.
Page 571: Figure 19-50. I2S Master Reception Disabling Sequence
GD32F1x0 User Manual Figure 19-50. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTDSEL ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTDSEL !=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle...
Page 572 GD32F1x0 User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 573: Table 19-10. I2S Interrupt
GD32F1x0 User Manual Error conditions There are three error flags:  Transmission underrun error flag (TXURERR) This situation occurs when the transmission buffer is empty when the valid SCK signal starts in slave transmission mode.  Reception overrun error flag (RXORERR) This situation occurs when the reception buffer is full and a newly incoming data has been completely received.
Page 574 GD32F1x0 User Manual 19.5. Register definition SPI0/I2S0 base address: 0x4001 3000 SPI1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 Control register 0 (SPI_CTL0) 19.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). This register has no meaning in I2S mode.
Page 575 GD32F1x0 User Manual SPI_DATA register. In receive only mode, set this bit after the second last data is received. FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex mode 1: Receive-only mode SWNSSEN...
Page 576 GD32F1x0 User Manual 1: CLK pin is pulled high when SPI is idle. CKPH Clock phase selection 0: Capture the first data at the first clock transition. 1: Capture the first data at the second clock transition. Control register 1 (SPI_CTL1) 19.5.2.
Page 577 GD32F1x0 User Manual 0: Disable receive buffer DMA 1: Enable receive buffer DMA, when the RBNE bit in SPI_STAT is set, it will be a DMA request on corresponding DMA channel. Status register (SPI_STAT) 19.5.3. Address offset: 0x08 Reset value: 0x0000 0002 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
Page 578 GD32F1x0 User Manual 0: No transmission underrun error occurs. 1: Transmission underrun error occurs. This bit is set by hardware and cleared by a read operation on the SPI_STAT register. This bit is not used in SPI mode. I2SCH I2S channel side 0: The next data needs to be transmitted or the data just received is channel left.
Page 579 GD32F1x0 User Manual CRC polynomial register (SPI_CRCPOLY) 19.5.5. Address offset: 0x10 Reset value: 0x0000 0007 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved CRCPOLY[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CRCPOLY[15:0] CRC polynomial register...
Page 580 GD32F1x0 User Manual in RCU reset register is set. TX CRC register (SPI_TCRC) 19.5.7. Address offset: 0x18 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved TCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 581 GD32F1x0 User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. I2SSEL I2S mode selection 0: SPI mode 1: I2S mode This bit should be configured when SPI mode or I2S mode is disabled. I2SEN I2S enable 0: Disable I2S 1: Enable I2S This bit is not used in SPI mode.
Page 582 GD32F1x0 User Manual 11: Reserved These bits should be configured when I2S mode is disabled. These bits are not used in SPI mode. CHLEN Channel length 0: 16 bits 1: 32 bits The channel length must be equal to or greater than the data length. This bit should be configured when I2S mode is disabled.
Page 583 GD32F1x0 User Manual Quad-SPI mode control register (SPI_QCTL) of GD32F170xx and 19.5.10. GD32F190xx devices Address offset: 0x80 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved IO23_DR Reserved QMOD Bits Fields Descriptions 31:3...
Page 584 GD32F1x0 User Manual HDMI-CEC controller(HDMI-CEC) 20.1. Overview The products of the GD32F150xx series integrate the HDMI-CEC controller inside to support the CEC protocol. Consumer Electronics Control (CEC) belongs to a part of HDMI (High- Definition Multimedia Interface) standard. CEC as a kind of protocol, provides the advanced control functions of all kinds of audio-visual products in a user environment.
Page 585: Figure 20-1. Hdmi-Cec Controller Block Diagram
GD32F1x0 User Manual device is in the output state, in order to allow a wired-and connection, the CEC pin need to be configured in alternate function open drain mode, and an external 27kΩ resister is needed for pulling-up the CEC pin to a +3.3V supply voltage. Figure 20-1.
Page 586: Figure 20-3. Start Bit Timing
GD32F1x0 User Manual Information bits ENDOM The information bits are data, opcodes or addresses, dependent on context. The control bits, ENDOM and ACK, are always present and always have the same usage. Bit timing description 20.3.3. All bits timing in the message are divided into two types: Start bit and Data bit. 1) Start Bit: The start bit has to be validated by its low duration(a) and its total duration(b) showed as below: Figure 20-3.
Page 587: Figure 20-5. The Process Of Cec Line Arbitration
GD32F1x0 User Manual Time (ms) The bit start event. impedance state(logical 0). T6 as the latest time that a device is allowed to return to a high impedance 1.7ms state(logical 0). 2.05ms T7 as the earliest time for the start of a following bit. 2.4ms As a nominal data bit period.
Page 588: Table 20-3. The Relationship Betwwen Signal Free Time And Precondition
GD32F1x0 User Manual Table 20-3. The relationship betwwen Signal Free Time and precondition Signal Free Time (nominal data bit Precondition periods) Present Initiator wants to send another message ≥7 immediately after its previous message ≥5 New Initiator wants to send a message ≥3 Previous attempt to send message unsuccessful This means that there is an opportunity for other devices to gain access to the CEC line during...
Page 589: Figure 20-7. Erro Bit Period
GD32F1x0 User Manual Figure 20-7. Erro bit period Frame error CEC protocol defines that each frame of message need the acknowledgement to confirm the communication is successful. For broadcast(destination address=0xF), the ACK bit should be logic 1 and for singlecast(destination address<0xF), the ACK bit should be logic 0, otherwise the frame error occurs(TAERR/RAE flag asserted).
Page 590: Figure 20-8. The Timing Of Bit Period Long Error
GD32F1x0 User Manual expected. If BPLEIE=1, the CEC interrupt is generated after BPLE is set. When BPLE asserted, controller will stop receiving message and generate error bit if in one of the cases below: BPLEG=1 in both singlecast and broadcast BCNG=0 in broadcast Figure 20-8.
Page 591: Figure 20-9. Transmission Error Detection
GD32F1x0 User Manual Transmission error detection(TERR) The TERR is set when the initiator find low impedance on the CEC bus when it is transmitting high impedance. TERR will also generate CEC interrupt if TERRIE=1. When TERR asserted the transmission is aborted and the software can retry the transmission. TERR check window is depending on the different bit state of the frame shown as below: Figure 20-9.
Page 592: Table 20-6. Hdmi-Cec Interrupt
GD32F1x0 User Manual HDMI-CEC interrupt 20.3.7. There 13 interrupts in HDMI-CEC controller are made up of corresponding flag and interrupt enable bit: Table 20-6. HDMI-CEC Interrupt Interrupt event in HDMI-CEC Event flag Interrupt enable bit Arbitration fail ARBF ARBFIE TX Byte Request TBRIE Transmission end TEND...
Page 593 GD32F1x0 User Manual 20.4. Register definition HDMI-CEC base address: 0x4000 7800 Control register (CEC_CTL) 20.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved ENDOM STAOM CECEN Bits Fields Descriptions 31:3 Reserved Must be kept at reset value.
Page 594 GD32F1x0 User Manual Configuration register (CEC_CFG) 20.4.2. Address offset: 0x04 Reset value: 0x0000 0000 Note: This register can only be write when CECEN=0. This register has to be accessed by word(32-bit). LMEN OAD [14:0] Reserved SFTOPT BCNG BPLEG BREG BRES RTOL SFT[2:0] Bits...
Page 595 GD32F1x0 User Manual 0: Not generate an Error-bit on CEC line when detected BPLE in singlecast 1: Generate an Error-bit on CEC line when detected BPLE in singlecast BREG Generate an Error-bit when detected BRE in singlecast This bit is set and cleared by software. 0: Not generate an Error-bit on CEC line when detected BRE in singlecast 1: Generate an Error-bit on CEC line when detected BRE in singlecast BRES...
Page 596 GD32F1x0 User Manual Reserved TDATA[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. TDATA[7:0] Transmit data register These bits are write only and contain the data byte to be transmit. Receive data register (CEC_RDATA) 20.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 597 GD32F1x0 User Manual 31:13 Reserved Must be kept at reset value. TAERR Transmit ACK Error flag. This bit is set by hardware and cleared by software writing 1. The ACK bit is received 1 in singlecast and is received 0 in broadcast will assert the flag.
Page 598 GD32F1x0 User Manual in broadcast. BPSE Bit Period Short Error This bit is set by hardware and cleared by software writing 1. BPSE is asserted if a data-bit period is less than the minimal period. Bit Rising Error This bit is set by hardware and cleared by software writing 1. BRE is asserted if the rising edge in a period is occurs in unexpected time.
Page 599 GD32F1x0 User Manual TERRIE TERR Interrupt Enable. This bit is set and cleared by software. 0: TERR interrupt disable 1: TERR interrupt enable TUIE TU Interrupt Enable. This bit is set and cleared by software. 0: TU interrupt disable 1: TU interrupt enable TENDIE TEND Interrupt Enable.
Page 600 GD32F1x0 User Manual 1: RO interrupt enable RENDIE REND Interrupt Enable. This bit is set and cleared by software. 0: REND interrupt disable 1: REND interrupt enable BRIE BR Interrupt Enable. This bit is set and cleared by software. 0: BR interrupt disable 1: BR interrupt enable...
Page 601: Figure 21-1. Block Diagram Of Tsi Module
GD32F1x0 User Manual Touch sensing interface(TSI) 21.1. Overview Touch Sensing Interface (TSI) provides a convenient solution for touch keys, sliders and capacitive proximity sensing applications. The controller builds on charge transfer method. Placing a finger near fringing electric fields adds capacitance to the system and TSI is able to measure this capacitance change using charge transfer method.
Page 602: Figure 21-2. Block Diagram Of Sample Pin And Channel Pin
GD32F1x0 User Manual Touch sensing technique overview 21.3.2. There are different technologies for touch sensing, such as optical, resistive, capacitive, strain, etc. Detecting the change of a system is the key problem and goal in these technologies. The TSI module is designed to use charge transfer method which detects the capacitive change of an electrode when touched by or a finger close to it.
Page 603: Table 21-1. Pin And Analog Switch State In A Charge-Transfer Sequence
GD32F1x0 User Manual in chip. The sequence shown in Table 21-1. Pin and analog switch state in a charge- is described based on the connection of transfer sequence Figure 21-2. Block diagram of Pin, i.e. PIN0 is channel pin and PIN1 is sample pin. Sample pin and Channel Table 21-1.
Page 604: Figure 21-3. Voltage Of A Sample Pin During Charge-Transfer Sequence
GD32F1x0 User Manual Charge transfer ASW_0 and ASW_1 are closed and PIN0 is configured to input floating to transfer charge from C . The transfer time should be configured (see Register Section for detail) to ensure the full transfer after that the voltage of C and C will be equal.
Page 605: Figure 21-4. Fsm Flow Of A Charge-Transfer Sequence
GD32F1x0 User Manual Figure 21-4. FSM flow of a charge-transfer sequence IDLE(discharge) Started Buffer Time1 Extend Charge Charge enabled Spread spectrum disabled Extend Charge Buffer Time2 Vx > Vth ！(Vx > Vth) or the cycle number or the cycle number reaches MCN Charge Transfer reaches MCN...
Page 606: Table 21-2. Duration Time Of Extend Charge State In Each Cycle
GD32F1x0 User Manual Clock and duration time of states 21.3.5. There are 3 clocks in TSI module: HCLK, CTCLK and ECCLK. HCLK is system clock and drives TSI’s register and FSM. CTCLK, which is divided from HCLK with division factor defined by register CTCDIV is the clock used for calculating the duration time of the charge state and Charge Transfer state.
Page 607 GD32F1x0 User Manual When a PIN is configured in GPIO (see chapter GPIO) used by TSI, the pin’s mode is controlled by TSI. Generally, each pin has 3 modes: input, output high and output low. The mode of a channel pin or a sample pin during a charge-transfer sequence is described in which PIN0 Table 21-1.
Page 608: Table 21-3. Tsi Errors And Flags
GD32F1x0 User Manual TSI flags and interrupts 21.3.9. Table 21-3. TSI errors and flags Flag Name Description Cleared by TSI stops because all enabled samplers’ CTCF CCTCF bit in TSI_INTC sample pins reach V TSI stops because the cycle number MNERR CMNERR bit in TSI_INTC reaches the maximum value.
Page 609 GD32F1x0 User Manual 21.4. Register definition TSI base address: 0x4002 4000 Control register (TSI_CTL) 21.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by word(32-bit). CDT[3:0] CTDT[3:0] ECDT[6:0] ECEN ECDIV CTCDIV[2:0] Reserved MCN[2:0] PINMOD EGSEL TSIS TSIEN TRGMOD Bits...
Page 610 GD32F1x0 User Manual …. 1111111: 128×t ECCLK ECEN Extend Charge State Enable. 0: Extend Charge disabled 1: Extend Charge enabled ECDIV ECCLK clock division factor. ECCLK in TSI is divided from HCLK and ECDIV defines the division factor. 0: f ECCLK HCLK 1: f...
Page 611 GD32F1x0 User Manual pin detected. TSIS TSI start This bit is set by software to start a charge-transfer sequence in software trigger mode and reset by hardware when the sequence stops. After setting this bit, software can reset it to stop the started sequence manually. 0: TSI is not started 1: TSI is started.
Page 612 GD32F1x0 User Manual Reserved Reserved CMNERR CCTCF Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CMNERR Clear max cycle number error 0: Reserved 1: Clear MNERR CCTCF Clear charge-transfer complete flag 0: Reserved 1: Clear CTCF Interrupt flag register (TSI_INTF) 21.4.4.
Page 613 GD32F1x0 User Manual number reaches the value defined by MCN[2:0]. This bit is cleared by writing 1 to CCTCF bit in TSI_INTC register. 0: Charge-Transfer not complete 1: Charge-Transfer complete Pin hysteresis mode register (TSI_PHM) 21.4.5. Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by word(32-bit).
Page 614 GD32F1x0 User Manual This bit is set and cleared by software. 0: Analog switch of GxPy is open 1: Analog switch of GxPy is closed Sample configuration register (TSI_SAMPCFG) 21.4.7. Address offset: 0x20 Reset value: 0x0000 0000 This register can be accessed by word(32-bit). Reserved G5P3 G5P2...
Page 615 GD32F1x0 User Manual 0: Pin GxPy is not a channel pin 1: Pin GxPy is a channel pin Group control register (TSI_GCTL) 21.4.9. Address offset: 0x30 Reset value: 0x0000 0000 This register can be accessed by word(32-bit). Reserved Reserved Bits Fields Descriptions 31:24...
Page 616 GD32F1x0 User Manual Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:0 CYCN[13:0] Cycle number These bits reflect the cycle number for a group as soon as a charge-transfer sequence completes. They are cleared by hardware when a new charge-transfer sequence starts.
Page 617: Figure 22-1. Usbd Block Diagram
GD32F1x0 User Manual Universal Serial Bus full-speed device interface (USBD) The USBD is only available on GD32F150 series. 22.1. Overview The Universal Serial Bus full-speed device interface (USBD) module provides a device solution for implementing a USB 2.0 full-speed compliant peripheral. It contains a full-speed internal USB PHY and no more external PHY chip is needed.
Page 618: Table 22-1. Usbd Signal Description
GD32F1x0 User Manual 22.4. Signal description Table 22-1. USBD signal description I/O port Type Description VBUS Input Bus power port Input/Output Differential D- Input/Output Differential D+ Note: As soon as the USBD is enabled, these pins are connected to the USBD internal transceiver automatically.
Page 619 GD32F1x0 User Manual Each endpoint supports:  Single/Double buffer (endpoint 0 can’t use double buffer).  One endpoint buffer descriptor.  Programmable buffer starting address and buffer length.  Configurable response to a packet.  Control transfer (endpoint 0 only). Endpoint buffer The function of the device operation is to transfer a request in the memory image to and from the Universal Serial Bus.
Page 620: Figure 22-2. An Example With Buffer Descriptor Table Usage (Usbd_Baddr = 0)
GD32F1x0 User Manual Figure 22-2. An example with buffer descriptor table usage (USBD_BADDR = 0) offset 0x1FF IN endpoint 1 double buffer 0 IN endpoint 1 double buffer 1 Endpoint 0 reception buffer Endpoint 0 transmission buffer COUNT1_TX1 ADDR1_TX1 COUNT1_TX0 Endpoint 1 buffer descriptor (double buffer) ADDR1_TX0 COUNT0_RX...
Page 621: Table 22-2. Double-Buffering Buffer Flag Definition
GD32F1x0 User Manual Table 22-2. Double-buffering buffer flag definition Buffer flag Tx endpoint Rx endpoint TX_DTG (USBD_EPxCS bit 6) RX_DTG (USBD_EPxCS bit 14) SW_BUF RX_DTG (USBD_EPxCS bit 14) TX_DTG (USBD_EPxCS bit 6) The DTG bit and the SW_BUF bit are responsible for the flow control. When a transfer completes, the USB peripheral toggle the DTG bit;...
Page 622 GD32F1x0 User Manual After the transaction process is completed, an endpoint-specific interrupt is generated. In the interrupt routine, the application can process it accordingly. Transaction formatting is performed by the hardware, including CRC generation and checking. Once the endpoint is enabled, endpoint control and status register, buffer address and COUNT filed should not be modified by the application software.
Page 623 GD32F1x0 User Manual length of data is greater than actually allocated length, the excess data are not copied. This is a buffer overrun situation. A STALL handshake is sent, and this transaction fails. If an addressed endpoint is not valid, a NAK or STALL handshake packet is sent instead of the ACK, according to the endpoint status and no data is written to the endpoint data buffers.
Page 624 GD32F1x0 User Manual the data transmission or reception of data in another buffer. The DTOG bit indicates which buffer that the USB peripheral is currently using. The application software initializes the DTOG according to the first buffer to be used. At the end of each transaction, the RX_ST or TX_ST bit is set, depending on the enabled direction regardless of CRC errors or buffer-overrun conditions (if errors occur, the ERRIF bit will be set).
Page 625 GD32F1x0 User Manual  A device in the non-configured state should draw a maximum of 100mA from the USB bus.  A configured device can draw only up to what is specified in the Max Power field of the configuration descriptor. The maximum value is 500mA. ...
Page 626 GD32F1x0 User Manual Endpoint initialization sequence 1. Program USBD_EPxTBADDR or USBD_EPxRBADDR registers with transmission or reception data buffer address. 2. Program the EP_CTL and EP_KCTL bits in USBD_EPxCS register to set endpoint type and buffer kind according to the endpoint usage. 3.
Page 627 GD32F1x0 User Manual programming USBD_EPxCS register. 3. Wait for successful transfer interrupt (STIF). 4. In the interrupt handler, application needs to update user buffer length and location pointer. Then application fill the endpoint buffer with user buffer data. Last application will configure the endpoint status to be VALID to start next transfer.
Page 628 GD32F1x0 User Manual 22.7. Register definition USBD base address: 0x4000 5C00 USBD control register (USBD_CTL) 22.7.1. Address offset: 0x40 Reset value: 0x0003 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved STIE PMOUIE ERRIE WKUPIE SPSIE RSTIE SOFIE ESOFIE Reserved...
Page 629 GD32F1x0 User Manual 1: Interrupt generated when SOFIF bit in USBD_INTF register is set. ESOFIE Expected start of frame interrupt enable 0: Expected start of frame interrupt disabled 1: Interrupt generated when ESOFIF bit in USBD_INTF register is set. Reserved Must be kept at reset value RSREQ Resume request...
Page 630 GD32F1x0 User Manual rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value STIF Successful transfer interrupt flag This bit set by hardware when a successful transaction completes PMOUIF Packet memory overrun/underrun interrupt flag This bit set by hardware to indicate that the packet memory is inadequate to hold transfer data.
Page 631 GD32F1x0 User Manual This register can be accessed by half-word (16-bit) or word (32-bit). Reserved RX_DP RX_DM LOCK SOFLN[1:0] FCNT[10:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value RX_DP Receive data + line status Represent the status on the DP line RX_DM Receive data - line status Represent the status on the DM line...
Page 632 GD32F1x0 User Manual 0: The USB device disabled. No transactions handled. 1: The USB device enabled. USBDAR[6:0] USBD device address After bus reset, the address is reset to 0x00. If the enable bit is set, the device will respond on packets for function address DEV_ADDR USBD buffer address register (USBD_BADDR) 22.7.5.
Page 633: Table 22-4. Reception Status Encoding
GD32F1x0 User Manual 31:16 Reserved Must be kept at reset value RX_ST Reception successful transferred Set by hardware when a successful OUT/SETUP transaction complete Cleared by software by writing 0 RX_DTG Reception data PID toggle This bit represent the toggle data bit (0=DATA0,1=DATA1)for non-isochronous endpoint Used to implement the flow control for double-buffered endpoint Used to swap buffer for isochronous endpoint 13:12...
Page 634: Table 22-5. Endpoint Type Encoding
GD32F1x0 User Manual Table 22-5. Endpoint type encoding EP_CTL[1:0] Meaning BULK: bulk endpoint CONTROL: control endpoint ISO: isochronous endpoint INTERRUPT: interrupt endpoint Table 22-6. Endpoint kind meaning EP_CTL[1:0] EP_KCTL Meaning BULK DBL_BUF CONTROL STATUS_OUT Table 22-7. Transmission status encoding TX_STA[1:0] Meaning DISABLED: ignore all transmission requests of this endpoint STALL: STALL handshake status...
Page 635 GD32F1x0 User Manual USBD endpoint transmission buffer byte count register 22.7.8. (USBD_EPxTBCNT), x=[0..7] Address offset: [USBD_BADDR] + x * 16 + 4 USB local Address: [USBD_BADDR] + x * 8 + 2 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved EPTXCNT[9:0]...
Page 636 GD32F1x0 User Manual EPRBAR[0] Must be set to 0 USBD endpoint reception buffer byte count register 22.7.10. (USBD_EPxRBCNT), x=[0..7] Address offset: [USBD_BADDR] + x * 16 + 12 USB local Address: [USBD_BADDR] + x * 8 + 6 This register can be accessed by half-word (16-bit) or word (32-bit). Reserved BLKSIZ BLKNUM[4:0]...
Page 637 GD32F1x0 User Manual Segment LCD controller (SLCD) This chapter applies to GD32F170xx and GD32F190xx devices. 23.1. Overview The SLCD controller directly drives LCD displays by creating the AC segment and common voltage signals automatically. It can drive the monochrome passive liquid crystal display (LCD) which composed of a plurality of segments (pixels or complete symbols) that can be converted to visible or invisible.
Page 638: Figure 23-1. Slcd Block Diagram
GD32F1x0 User Manual Figure 23-1. SLCD Block Diagram SLCD Blink Clock control generator COM0...7 control signal SLCD ANALOG matrix SEG0...31 Driver SLCD data data The SLCD REG is the register of SLCD controller, which configured by APB bus, and generate interrupt to CPU.
Page 639: Figure 23-2. 1/3 Bias, 1/4 Duty
GD32F1x0 User Manual The SOF bit in SLCD_STAT register is set by the hardware at the start of the frame, and the SLCD interrupt is executed if the SOFIE bit in SLCD_CFG is set. SOF is cleared by writing 1 to the SOFC bit in SLCD_STATC register.
Page 640: Table 23-2. The Even Frame Voltage
GD32F1x0 User Manual BIAS Static 1/2 bias 1/3 bias 1/4 bias SEG active SEG inactive VSLCD VSLCD 2/3 VSLCD 1/2 VSLCD Table 23-2. The even frame voltage BIAS Static 1/2 bias 1/3 bias 1/4 bias COM active COM inactive 1/2 VSLCD 2/3 VSLCD 3/4 VSLCD SEG active...
Page 641: Figure 23-3. 1/4 Bias, 1/6 Duty
GD32F1x0 User Manual Figure 23-3. 1/4 Bias, 1/6 Duty VSLCD 3/4VSLCD COM0 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD COM2 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD COM3 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD COM5 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD SEG2 1/2VSLCD 1/4VSLCD VSLCD 3/4VSLCD SEG4 1/2VSLCD 1/4VSLCD DEAD time: The dead time is using DTD bits in SLCD_CFG register.
Page 642 GD32F1x0 User Manual Double buffer memory 23.3.5. The double buffer memory is used to ensure the coherency of the displayed information. The application access the first buffer according to modify the SLCD_DATAx registers. After writing the displayed information into the SLCD_DATAx registers, the application need to set the UPRF bit in SLCD_STAT register, then the hardware will transfer the data from the first buffer to the seconed buffer, during this time, the UPRF keeps set and the SLCD_DATAx registers are write protected.
Page 643 GD32F1x0 User Manual switched on according to setting the HDEN bit in the SLCD_CFG register. External decoupling: The VSLCD intermediate voltage rails (VSLCDrail1, VSLCDrail2, VSLCDrail3 in the figure 23- 5) can be connect to the GPIOs by configuring the SLCD_DECA bits of the SYSCFG_CFG1 register.
Page 644 GD32F1x0 User Manual 23.4. Register definition SLCD base address: 0x4000 2400 Control register (SLCD_CTL) 23.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved COMS BIAS[1:0] DUTY[2:0] VSRC SLCDON Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 645 GD32F1x0 User Manual 110: Reserved 111: Reserved VSRC SLCD Voltage source Set this bit determines which is the SLCD voltage source. 0: Internal source 1: External source (VSLCD pin) SLCDON SLCD controller start Set this bit by software to start SLCD controller. Clear this bit by software to stop SLCD controller and the SLCD controller stop at the beginning of the next frame.
Page 646 GD32F1x0 User Manual 17:16 BLKMOD[1:0] Blink mode 00: No Blink 01: Blink on SEG[0], COM[0] (1 pixel) 10: Blink on SEG[0], all COMs (up to 8 pixels depending on the programmed duty) 11: Blink on all SEGs and all COMs (all pixels) 15:13 BLKDIV[2:0] Blink frequency divider...
Page 647 GD32F1x0 User Manual 110: 6/f 111: 7/f UPDIE SLCD update done interrupt enable This bit is set and cleared by software. 0: SLCD Update Done interrupt disabled 1: SLCD Update Done interrupt enabled Reserved Must be kept at reset value. SOFIE Start of frame interrupt enable This bit is set and cleared by software.
Page 648 GD32F1x0 User Manual 0: SLCD voltage Is not ready 1: Step-up converter is enabled and ready to provide the correct voltage UPDF Update SLCD data done flag This bit is set by hardware when update SLCD data done. It is cleared by writing 1 to the UPDC bit in the SLCD_STATC register.
Page 649 GD32F1x0 User Manual UPDC SLCD data update done clear bit Set this bit to clear the UPDF flag in SLCD_STAT register. 0: No effect 1: Clear UPDF flag Reserved Must be kept at reset value. SOFC Start of frame flag clear Set this bit to clear the SOF flag in the SLCD_STAT register.
Page 650 GD32F1x0 User Manual Operational amplifiers (OPA) This chapter applies to GD32F170xx and GD32F190xx devices. Overview 24.1. There are three operational amplifiers in the MCU and the operational amplifiers can be able to route to external or internal follower. When an operational amplifier is enabled, there will be a corresponding ADC channel used to output measurement outcome.
Page 651: Figure 24-1. Opa0 Signal Route
GD32F1x0 User Manual Figure 24-1. OPA0 Signal Route Figure 24-2. OPA1 Signal Route Figure 24-3. OPA2 Signal Route DAC1 switch OPA2 matrix OPA_CTL register can select the routing for the three operational amplifiers.For OPA0-2, S3/S4 is used to connect DAC0/DAC1 to their positive input.The OPAx_PD bit can be used to power down all operational amplifiers.
Page 652: Table 24-1. Operating Mode And Calibration
GD32F1x0 User Manual and used to initialize the operational amplifier offset. But also the chip support software using the user value to trim the operational amplifier offset. During trimming operation, all switches related to the inputs of each operational amplifier must be disconnected.
Page 653 GD32F1x0 User Manual Offset cal- analog high Offset cal- analog...
Page 654 GD32F1x0 User Manual Register definition 24.4. OPA base address: 0x4000 7C5C ontrol register (OPA_CTL) 24.4.1. Address offset: 0x00 Reset value: 0x0001 0101 This register has to be accessed by word(32-bit). OPA2CA OPA1CA OPA0CA OPA_RA OPA2LP OPA2CA OPA2CA S4OPA1 Reserved S3OPA2 S2OPA2 S1OPA2 T3OPA2...
Page 655 GD32F1x0 User Manual 0: OPA2 offset calibration for N diff OFF 1: OPA2 offset calibration for N diff ON if OPA2CAL_L = 0 OPA2CAL_L OPA2 offset calibration for P diff 0: OPA2 offset calibration for P diff OFF 1: OPA2 offset calibration for P diff ON if OPA2CAL_H = 0 S3OPA2 S3 switch enable for OPA2 0: S3 switch opened...
Page 656 GD32F1x0 User Manual 1: S1 switch closed T3OPA1 T3 switch enable for OPA1 0: T3 switch opened 1: T3 switch closed OPA1PD OPA1 power down 0: OPA1 enabled 1: OPA1 disabled OPA0LPM OPA0 low power mode 0: OPA0 low power mode off 1: OPA0 low power mode on OPA0CAL_H OPA0 offset calibration for N diff...
Page 657 GD32F1x0 User Manual OT_USE Reserved OA2_TRIM_HIGH[4:0] OA2_TRIM_LOW[4:0] OA1_TRIM_HIGH[4:1] OA1_ TRIM_HI OA1 _TRIM_LOW[4:0] OA0 _TRIM_HIGH[4:0] OA0 _TRIM_LOW[4:0] GH[0] Bits Fields Descriptions OT_USER This bit is set and cleared by software; it is always read as 0. It is used to select if the OPAx offset is trimmed by the preset factory-programmed trimming values or the user programmed trimming value.
Page 658 GD32F1x0 User Manual LP_HIGH Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:25 OA2_TRIM_LP OPA2, low-power mode 5-bit offset trim value for NMOS pairs _HIGH[4:0] 24:20 OA2_TRIM_LP OPA2, low-power mode 5-bit offset trim value for PMOS pairs _LOW[4:0] 19:15 OA1_TRIM_LP...
Page 659 GD32F1x0 User Manual Programmable Current and Voltage Reference (IVREF) Overview 25.1. An application programmable current reference module is included in the MCU. When users want to use current reference, there are two different running modes are supplied. One mode named Low Power Mode and another one named High Current Mode.The difference between two modes is the current step and maximum current.
Page 660 GD32F1x0 User Manual decoupling capacitors are recommended. User Trimming 25.3.2. User can trim the IREF outputting current by programming CPT[4:0] and can trim the voltage by programming VPT[4:0].
Page 661 GD32F1x0 User Manual Register definition 25.4. IVREF base address: 0x4000 7C00 ontrol register (IVREF_CTL) 25.4.1. Address offset: 0x300 Reset value: 0x1000 0F00 This register has to be accessed by word (32-bit). VREN DECAP Reserved VPT[4:0] Reserved CREN SSEL Reserved CPT[4:0] SCMOD Reserved CSDT[5:0] Bits...
Page 662 GD32F1x0 User Manual 12:8 CPT[4:0] Current precision trim 00000: -15% …. 11111: +16% SCMOD Sink current mode 0: Source current 1: Sink current Reserved Must be kept at reset value CSDT[5:0] Current step data 000000: Default value. 000001: Step * 1 ….
Page 663 GD32F1x0 User Manual Controller area network (CAN) This chapter applies to GD32F170xx and GD32F190xx devices. Overview 26.1. CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. As CAN network interface, basic extended CAN supports the CAN protocols version 2.0A and B.
Page 664: Figure 26-1. Can Module Block Diagram
GD32F1x0 User Manual Function overview 26.3. Figure 26-1. CAN module block diagramshows the CAN block diagram. Figure 26-1. CAN module block diagram Working mode 26.3.1. The CAN interface has three working modes:  Sleep working mode  Initial working mode ...
Page 665 GD32F1x0 User Manual Initial working mode When the configuration of CAN bus communication is needed to be changed, the CAN must enter initial working mode. When IWMOD bit in CAN_CTL register is set, the CAN enters the initial working mode. Then the IWS bit in CAN_STAT register is set.
Page 666: Figure 26-2. Transmission Register
GD32F1x0 User Manual FIFOs, the RX pin is disconnected from the CAN network and the TX pin can still send messages to the CAN network. Setting LCMOD bit in CAN_BT register to enter loopback communication mode, while clearing it to leave. Loopback communication mode is useful for self-test. Loopback and silent communication mode Loopback and silent communication mode means the RX and TX pins are disconnected from the CAN network while the transmitted messages are transferred into the RX FIFOs.
Page 667: Figure 26-3. State Of Transmission Mailbox
GD32F1x0 User Manual set TEN bit in CAN_TMIx register to prepare for starting the transmission (pending state). If more than one mailbox is in the pending state, they need scheduling the transmission (scheduled state). A mailbox with highest priority enters into transmit state and starts transmitting the message (transmit state).
Page 668: Figure 26-4. Reception Register
GD32F1x0 User Manual in CAN_TSTAT are set and state changes to be empty. In case that the transmission is failed, the state changes to be scheduled and then the abort of transmission can be done immediately. Priority When more than one transmit mailbox is pending, the transmission order is given by the TFO bit in CAN_CTL register.
Page 669: Figure 26-5. 32-Bit Filter
GD32F1x0 User Manual CAN_RFIFO0 and CAN_RFIFO1. If at least one frame has been stored in the Rx FIFO0, the frame data is stored in the CAN_RFIFOMI0, CAN_RFIFOMP0, CAN_RFIFOMDATA00 and CAN_RFIFOMDATA10 registers. After reading the current frame, set RFD bit in CAN_RFIFO0 to release a frame in the Rx FIFO and the software can read the next frame.
Page 670: Figure 26-6. 16-Bit Filter
GD32F1x0 User Manual Figure 26-6. 16-bit filter FDATA[31:21] FDATA[20:16] FDATA[15:5] FDATA[4:0] SFID[10:0] FT FF EFID[17:15] SFID[10:0] FT FF EFID[17:15] Mask mode In mask mode, the identifier registers are associated with mask registers which specifies the bits of the identifier are handled as “must match” (when the bit in mask register is ‘1’) or as “don’t care”...
Page 671: Table 26-1. 32-Bit Filter Number
GD32F1x0 User Manual Table 26-1. 32-bit filter configured as 32-bit list mode. The filter number is shown in number. Table 26-1. 32-bit filter number Filter Bank Filter Data Register Filter Number F0DATA0-32bit-ID F0DATA1-32bit-Mask F1DATA0-32bit-ID F1DATA1-32bit-ID Associated FIFO 28 banks can be associated with FIFO0 or FIFO1. If the bank is associated with FIFO0, the frames passed the bank will be stored in the FIFO0.
Page 672 GD32F1x0 User Manual Filter Filter Filter Filter FIFO0 Active FIFO1 Active Bank Nunber Bank Nunber F7DATA0[31:16]-16bit-ID F6DATA0[31:16]-16bit-ID F7DATA1[15:0]-16bit-ID F6DATA1[15:0]-16bit-ID F7DATA1[31:16]-16bit-ID F6DATA1[31:16]-16bit-ID F8DATA0[15:0]-16bit-ID F10DATA0[15:0]-16bit-ID F10DATA0[31:16]-16bit- F8DATA0[31:16]-16bit-ID Mask F8DATA1[15:0]-16bit-ID F10DATA1[15:0]-16bit-ID F10DATA1[31:16]-16bit- F8DATA1[31:16]-16bit-ID Mask F9DATA0[15:0]-16bit-ID F11DATA0[15:0]-16bit-ID F9DATA0[31:16]-16bit- F11DATA0[31:16]-16bit- Mask F9DATA1[15:0]-16bit-ID F11DATA1[15:0]-16bit-ID F9DATA1[31:16]-16bit- F11DATA1[31:16]-16bit- Mask F12DATA0-32bit-ID F13DATA0-32bit-ID...
Page 673 GD32F1x0 User Manual Communication parameters 26.3.7. Automatic retransmission forbid mode This mode has been implemented in order to fulfill the requirement of the time-triggered communication option of the CAN standard. To configure the hardware in this mode the ARD bit in the CAN_CTL register must be set. In this mode, each transmission is implemented only once.
Page 674: Figure 26-11. The Bit Time
GD32F1x0 User Manual Figure 26-11. The bit time The resynchronization Jump Width (SJW): it can be lengthened or shortened to compensate for the Synchronization error of the CAN network node. It is programmable from 1 to 4 time quanta. A valid edge is defined as the first toggle in a bit time from dominant to recessive bus level before the controller sends a recessive bit.
Page 675 GD32F1x0 User Manual Furthermore, the CAN hardware provides detailed information on the current error status in CAN_ERR register. By using the CAN_INTEN register (ERRIE bit, etc.), the software can control the interrupt generation when error is detected. Bus-Off recovery The CAN controller is in Bus-Off state when TECNT is over than 255. In This state, BOERR bit is set in CAN_ERR register, and no longer able to transmit and receive messages.
Page 676 GD32F1x0 User Manual RX FIFO0 overrun: RFO0 bit in the CAN_RFIFO0 register is set and RFOIE0 in – CAN_INTEN register is set. Receive FIFO1 interrupt The receive FIFO1 interrupt can be generated by the following conditions: RX FIFO1 not empty: RFL1 bits in the CAN_RFIFO1 register are not ‘00’ and –...
Page 677: Figure 26-12. Can Phy Connection
GD32F1x0 User Manual Figure 26-12. CAN PHY connection diode diode CANH CANL diode diode Configure the PA5/PA6 to analog input mode. Enable the CAN clock. Set PHYEN bit and PDMODE if needed in CAN_PHYCTL register. Configure CAN registers as usual, same as not in CAN PHY mode.
Page 678 GD32F1x0 User Manual Register definition 26.4. CAN0 base address : 0x4000 6400 CAN1 base address : 0x4000 6800 Control register (CAN_CTL) 26.4.1. Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit). Reserved SLPWMO SWRST Reserved ABOR RFOD...
Page 679 GD32F1x0 User Manual 0: The sleeping working mode is left manually by software 1: The sleeping working mode is left automatically by hardware Automatic retransmission disable 0: Enable automatic retransmission 1: Disable automatic retransmission RFOD Rx FIFO overwrite disable 0: Enable Rx FIFO overwrite when Rx FIFO is full and overwrite the FIFO with the incoming frame 1: Disable Rx FIFO overwrite when Rx FIFO is full and discard the incoming frame Tx FIFO order...
Page 680 GD32F1x0 User Manual LASTRX Last sample value of RX pin Receiving state 0: CAN is not working in the receiving state 1: CAN is working in the receiving state Transmitting state 0: CAN is not working in the transmitting state 1: CAN is working in the transmitting state Reserved Must be kept at reset value.
Page 681 GD32F1x0 User Manual Initial working state This bit is set by hardware when the CAN enters initial working mode after setting IWMOD bit in CAN_CTL register. If the CAN leaves normal working mode to initial working mode, it must wait the current frame transmission or reception to be completed.
Page 682 GD32F1x0 User Manual 1: Transmit mailbox 1 empty TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24 NUM[1:0] These bits are the number of the Tx FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.
Page 683 GD32F1x0 User Manual next transmit starts. MAL1 Mailbox 1 arbitration lost This bit is set when the arbitration lost occurs. This bit is reset by writting 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit is reset by hardware when next transmit starts.
Page 684 GD32F1x0 User Manual Receive message FIFO0 register (CAN_RFIFO0) 26.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved RFD0 RFO0 RFF0 Reserved RFL0[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. RFD0 Rx FIFO0 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO0.
Page 685 GD32F1x0 User Manual Reserved RFD1 RFO1 RFF1 Reserved RFL1[1:0] rc_w0 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. RFD1 Rx FIFO1 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO1. This bit is reset by hardware when the dequeuing is done.
Page 686 GD32F1x0 User Manual Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. SLPWIE Sleep working interrupt enable 0: Sleep working interrupt disabled 1: Sleep working interrupt enabled Wakeup interrupt enable 0: Wakeup interrupt disabled 1: Wakeup interrupt enabled ERRIE Error interrupt enable 0: Error interrupt disabled...
Page 687 GD32F1x0 User Manual RFFIE0 Rx FIFO0 full interrupt enable 0: Rx FIFO0 full interrupt disabled 1: Rx FIFO0 full interrupt enabled RFNEIE0 Rx FIFO0 not empty interrupt enable 0: Rx FIFO0 not empty interrupt disabled 1: Rx FIFO0 not empty interrupt enabled TMEIE Transmit mailbox empty interrupt enable 0: Transmit mailbox empty interrupt disabled...
Page 688 GD32F1x0 User Manual Whenever the CAN enters Bus-Off state, the bit will be set by hardware. PERR Passive error Whenever the TECNT or RECNT is greater than 127, the bit will be set by hardware. WERR Warning error Whenever the TECNT or RECNT is greater than or equal to 96, the bit will be set by hardware.
Page 689 GD32F1x0 User Manual Transmit mailbox identifier register (CAN_TMIx) (x=0..2) 26.4.9. Address offset: 0x180, 0x190, 0x1A0 Reset value: 0xXXXX XXXX (bit0=0) This register has to be accessed by word(32-bit). SFID[10:0]/EFID[28:18] EFID[17:13] EFID[12:0] Bits Fields Descriptions 31:21 SFID[10:0]/EFID[28:18 The frame identifier SFID[10:0]: Standard format frame identifier EFID[28:18]: Extended format frame identifier 20:16 EFID[17:13]...
Page 690 GD32F1x0 User Manual TS[15:0] Reserved TSEN Reserved DLENC[3:0] Bits Fields Descriptions 31:16 TS[15:0] Time stamp The time stamp of frame in transmit mailbox. 15:9 Reserved Must be kept at reset value. TSEN Time stamp enable 0: Time stamp disabled 1: Time stamp enabled. The TS[15:0] will be transmitted in the DB6 and DB7 in This bit is available when the TTC bit in CAN_CTL is set.
Page 691 GD32F1x0 User Manual Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) 26.4.12. Address offset: 0x18C, 0x19C, 0x1AC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit). DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0] Bits Fields Descriptions 31:24 DB7[7:0] Data byte 7 23:16 DB6[7:0] Data byte 6 15:8...
Page 692 GD32F1x0 User Manual Frame format 0: Standard format frame 1: Extended format frame Frame type 0: Data frame 1: Remote frame Reserved Must be kept at reset value. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1) 26.4.14. Address offset: 0x1B4, 0x1C4 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit).
Page 693 GD32F1x0 User Manual DB1[7:0] DB0[7:0] Bits Fields Descriptions 31:24 DB3[7:0] Data byte 3 23:16 DB2[7:0] Data byte 2 15:8 DB1[7:0] Data byte 1 DB0[7:0] Data byte 0 Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) 26.4.16. Address offset: 0x1BC, 0x1CC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit).
Page 694 GD32F1x0 User Manual Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:8 HBC1F[5:0] Header bank of CAN1 filter These bits are set and cleared by software to define the first bank for CAN1 filter. Bank0 ~ Bank HBC1F-1 is used for CAN0. Bank HBC1F ~ Bank27 is used for CAN1. When set 0, no bank used for CAN0.
Page 695 GD32F1x0 User Manual Reserved FS27 FS26 FS25 FS24 FS23 FS22 FS21 FS20 FS19 FS18 FS17 FS16 FS15 FS14 FS13 FS12 FS11 FS10 Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:0 Filter scale 0: Filter x with 16-bit scale 1: Filter x with 32-bit scale Filter associated FIFO register (CAN_FAFIFO) (Just for CAN0) 26.4.20.
Page 696 GD32F1x0 User Manual FW15 FW14 FW13 FW12 FW11 FW10 Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:0 Filter working 0: Filter x working disabled 1: Filter x working enabled Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1) (Just for CAN0) 26.4.22.
Page 697 GD32F1x0 User Manual Reserved POMOD Reserved PHYEN Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. POMOD CAN PHY output driver control register This bit set and cleared by software. 00: Low Slope Mode 01: Middle Slope Mode 10: High Slope Mode 11: High Speed Mode(Default) Reserved...
Page 698: Table 27-1. List Of Abbreviations Used In Register
GD32F1x0 User Manual Appendix 27.1. List of abbreviations used in register Table 27-1. List of abbreviations used in register abbreviations for Descriptions registers read/write (rw) Software can read and write to this bit. read-only (r) Software can only read this bit. write-only (w) Software can only write to this bit.
Page 699 GD32F1x0 User Manual 27.3. Available peripherals For availability of peripherals and their number across all MCU series types, refer to the corresponding device data datasheet.
Page 700 GD32F1x0 User Manual Revision history Table 28-1. Revision history Revision No. Description Date Initial Release Mar.18, 2014 Add GD32F170/190 Products Jan.15, 2016 Jun.24, 2016 Adapt To New Name Convention 3.0.1 Mar.30, 2017 Proofreading 3.1.0 Proofreading Jan.22, 2018 1. Modify the format according to the version specification. 2.
Page 701 GD32F1x0 User Manual Revision No. Description Date 9. Update Analog to digital converter (ADC) chapter.
Page 702 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.

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