Related Manuals for GigaDevice Semiconductor GD32G5 Series
Summary of Contents for GigaDevice Semiconductor GD32G5 Series
- Page 1 GigaDevice Semiconductor Inc. GD32G5xx Hardware Development Guide Application Note AN193 Revision 1.0 （Sep. 2024）...
-
Page 2: Table Of Contents
AN193 GD32G5xx Hardware Development Guide Table of Contents Table of Contents ......................2 List of Figures ........................ 4 List of Tables ........................5 1. Introduction ......................6 2. Hardware design ...................... 7 2.1. Power supply ....................... 7 2.1.1. Backup domain ........................7 2.1.2. - Page 3 AN193 GD32G5xx Hardware Development Guide 5. Revision history ..................... 38...
-
Page 4: List Of Figures
AN193 GD32G5xx Hardware Development Guide List of Figures Figure 2-1. GD32G5xx series Power supply overview ................. 7 Figure 2-2. VREF Connection ......................... 10 Figure 2-3. GD32G5xx Recommended Power Supply Design..............10 Figure 2-4. Waveform of the POR/PDR ......................11 Figure 2-5. Waveform of the BOR ........................12 Figure 2-6. -
Page 5: List Of Tables
AN193 GD32G5xx Hardware Development Guide List of Tables Table 1-1. Applicable Products ........................6 Table 2-1. V Operating voltage range ....................9 Table 2-2. Clock output source select ......................18 Table 2-3. Low-speed clock output source select ..................19 Table 2-4. Boot modes ............................. 20 Table 2-5. -
Page 6: Introduction
AN193 GD32G5xx Hardware Development Guide Introduction This document is specifically designed for developers of the 32-bit general-purpose MCU GD32G5xx series based on the Arm ® Cortex ® -M33 architecture, providing an overall introduction to the hardware development of the GD32G5xx series products, such as power supply, reset, clock, boot mode settings, and download debugging. -
Page 7: Hardware Design
AN193 GD32G5xx Hardware Development Guide Hardware design Power supply 2.1. The operating voltage range for V in the GD32G5xx series is 1.71 V to 3.6 V. As shown in Figure 2-1. GD32G5xx series Power supply overview, the GD32G5xx series devices have three power domains, including the V domain, the 1.1 V domain, and the backup domain. - Page 8 AN193 GD32G5xx Hardware Development Guide PC13 to PC15. In order to ensure the content of the Backup domain registers and the RTC supply, when V supply is shut down, VBAT pin can be connected to an optional standby voltage supplied by a battery or by another source. The power switch is controlled by the power down reset circuit in the V domain.
-
Page 9: Vdd / Vdda Domain
AN193 GD32G5xx Hardware Development Guide domain 2.1.2. DD / The V power domain includes two parts: V domain and V domain. If V is not equal to V , the voltage difference between the two should not exceed 300mV (the internal and V of the chip are connected through a back-to-back diode). -
Page 10: Power Supply Design
AN193 GD32G5xx Hardware Development Guide Figure 2-2. VREF Connection Connect to the VREFP external circuit VREF 0.1uF/ 1uF+10nF Power supply design 2.1.4. The system needs a stable power supply. There are some important things to pay attention to when developing and using: ◼... -
Page 11: Reset And Power Management
AN193 GD32G5xx Hardware Development Guide Note： 1、 All decoupling capacitors must be placed close to the corresponding VDD, VDDA, VBAT, VREFP pins of the chip. 2、 When the MCU power supply voltage is unstable or there is a risk of voltage drop, it is recommended to adjust the 4.7uF capacitor not less than 10uF. -
Page 12: Figure 2-5. Waveform Of The Bor
AN193 GD32G5xx Hardware Development Guide bits in option bytes. Notice that the POR/PDR circuit is always implemented regardless of BOR_TH bits in option bytes is 0b11 or not. shows the Figure 2-5. Waveform of the BOR relationship between the supply voltage and the BOR reset signal. V , which defined in the BOR_TH bits in option bytes, indicates the threshold of BOR on reset.The Vhyst is 100mV. -
Page 13: Figure 2-6. Waveform Of The Lvd Threshold
AN193 GD32G5xx Hardware Development Guide Figure 2-6. Waveform of the LVD threshold threshold hyst LVD output The MCU reset source can be searched by the register RCU_RSTSCK. This register can only clear the flag bit after power-on reset. Therefore, during use, after the reset source is obtained, the reset flag can be cleared through the RSTFC control bit, so that a watchdog reset or other reset events can be more accurately reflected in the RCU_RSTSCK register: Figure 2-7. -
Page 14: Clock
AN193 GD32G5xx Hardware Development Guide Figure 2-9. Recommend External Reset Circuit External reset circuit 10 kΩ NRST 100 nF GD32G5xx Note: Internal pull-up resistance R = 40 kΩ. You are advised to use an external pull-up resistance of 10 kΩ to ensure that voltage interference does not cause chip abnormalities. If the influence of static electricity is considered, an ESD protection diode can be placed at the NRST pin. -
Page 15: External High-Speed Crystal Oscillator Clock (Hxtal)
AN193 GD32G5xx Hardware Development Guide Figure 2-10. GD32G5xx Clock Tree HCLK AHB enable to AHB bus, Cortex-M33, SRAM, DMA, peripherals SCS[1:0] ÷ 8 (to Cortex-M33 SysTick) FCLK (free running clock) CK_IRC8M 8 MHz TIMER1,2,3,4,5,6 IRC8M if(APB1 prescaler = 216 MHz max CK_SYS CK_AHB CK_HXTAL... -
Page 16: Figure 2-10. Hxtal External Crystal Circuit
AN193 GD32G5xx Hardware Development Guide HXTAL can also use a bypass input mode to input a clock source (such as a 1 – 48 MHz Figure 2-12. HXTAL External Clock active crystal oscillator). The details are shown in Circuit. When bypassing to an external circuit, the signal is connected to the OSC_IN pin, and the OSC_OUT pin is left floating. -
Page 17: External Low-Speed Crystal Oscillator Clock (Lxtal)
AN193 GD32G5xx Hardware Development Guide The traces connecting the resonator to the MCU clock pins may cause inconsistent lengths of the traces connected to the OSCOUT and OSCIN pins due to the space constraints of the PCB layout. This will make the stray capacitances introduced by the two PCB traces inconsistent, so that the load capacitances on both sides of the resonator cannot be equal in value, and there needs to be a difference to match the actual PCB board. -
Page 18: Clock Output Capability (Ckout)
AN193 GD32G5xx Hardware Development Guide remains floating. For the size of the external matching capacitor, please refer to the formula: C 2*(C ), where C is the stray capacitance of the PCB and MCU pins, the empirical LOAD value is between 2pF ~ 7pF, and 5pF is recommended as a reference value calculation. When it is recommended to use an external crystal, try to choose a crystal load capacitance of about 10pF, so that the externally connected matching capacitors C can be 10pF, and the PCB layout should be as close to the crystal pin as possible. -
Page 19: Hxtal Clock Monitor（Ckm
AN193 GD32G5xx Hardware Development Guide The CK_LXTAL and CK_IRC32K clock signals also can be output on LSCK_OUT pin, even in Deepsleep mode and Standby mode，which seleted by LSCKOUTSEL in the backup Table 2-3. Low-speed domain control register (RCU_BDCTL). The details are shown in clock output source select Table 2-3. -
Page 20: Figure 2-14. Recommend Boot Circuit Design
AN193 GD32G5xx Hardware Development Guide Table 2-4. Boot modes Boot mode configuration Selected nBOOT1 BOOT0 nSWBT0 boot area BOOTLK nBOOT0 bit Main Flash memory Main Flash memory Main Flash memory System memory System memory Embedded SRAM0 Embedded SRAM0 ® ® After power-on sequence or a system reset, the Arm Cortex -M33 processor fetches the... -
Page 21: Typical Peripheral Modules
AN193 GD32G5xx Hardware Development Guide Note: After the MCU is running, if the BOOT state is changed, it will take effect after the system is reset. MCU. Typical Peripheral Modules 2.4. GPIO Circuit 2.4.1. GD32G5xx can support up to 107 universal I/O pins（GPIO） ，including PA0 ~ PA15，PB0 ~ PB15，PC0 ~ PC15，PD0 ~ PD15，PE0 ~ PE15，PF0 ~ PF15，PG0 ~ PG10.Each on-chip device uses it to implement logical input / output functions. -
Page 22: Adc Circuit
AN193 GD32G5xx Hardware Development Guide The same label PIN in multiple groups can only configure one port as an external interrupt. For example, PA0, PB0, and PC0 only support one of the three IO ports to generate external interrupts, and do not support three external interrupt modes. Non-5V tolerance I/O, external voltage over V , may generate perfusion current. -
Page 23: Internal Temperature Sensor Calibration
AN193 GD32G5xx Hardware Development Guide relationship between input impedance and sampling period is as shown in Table 2-5. Relationship between Sampling Period and External Input Impedance at fADC = 40MHz. Table 2-5. Relationship between Sampling Period and External Input Impedance at f = 40MHz. -
Page 24: Dac Circuit
AN193 GD32G5xx Hardware Development Guide value at 25° C, the typical value please refer to the datasheet. temperature Avg_Slope: Average Slope for curve between Temperature vs. V , the typical temperature value please refer to the datasheet. Using high-precision temperature sensors: 1. -
Page 25: Cmp Circuit
AN193 GD32G5xx Hardware Development Guide The DAC conversion can be triggered by software or rising edge of external trigger source. The DAC external trigger is enabled by setting the DTENx bits in the DAC_CTL0 register. The DAC external triggers are selected by the DTSELx bits in the DAC_CTL0 register, which is shown as Table 2-6. -
Page 26: Table 2-7. Cmp Inputs And Outputs Summary
AN193 GD32G5xx Hardware Development Guide These I / Os must be configured in analog mode in the GPIOs registers before they are selected as CMP inputs, Table 2-7. CMP inputs and outputs summary details the inputs and outputs of the CMP. Table 2-7. -
Page 27: Figure 2-18. Cmp Hysteresis
AN193 GD32G5xx Hardware Development Guide CMP0 CMP1 CMP2 CMP3 CMP4 CMP5 CMP6 CMP7 CMP outputs BREAK0(TIMER0, TIMER7, TIMER14, TIMER15, TIMER16, TIMER19) connected to internal BREAK1(TIMER0, TIMER7, TIMER19) signals In order to avoid spurious output transitions that caused by the noise signal, a programmable hysteresis is designed to force the hysteresis value by configuring CMPx_CS register. -
Page 28: Hrtimer
AN193 GD32G5xx Hardware Development Guide For more detailed information on the functions and usage of the CMP peripheral, please refer to the《GD32G533_553_User_Manual》、《AN198 CMP usage in GD32G5 Series》. HRTIMER 2.4.6. HRTIMER has a high-resolution counting clock(Master_TIMER，Slave_TIMERx (x=0..7)) and can be used for high-precision timing. It can generate 16 high resolution and flexible digital signals to control motor or be used for power management applications. - Page 29 AN193 GD32G5xx Hardware Development Guide Table 2-8. Resolution with f = 216MHz HRTIMER_CK CNTCKDIV[2:0] Resolution HRTIMER_PSCCK 3'b000 216*32MHz = 6.912GHz 144.68ps 3'b001 216*16MHz = 3.456GHz 289.35ps 3'b010 216*8MHz = 1.728GHz 578.70ps 3'b011 216*4MHz = 864MHz 1.16ns 3'b100 216*2MHz = 432MHz 2.31ns 3'b101 216*1MHz = 216MHz...
-
Page 30: Power Saving Modes
AN193 GD32G5xx Hardware Development Guide The immediately update mode of HRTIMER is available for compare 0 reset event and compare 2 reset event, and this mode is enabled by setting IMUPDxV bit in HRTIMER_STxCTL1 register. The output PWM waveform is updated immediately without waiting for the end of the current period when the immediate update mode is enabled. -
Page 31: Download The Debug Circuit
AN193 GD32G5xx Hardware Development Guide Figure 2-22. Recommend Standby external wake-up pin circuit design PC13 Wakeup 10 kΩ Note: In this mode, attention should be paid to the circuit design. If there is a series resistance between the WKUP pin and V , additional power consumption may be added. -
Page 32: Figure 2-22. Recommend Jtag Wiring Reference Design
AN193 GD32G5xx Hardware Development Guide Figure 2-23. Recommend JTAG wiring reference design 10 kΩ JTMS PA13 PA14 JTCK JTDI PA15 JTDO NJTRST RESET NRST 10 kΩ JTAG GD32G5xx Note: After reset, the debug related ports are in input pull-up / pull-down mode, where: PA13: SWDIO in pull-up mode PA14: SWCLK in pull-down mode Table 2-11. -
Page 33: Reference Schematic Design
AN193 GD32G5xx Hardware Development Guide eference Schematic Design 2.7. Figure 2-25. GD32H7xx Recommend Reference Schematic Design 8M/25M HC-49S-G20SSA-8MHz OSC_IN 50V/20pF BOOT OSC_OUT PA10 PD10 PA10 PD10 PA11 PD11 50V/20pF PA11 PD11 PA12 PD12 PA12 PD12 PA13 PD13 BOOT0 PA13 PD13 PA14 PD14 32.768k... -
Page 34: Pcb Layout Design
AN193 GD32G5xx Hardware Development Guide PCB Layout Design In order to enhance the functional stability and EMC performance of the MCU, it is not only necessary to consider the performance of the supporting peripheral components, but also the PCB Layout. In addition, when conditions permit, try to choose a PCB design solution with an independent GND layer and an independent power supply layer, which can provide better EMC performance. -
Page 35: Reset Circuit
AN193 GD32G5xx Hardware Development Guide Figure 3-2. Recommend Clock Pin Layout Design (passive crystal) Note: The crystal should be as close to the MCU clock pin as possible, and the matching capacitor should be as close as possible to the crystal. The whole circuit should be on the same layer as the MCU, and the wiring should not go through the layer as much as possible. -
Page 36: Fan-Out For Wlcsp Package
AN193 GD32G5xx Hardware Development Guide Note: The resistance and capacitance of the reset circuit should be as close as possible to the NRST pin of the MCU, and the NRST trace should be kept away from devices with strong interference risk and high-speed traces as far as possible. If conditions permit, it had better to wrap the NRST traces for better shielding effect. -
Page 37: Package Description
AN193 GD32G5xx Hardware Development Guide Package Description The GD32H7xx series comes in five packaging forms, LQFP128、WLCSP81、LQFP64、 LQFP64 and QFN48. Table 4-1. Package Description Ordering code Package GD32G553QxT6 LQFP128（14x14, 0.4 pitch） GD32G533QxT6 GD32G553MEY6 WLCSP81（4x4, 0.4 pitch） GD32G533MEY6 GD32G553RET6 LQFP64（10x10, 0.5 pitch） GD32G533RxT6 GD32G553CET6 LQFP48(7x7, 0.5 pitch) -
Page 38: Table 5-1. Revision History
AN193 GD32G5xx Hardware Development Guide Revision history Table 5-1. Revision history Revision No. Description Date Initial Release Sep.15, 2024... -
Page 39: Important Notice
Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.
Need help?
Do you have a question about the GD32G5 Series and is the answer not in the manual?
Questions and answers