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GigaDevice Semiconductor GD32F1 0 Series User Manual

GigaDevice Semiconductor GD32F1 0 Series User Manual

Arm cortex-m3 32-bit mcu

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GigaDevice Semiconductor Inc.

GD32F1x0

™

®

ARM

Cortex

-M3 32-bit MCU

User Manual

Revision 2.0

( Jan. 2016 )

Table of Contents

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Summary of Contents for GigaDevice Semiconductor GD32F1 0 Series

Page 1 GigaDevice Semiconductor Inc. GD32F1x0 ™ ® Cortex -M3 32-bit MCU User Manual Revision 2.0 ( Jan. 2016 )
Page 2 1.3.3. On-chip Flash memory .......................... 9 1.4. Boot configuration ......................10 1.5. System configuration registers (SYSCFG) ................11 1.5.1. System configuration register 1 (SYSCFG_R1)..................11 1.5.2. System configuration register 2 (SYSCFG_R2)..................12 1.5.3. EXTI sources selection register 1 (SYSCFG_EXTISS1) ................12 1.5.4.
Page 3 GD32F1x0 User Manual 3. Flash Memory Controller (FMC)................33 3.1. Introduction ........................33 3.2. Main features ........................33 3.3. Function description ......................33 3.3.1. Flash Memory Architecture ......................... 33 3.3.2. Read operations........................... 34 3.3.3. Unlock the FMC_CMR register ......................35 3.3.4.
Page 4 GD32F1x0 User Manual 4.3.6. AHB Clock Control Register (RCC_AHBCCR) ..................79 4.3.7. APB2 Clock Control Register (RCC_APB2CCR)..................81 4.3.8. APB1 clock Control Register (RCC_APB1CCR) ..................82 4.3.9. Backup Domain Control Register (RCC_BDCR) ..................87 4.3.10. Global Control/Status Register (RCC_GCSR) ..................90 4.3.11.
Page 5 GD32F1x0 User Manual 6.1. Introduction ........................121 6.2. Main features ........................121 6.3. Function Description ......................122 6.4. CRC Registers ........................123 6.4.1. CRC Data Register (CRC_DTR) ......................123 6.4.2. CRC Free Data Register (CRC_FDTR) ....................123 6.4.3. CRC Control Register (CRC_CTLR) ...................... 124 6.4.4.
Page 6 GD32F1x0 User Manual 8.4.6. DMA channel x memory base address register (DMA_MBARx) ............147 9. Timer (TIMERx) ..................... 149 9.1. Advanced timer (TIMER1) ....................150 9.1.1. Introduction ............................150 9.1.2. Main features ............................ 150 9.1.3. Function description .......................... 150 9.1.4. TIMER1 registers ..........................
Page 7 GD32F1x0 User Manual 11.1.2. Main features ............................ 352 11.1.3. Function description .......................... 352 11.1.4. IWDG registers ........................... 354 11.2. Window watchdog (WWDG) ..................358 11.2.1. Introduction ............................358 11.2.2. Main features ............................ 358 11.2.3. Function description .......................... 358 11.2.4. WWDG registers ..........................360 Analog to Digital converter (ADC) ..............
Page 8 GD32F1x0 User Manual 12.4.13. ADC inserted data register x (ADC_IDTRx) (x= 1..4)............... 388 12.4.14. ADC regular data register (ADC_RDTR) ..................389 12.4.15. ADC oversampling control register (ADC_OVSCR) of GD32F170xx and GD32F190xx devices ..389 Digital-to-analog converter (DAC) ..............391 13.1. DAC Introduction ......................
Page 9 GD32F1x0 User Manual 14.3.1. SDA and SCL lines ..........................409 14.3.2. Data validation ........................... 410 14.3.3. START and STOP condition ......................... 410 14.3.4. Clock synchronization ........................410 14.3.5. Arbitration ............................411 14.3.6. I2C communication flow ........................411 14.3.7. Programming model .......................... 412 14.3.8.
Page 10 GD32F1x0 User Manual 15.4.2. Supported audio standards ....................... 450 15.4.3. Clock generator ..........................457 15.4.4. Operation ............................459 15.4.5. DMA features............................. 463 15.5. SPI registers ........................463 15.5.1. SPI control register 1 (SPI_CTLR1) ..................... 463 15.5.2. SPI control register 2 (SPI_CTLR2) ..................... 465 15.5.3.
Page 11 GD32F1x0 User Manual 17.3.11. Smartcard (ISO7816) mode ......................491 17.3.12. IrDA SIR ENDEC mode ........................493 17.3.13. Hardware flow control........................495 17.3.14. DMA requests ..........................496 17.3.15. Wakeup from Deep-sleep mode ....................497 17.3.16. USART interrupts ........................... 497 17.4. USART registers ......................498 17.4.1.
Page 12 GD32F1x0 User Manual 19.3.7. Power management .......................... 537 19.4. USB registers ........................ 539 19.4.1. USB control register (USB_CTLR) ....................... 539 19.4.2. USB interrupt Flag register (USB_IFR)....................540 19.4.3. USB Status register (USB_SR) ......................541 19.4.4. USB device address register (USB_AR) ....................
Page 13 GD32F1x0 User Manual 20.4.5. RTC prescaler register (RTC_PSCR) ....................567 20.4.6. RTC alarm register(RTC_ALMR) ......................567 20.4.7. RTC write protection register(RTC_WPR) ..................568 20.4.8. RTC sub second register (RTC_SSR) ....................569 20.4.9. RTC shift function control register(RTC_SHIFTCTLR)................569 20.4.10. RTC timestamp time register(RTC_TTR) ..................570 20.4.11.
Page 14 GD32F1x0 User Manual 22.3. Function Description ..................... 593 22.3.1. CEC Bus Pin ............................593 22.3.2. Message description .......................... 594 22.3.3. Bit Timing Description ........................595 22.3.4. Arbitration ............................596 22.3.5. SFT option bit description........................597 22.3.6. Error Definition ..........................597 22.3.7.
Page 15 GD32F1x0 User Manual 24.2.2. Main features ............................ 628 24.2.3. Function description .......................... 629 24.2.4. IVREF registers ........................... 629 Controller Area Network (bxCAN) ..............631 25.1. Introduction ......................... 631 25.2. Main features ....................... 631 25.3. Function description ..................... 632 25.3.1. Working mode ........................... 632 25.3.2.
Page 16 GD32F1x0 User Manual Revision history ....................662...
Page 17: Table Of Contents
GD32F1x0 User Manual List of Figures Figure 1-1. Cortex™-M3 block diagram ....................2 Figure 1-2. Series system architecture of GD32F130xx and GD32F150xx devices ....3 Figure 1-3. Series system architecture of GD32F170xx and GD32F190xx devices ....4 Figure 1-4. Memory map of GD32F130xx and GD32F150xx devices .......... 6 Figure 1-5.
Page 18 GD32F1x0 User Manual Figure 9-17. Counter timing diagram, internal clock divided by 4, TIMERx_CARL=0x63.. 161 Figure 9-18. Counter timing diagram, internal clock divided by N .......... 162 Figure 9-19. Counter timing diagram, update event with ARSE=1(counter underflow) ..162 Figure 9-20. Counter timing diagram, Update event with ARSE=1 (counter overflow) ..163 Figure 9-21.
Page 19 GD32F1x0 User Manual Figure 9-60. Counter timing diagram, internal clock divided by 1, TIMERx_CARL = 0x5 .. 215 Figure 9-61. Counter timing diagram, internal clock divided by 2 ........... 215 Figure 9-62. Counter timing diagram, internal clock divided by 4, TIMERx_CARL=0x63.. 216 Figure 9-63.
Page 21 GD32F1x0 User Manual...
Page 22 GD32F1x0 User Manual Figure 15-8. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ..450 Figure 15-9. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) ..451 Figure 15-10. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) ..451 Figure 15-11. I2S Phillips standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ..451 Figure 15-12.
Page 23 GD32F1x0 User Manual CHLEN=1, CKPL=0) ........................456 Figure 15-40. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ........................456 Figure 15-41. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ........................457 Figure 15-42. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ........................
Page 24 GD32F1x0 User Manual Figure 25-12. bxCAN PHY connection .................... 644...
Page 25 GD32F1x0 User Manual List of Tables Table 1-1. Flash module organization ....................9 Table 1-2. Flash module organization ....................9 Table 1-3. Boot modes .......................... 10 Table 2-1. Power saving mode summary ..................28 Table 3-1. Base address and size for flash memory ..............34 Table 3-2 Base address and size for flash memory ...............
Page 26 GD32F1x0 User Manual Table 15-4. Audio sampling frequency configuration and precision ........458 Table 15-5. Direction of I2S interface signals for each operation mode ........ 459 Table 15-6. I2S interrupt ........................460 Table 17-1. USART important pins description ................485 Table 17-2.
Page 27 GD32F1x0 User Manual System and memory architecture Cortex™- The system architecture of the devices of GD32F1x0 series that includes the ARM ® M3 processor, bus architecture and memory organization will be described in the following sections. The Cortex™-M3 processor is a next generation processor core which offers many new features.
Page 28: Figure 1-1. Cortex™-M3 Block Diagram
GD32F1x0 User Manual Figure 1-1. Cortex™-M3 block diagram 1.2. System architecture The system architecture of the GD32F1x0 series is shown in the following figure. The AHB matrix based on AMBA 3.0 AHB-LITE is a multi-layer AHB, which enables parallel access paths between multiple masters and slaves in the system.
Page 29: Figure 1-2. Series System Architecture Of Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual Figure 1-2. Series system architecture of GD32F130xx and GD32F150xx devices 1.2V TPIU GPIO Ports AHB2: Fma x = 72MHz POR/PDR A, B, C, D, F ARM Cortex-M3 Processor SRAM SRAM : 72MHz Controller IBus Flash : 72MHz Touch Flash Memory...
Page 30: Figure 1-3. Series System Architecture Of Gd32F170Xx And Gd32F190Xx Devices
GD32F1x0 User Manual Figure 1-3. Series system architecture of GD32F170xx and GD32F190xx devices 1.8V TPIU GPIO Ports AHB2: Fma x = 72MHz POR/PDR A, B, C, D, F ARM Cortex-M3 Processor SRAM SRAM : 72MHz Controller IBus Flash : 72MHz Touch Flash Memory...
Page 31 GD32F1x0 User Manual 1.3. Memory map Cortex™-M3 processor is structured in Harvard architecture which can use ® The ARM separate buses to fetch instructions and load/store data. The instruction code and data are both located in the same memory address space but in different address ranges. Program memory, data memory, registers and I/O ports are organized within the same linear 4-Gbyte address space which is the maximum address range of the Cortex™-M3 since it has a 32-bit bus address width.
Page 32 TIMER16 0x4001 4400 TIMER15 0x4001 4000 reserved 0x4001 3C00 USART1 0x4001 3800 reserved 0x4001 3400 SPI/I2S1 0x4001 3000 TIMER1 0x4001 2C00 0xFFFF FFFF reserved 0x4001 2800 reserved 0x4001 2400 reserved 0xE010 0000 Cortex-M3 Internal 0x4001 0800 0x1FFF FFFF reserved EXTI Peripherals 0xE000 0000 0x4001 0400...
Page 33: Figure 1-5. Memory Map Of Gd32F170Xx And Gd32F190Xx Devices
GD32F1x0 User Manual Figure 1-5. Memory map of GD32F170xx and GD32F190xx devices 0x5000 0000 reserved 0x4800 1800 Port F 0x4800 1400 reserved 0x4800 1000 Port D 0x4800 0C00 Port C 0x4800 0800 Port B 0x4800 0400 Port A 0x4800 0000 reserved 0x4002 4400 0x4002 4000...
Page 34 GD32F1x0 User Manual 1.3.1. Bit-banding In order to reduce the time of read-modify-write operations, the Cortex™-M3 processor provides a bit-banding function to perform a single atomic bit operation. The memory map includes two bit-band regions. These occupy the SRAM and Peripherals respectively. These bit-band regions map each word in an alias region of memory to a bit in a bit-band region of memory.
Page 35: Table 1-1. Flash Module Organization
GD32F1x0 User Manual when reading non-initialized locations. 1.3.3. On-chip Flash memory For GD32F130xx and GD32F150xx devices The devices provide up to 64 KB of on-chip flash memory. The flash memory consists of up to 64 KB main flash organized into 64 pages with 1 KB capacity per page and a 3 KB information block for the boot loader.
Page 36: Table 1-3. Boot Modes
GD32F1x0 User Manual F7FF Option Bytes 0x1FFF F800 - 0x1FFF 16 bytes F80F Read accesses to the preceding 32 pages can be performed 32 bits per cycle without any wait state. All of byte, half-word (16 bits) and word (32 bits) read accesses are supported. The flash memory can be programmed half-word (16 bits) or word (32 bits) at a time.
Page 37 GD32F1x0 User Manual 1.5. System configuration registers (SYSCFG) 1.5.1. System configuration register 1 (SYSCFG_R1) Address offset: 0x00 Reset value: 0x0000 000X (X indicates BOOT_MODE[1:0] may be any value according to the BOOT0 pin and the OB_BOOT1_n option bit after reset) This register has to be accessed by word(32-bit) Reserved PB9_HCCE...
Page 38: Boot_Mode
GD32F1x0 User Manual 0: Not remap (USART1_TX DMA requests are mapped on DMA channel 2) 1: Remap (USART1_TX DMA requests are mapped on DMA channel 4) ADC_DMA_RMP ADC DMA request remapping enable 0: Not remap (ADC DMA requests are mapped on DMA channel 1) 1: Remap (ADC DMA requests are mapped on DMA channel 2) Reserved Must be kept at reset value...
Page 39 GD32F1x0 User Manual Reserved EXTI3_SS [3:0] EXTI2_SS [3:0] EXTI1_SS [3:0] EXTI0_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 EXTI3_SS[3:0] EXTI 3 sources selection X000: PA3 pin X001: PB3 pin X010: PC3 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved...
Page 40 GD32F1x0 User Manual X101: PF0 pin X110: Reserved X111: Reserved 1.5.4. EXTI sources selection register 2 (SYSCFG_EXTISS2) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved EXTI7_SS [3:0] EXTI6_SS [3:0] EXTI5_SS [3:0] EXTI4_SS [3:0] Bits Fields Descriptions...
Page 41 GD32F1x0 User Manual X100: Reserved X101: PF5 pin X110: Reserved X111: Reserved EXTI4_SS[3:0] EXTI 4 sources selection X000: PA4 pin X001: PB4 pin X010: PC4 pin X011: Reserved X100: Reserved X101: PF4 pin X110: Reserved X111: Reserved 1.5.5. EXTI sources selection register 3 (SYSCFG_EXTISS3) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
Page 42 GD32F1x0 User Manual...
Page 43: System Configuration Register 2 (Syscfg_R2)
GD32F1x0 User Manual X010: PC15 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved X111: Reserved 11:8 EXTI14_SS[3:0] EXTI 14 sources selection X000: PA14 pin X001: PB14 pin X010: PC14 pin X011: Reserved X100: Reserved X101: Reserved X110: Reserved X111: Reserved EXTI13_SS[3:0] EXTI 13 sources selection X000: PA13 pin...
Page 44 GD32F1x0 User Manual SRAM_ LOCK LVD_ PARITY_ Reserved SRAM_PCEF Reserved LOCK ERROR_ LOCK LOCK Bits Fields Descriptions 31:9 Reserved Must be kept at reset value SRAM_PCEF SRAM parity check error flag This bit is set by hardware when an SRAM parity check error occurs. It is cleared by software by writing 1.
Page 45 GD32F1x0 User Manual...
Page 46 UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID GD32F1x0 User Manual...
Page 47 A power switch is implemented for the Backup domain. It can be powered from the V voltage when the main V supply is shut down. 2.2. Main features  Three power domains: V and 1.2V power domains for GD32F130xx and GD32F150xx devices or 1.8V power domains for GD32F170xx and GD32F190xx devices ...
Page 48: Figure 2-1. Power Supply Overview Of Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual Figure 2-1. Power supply overview of GD32F130xx and GD32F150xx devices Backup Domain Power Switch 3.3V BPOR WKUP1 WKUP5 BREG WKUP2 PC13 CTRL WKUP3 NRST APB INTF2 APB INTF1 WKUP4 SLEEPING IWDG Cortex-M3 SLEEPDEEP POR/PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain...
Page 49: Figure 2-2. Power Supply Overview Of Gd32F170Xx And Gd32F190Xx Devices
GD32F1x0 User Manual Figure 2-2. Power supply overview of GD32F170xx and GD32F190xx devices Backup Domain Power Switch BPOR WKUP1 WKUP5 BREG WKUP2 PC13 CTRL WKUP3 NRST APB INTF2 APB INTF1 WKUP4 SLEEPING IWDG Cortex-M3 SLEEPDEEP POR/PDR AHB IPs APB IPs 1.8V Domain 1.8V Domain...
Page 50 GD32F1x0 User Manual the WFI/WFE instruction, the Cortex™-M3 needs to setup the RTC register with an expected wakeup time and enable the wakeup function to achieve the RTC timer wakeup event. After entering the power saving mode for a certain amount of time, the RTC alarm will be asserted to wake up the device when the time match event occurs.
Page 51: Figure 2-3. Waveform Of The Power Reset
GD32F1x0 User Manual The LVD is used to detect whether the V or V supply voltage is lower than the low voltage detector threshold. The function is configured by the Power Control Register (PWR_CTLR). The LVDE bit controls whether LVD is enabled or not, while the LVDT[2:0] bits select the low voltage detector threshold from 2.2V to 2.9V for GD32F130xx and GD32F150xx devices or 2.4V to 4.5V for GD32F170xx and GD32F190xx devices.
Page 52: Figure 2-4. Waveform Of Lvd Threshold
GD32F1x0 User Manual Figure 2-4. Waveform of LVD threshold 100mV LVD threshold hyst LVD output 2.3.3. 1.2V power domain for GD32F130xx and GD32F150xx devices The main functions that include Cortex™-M3 logic, AHB/APB peripherals, the APB interfaces for the Backup domain and the V domain, etc., are located in the 1.2V power domain.
Page 53 GD32F1x0 User Manual wake up the system. The mode offers the lowest wakeup time as no time is wasted in interrupt entry or exit. According to the SLEEPONEXIT bit in the Cortex™-M3 System Control Register, there are two options to select the Sleep mode entry mechanism. ...
Page 54: Table 2-1. Power Saving Mode Summary
GD32F1x0 User Manual Table 2-1. Power saving mode summary Mode Sleep Deep-sleep Standby All clocks in the 1.2V 1.2V domain for domain for GD32F130/150xx GD32F130/150xx devices or 1.8V devices or 1.8V domain for domain for GD32F170/190xx Only CPU clock is GD32F170/190xx devices is power off Description...
Page 55 GD32F1x0 User Manual Bits Fields Descriptions 31:9 Reserved Must be kept at reset value BKPWE Backup Domain Write Enable 0: Disable write access to the registers in Backup domain 1: Enable write access to the registers in Backup domain After reset, any write access to the registers in Backup domain is ignored. This bit has to be set to enable write access to these registers.
Page 56 GD32F1x0 User Manual For GD32F170xx and GD32F190xx devices Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit). Reserved Reserved BKPWE LVDT[2:0] LVDE SBFR WUFR SDBM LDOLP rc_w1 rc_w1 Bits Fields...
Page 57 GD32F1x0 User Manual This bit is always read as 0. SDBM Standby Mode 0: Enter the Deep-sleep mode when the Cortex™-M3 enters SLEEPDEEP mode 1: Enter the Standby mode when the Cortex™-M3 enters SLEEPDEEP mode LDOLP LDO Low Power Mode 0: the LDO operates normally during the Deep-sleep mode 1: the LDO is in low power mode during the Deep-sleep mode Note: Some peripherals may work with the HSI clock in the Deep-sleep mode.
Page 58 GD32F1x0 User Manual 0: Low Voltage event has not occurred (V is higher than the specified LVD threshold) 1: Low Voltage event occurred (V is equal to or lower than the specified LVD threshold) Note: The LVD function is stopped in Standby mode. Standby Flag 0: The device has not been in Standby mode 1: The device has been in Standby mode...
Page 59 GD32F1x0 User Manual Flash Memory Controller (FMC) 3.1. Introduction The Flash Memory Controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time within 32K bytes while CPU executes instruction. It also provides page erase, mass erase, and word/half word program for flash memory. 3.2.
Page 60: Table 3-1. Base Address And Size For Flash Memory
GD32F1x0 User Manual the base address, size. Table 3-1. Base address and size for flash memory Block Name Address size(bytes) Page 0 0x0800 0000 - 0x0800 03FF Page 1 0x0800 0400 - 0x0800 07FF Page 2 0x0800 0800 - 0x0800 0BFF Main Flash Block...
Page 61 GD32F1x0 User Manual 3.3.3. Unlock the FMC_CMR register After reset, the FMC_CMR register is not accessible in write mode, except for the OPTR bit, which is used for reloading the option byte, and the LK bit in FMC_CMR register is 1. An unlocking sequence consists of two write operations to the FMC_UKEYR register can open the access to the FLASH_CMR register.
Page 62: Figure 3-1. Proccess Of Page Erase Operation
GD32F1x0 User Manual Figure 3-1. Proccess of page erase operation Start Is the LK bit 0 Unlock the FMC_CMR Is the BUSY bit 0 Set the FMC_AR, PE Send the command to FMC by setting START bit Is the BUSY bit 0 Finish 3.3.5.
Page 63: Figure 3-2. Process Of The Mass Erase Operation
GD32F1x0 User Manual all flash data will be reset to a value of 0xFFFF_FFFF, the mass erase operation can be implemented using a program that runs in SRAM or by using the debugging tool to access the FMC registers directly. The end of this operation is indicated by the ENDF bit in the FMC_CSR register.
Page 64: Figure 3-3. Process Of The Word Programming Operation
GD32F1x0 User Manual  A 32-bit word/16-bit half word write at desired address by DBUS.  Wait until all the operations have been completed by checking the value of the BUSY bit in FMC_CSR register.  Read and verify the Flash memory if required using a DBUS access. When the operation is executed successfully, an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CMR register is set, and the ENDF in FMC_CSR register is set.
Page 65 GD32F1x0 User Manual  Unlock the FMC_CMR register if necessary.  Unlock the OBWE bit in FMC_CMR register if necessary.  Check the BUSY bit in FMC_CSR register to confirm that no Flash memory operation is in progress (BUSY equal to 0). Otherwise, wait until the operation has been finished. ...
Page 66 GD32F1x0 User Manual...
Page 67: Table 3-4. Ob_Wp Bit For Pages Protected
GD32F1x0 User Manual on the Flash memory. The page erase or program will not be accepted by the FMC on protected pages. If the page erase or program command is sent to the FMC on a protected page, the WPEF bit in the FMC_CSR register will then be set by the FMC. If the WPEF bit is set and the ERIE bit is also set to 1 to enable the corresponding interrupt, then the Flash operation error interrupt will be triggered by the FMC to get the attention of the CPU.
Page 68: Address Offset: 0X04 Reset Value: 0X0000
GD32F1x0 User Manual SRAM or boot from boot loader mode is disabled. All operations are from user code. The main flash block is accessible by all operations. The option byte cannot be erased, and the OB_RDPT byte and its complement value cannot be reprogrammed. So, if protection level high is programmed, it cannot move back to protection level low or no protection level.
Page 69 GD32F1x0 User Manual...
Page 70: Reserved
GD32F1x0 User Manual When the operation executed successfully, this bit is set by hardware. The software can clear it by writing 1. WPEF Erase/Program protection error flag bit When erasing/programming on protected pages, this bit is set by hardware. The software can clear it by writing 1. Reserved Must be kept at reset value PGEF...
Page 71 GD32F1x0 User Manual ERIE Error interrupt enable bit This bit is set or cleared by software. 0: No interrupt generated by hardware 1: Error interrupt enable...
Page 72 GD32F1x0 User Manual Reset value: 0x0000 0080 This register has to be accessed by word(32-bit) AR[31:16] AR[15:0] Bits Fields Descriptions 31:0 AR[31:0] Flash command address bits These bits are set by software. AR bits are the address of flash erase command 3.4.7.
Page 73 GD32F1x0 User Manual Reset value: 0x0000 XXXX This register has to be accessed by word(32-bit) Reserved OB_WP[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 OB_WP[15:0] Store OB_WP[15:0] of option byte block after system reset 0: Protection active 1: Unprotected 3.4.9.
Page 74 GD32F1x0 User Manual For GD32F170xx and GD32F190xx devices Address offset: 0xFC Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Resrved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value BPEN FMC bit program enable register This bit set and reset by software.
Page 75 GD32F1x0 User Manual These bits are read only by software. These bits are unchanged constantly after power on. These bits are one time programmed when the chip product. 3.4.11. Flash Product reserved ID code register2 (FMC_RES_ID2) Address offset: 0x104 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) RES_ID2[31:16] 332828...
Page 76 GD32F1x0 User Manual Reset and clock control unit (RCC) 4.1. Reset Control Unit (RCU) 4.1.1. Introduction GD32F1x0 Reset Control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power on reset, known as a cold reset, resets the full system except the Backup domain during a power up.
Page 77: Figure 4-1. The System Reset Circuit
GD32F1x0 User Manual Figure 4-1. The system reset circuit Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the Backup domain control register or Backup domain power on reset (V or V power on, if both supplies have previously been powered off).
Page 78: Figure 4-2. Clock Tree Of Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual Figure 4-2. Clock tree of GD32F130xx and GD32F150xx devices CK_LSE CK_CEC ÷ 24 (to CEC) CECSEL CK_USB Prescaler (to USB) ÷ 1,1.5,2 CK_I2S (to I2S) CK_FMC SCS[1:0 FMC enable (to FMC) (by hardware) HCLK CK_HSI AHB enable (to AHB bus,Cortex-M3,SRAM,DMA) 8 MHz CK_CST...
Page 79: Figure 4-3. Clock Tree Of Gd32F170Xx And Gd32F190Xx Devices
GD32F1x0 User Manual Figure 4-3. Clock tree of GD32F170xx and GD32F190xx devices CK_LSE CK_CEC ÷ 24 (to CEC) CECSEL CK_I2S (to I2S) CK_FMC SCS[1:0 FMC enable (to FMC) (by hardware) HCLK CK_HSI AHB enable (to AHB bus,Cortex-M3,SRAM,DMA) 8 MHz CK_CST CK_PLL CK_SYS CK_AHB...
Page 80 GD32F1x0 User Manual or LSI clock or HSE clock divided by 32 which select by RTCSRC bit in Backup Domain Control Register (RCC_BDCR). The IWDG is clocked by LSI clock, which is forced on when IWDG started. If the APB prescaler is 1, the timer clock frequencies are set to AHB frequency divide by 1. Otherwise, they are set to the AHB frequency divide by half of APB prescaler.
Page 81 GD32F1x0 User Manual Select external clock bypass mode by setting the HSEBPS and HSEEN bits in the Global Clock Control Register RCC_GCCR. The CK_HSE is equal to the external clock which drives the OSCIN pin. High Speed Internal 8 M RC Oscillators (HSI) The high speed internal 8M RC oscillator, HSI8, has a fixed frequency of 8 MHz and is the default clock source selection for the CPU when the device is powered up.
Page 82 GD32F1x0 User Manual The high speed internal 28MRC oscillator, HSI28, has a fixed frequency of 28 MHz and dedicated as ADC clock. The HSI28 RC oscillator can be switched on or off using the HSI28EN bit in the Global Clock control register 2 (RCC_GCCR2). The HSI28RSTB flag in the Global Clock Control Register 2 (RCC_GCCR2) is used to indicate if the internal 28M RC oscillator is stable.
Page 83: Table 4-1. Clock Source Select
GD32F1x0 User Manual failure interrupt is connected to the Non-Maskable Interrupt, NMI, of the Cortex-M3. If the HSE is selected as the clock source of CK_SYS or PLL, the HSE failure will force the CK_SYS source to HSI and the PLL will be disabled automatically Clock Output Capability For GD32F130xx and GD32F150xx devices The clock output capability is ranging from 32 kHz to 54 MHz.
Page 84: Table 4-3. Core Domain Voltage Selected In Deep-Sleep Mode
GD32F1x0 User Manual CKOUTDIV[2:0] bits , in the Global Clock Configuration Register (RCC_GCFGR). The CK_OUT2 is seleced by CKOUT2SRC, in the Global Clock Configuration Register4 (RCC_GCFGR4). The CK_OUT2 frequency can be reduced by a configurable binary divider, controlled by the CKOUT2DIV[2:0] bits , in the Global Clock Configuration Register4 (RCC_GCFGR4).
Page 85 Reserved PLLSTB Reserved CKMEN HSEBPS HSESTB HSEEN HSICALIB[7:0] HSIADJ[4:0] Reserved. HSISTB HSIEN Bits Fields Descriptions 31:26 Reserved Must be kept at reset value. PLLSTB PLL Clock Stabilization Flag Set by hardware to indicate if the PLL output clock is stable and ready for use. 0: PLL is not stable 1: PLL is stable PLLEN...
Page 86 GD32F1x0 User Manual power on reset or clearing CKMF by software. Note: When the HSE clock monitor is enabled, the hardware will automatically enable the HSI internal RC oscillator regardless of the control bit, HSIEN, state. HSEBPS External crystal oscillator (HSE) clock bypass mode enable The HSEBPS bit can be written only if the HSEEN is 0.
Page 87 GD32F1x0 User Manual 4.3.2. Global Clock configuration register (RCC_GCFGR) For GD32F130xx and GD32F150xx devices Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) PLLDV CKOUTDIV[2:0] PLLMF[4] CKOUTSRC[2:0] USBPS[1:0] PLLMF[3:0] PLLPREDV PLLSEL ADCPS[1:0] APB2PS[2:0] APB1PS[2:0] AHBPS[3:0]...
Page 88 GD32F1x0 User Manual 23:22 USBPS[1:0] USB clock prescaler selection Set and reset by software to control the USB clock prescaler value. The USB clock must be 48MHz. These bits can’t be reset if the USB clock is enabled. 00: (CK_PLL / 1.5) selected 01: CK_PLL selected 10: (CK_PLL / 2.5) selected 11: (CK_PLL / 2) selected...
Page 89 GD32F1x0 User Manual PLLPREDV HSE divider for PLL source clock selection. This bit is the same bit as bit HSEPREDV[0] from RCC_GCFGR2. Refer to RCC_CGFGR2 HSEPREDV bits description. Set and cleared by software to divide HSE or not which is selected to PLL. 0: HSE clock selected 1: (CK_HSE / 2) clock selected PLLSEL...
Page 90 GD32F1x0 User Manual 1111: (CK_SYS / 512) selected SCSS[1:0] System clock switch status Set and reset by hardware to indicate the clock source of system clock. 00: select CK_HSI as the CK_SYS source 01: select CK_HSE as the CK_SYS source 10: select CK_PLL as the CK_SYS source 11: reserved SCS[1:0]...
Page 91 GD32F1x0 User Manual 30:28 CKOUTDIV[2:0] The CK_OUT divider which the CK_OUT frequency can be reduced see bits 26:24 of GCFGR for CK_OUT 000: The CK_OUT is divided by 1 001: The CK_OUT is divided by 2 010: The CK_OUT is divided by 4 011: The CK_OUT is divided by 8 100: The CK_OUT is divided by 16 101: The CK_OUT is divided by 32...
Page 92 11111: (PLL source clock x 32) Note: The PLL output frequency must not exceed 72 MHz. PLLPREDV HSE divider for PLL source clock selection. This bit is the same bit as bit HSEPREDV[0] from RCC_GCFGR2. Refer to RCC_CGFGR2 HSEPREDV bits description.
Page 93 GD32F1x0 User Manual Set and reset by software to control the APB1 clock division ratio. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected AHBPS[3:0] AHB prescaler selection Set and reset by software to control the AHB clock division ratio 0xxx: CK_SYS selected 1000: (CK_SYS / 2) selected...
Page 94 GD32F1x0 User Manual HSI14 Reserved CKMR Reserved STBR STBR STBR STBR STBR STBR HSI14 HSI14 Reserved CKMF Reserved STBIE STBIE STBIE STBIE STBIE STBIE STBF STBF STBF STBF STBF STBF Bits Fields Descriptions 31:24 Reserved Must be kept at reset value CKMR HSE Clock Stuck Interrupt Reset Write 1 by software to reset the CKMF flag.
Page 95 GD32F1x0 User Manual 1: Reset LSIRDYF flag 15:14 Reserved Must be kept at reset value HSI14STBIE HSI14 Stabilization Interrupt Enable Set and reset by software to enable/disable the HSI14 stabilization interrupt. 0: Disable the HSI14 stabilization interrupt 1: Enable the HSI14 stabilization interrupt PLLSTBIE PLL Stabilization Interrupt Enable Set and reset by software to enable/disable the PLL stabilization interrupt.
Page 96 GD32F1x0 User Manual Set by hardware when the PLL is stable and the PLLSTBIE bit is set. Reset by software when setting the PLLSTBR bit. 0: No PLL stabilization interrupt generated 1: PLL stabilization interrupt generated HSESTBF HSE stabilization interrupt flag Set by hardware when the External 4 ~ 16 MHz crystal oscillator clock is stable and the HSESTBIE bit is set.
Page 97 GD32F1x0 User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value CKMR HSE Clock Stuck Interrupt Reset Write 1 by software to reset the CKMF flag. 0: Not reset CKMF flag 1: Reset CKMF flag Reserved Must be kept at reset value HSI28STBR HSI28 stabilization Interrupt Reset Write 1 by software to reset the HSI28STBF flag.
Page 98 GD32F1x0 User Manual PLLSTBIE PLL Stabilization Interrupt Enable Set and reset by software to enable/disable the PLL stabilization interrupt. 0: Disable the PLL stabilization interrupt 1: Enable the PLL stabilization interrupt HSESTBIE HSE Stabilization Interrupt Enable Set and reset by software to enable/disable the HSE stabilization interrupt 0: Disable the HSE stabilization interrupt 1: Enable the HSE stabilization interrupt HSISTBIE...
Page 99 GD32F1x0 User Manual Reset by software when setting the HSESTBR bit. 0: No HSE stabilization interrupt generated 1: HSE stabilization interrupt generated HSISTBF HSI stabilization interrupt flag Set by hardware when the Internal 8 MHz RC oscillator clock is stable and the HSISTBIE bit is set.
Page 100 GD32F1x0 User Manual 0: No reset 1: Reset the TIMER 17 TIMER16RST Timer 16 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER 16 TIMER15RST Timer 15 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER 15 USART1RST...
Page 101 GD32F1x0 User Manual 4.3.5. APB1 Reset Control Register (RCC_APB1RCR) For GD32F130xx and GD32F150xx devices Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) I2C2 I2C1 USART Reserved Reserved Reserved Res. 2RST SPI3 SPI2 WWDG TIMER14...
Page 102 GD32F1x0 User Manual 1: Reset I2C2 I2C1RST I2C1 reset This bit is set and reset by software. 0: No reset 1: Reset I2C1 20:18 Reserved Must be kept at reset value USART2RST USART2 reset This bit is set and reset by software. 0: No reset 1: Reset USART2 Reserved...
Page 103 GD32F1x0 User Manual 0: No reset 1: Reset TIMER3 timer TIMER2RST TIMER2 timer reset This bit is set and reset by software. 0: No reset 1: Reset TIMER2 timer For GD32F170xx and GD32F190xx devices Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) OPAMPIVREF CAN2...
Page 104 GD32F1x0 User Manual CAN2RST CAN2 reset This bit is set and reset by software. 0: No reset 1: Reset CAN2 CAN1RST CAN1 reset This bit is set and reset by software. 0: No reset 1: Reset CAN1 24:23 Reserved Must be kept at reset value I2C2RST I2C2 reset This bit is set and reset by software.
Page 105 GD32F1x0 User Manual LCDRST LCD reset This bit is set and reset by software. 0: No reset 1: Reset LCD Timer TIMER14RST TIMER14 timer reset This bit is set and reset by software. 0: No reset 1: Reset TIMER14 Timer Reserved Must be kept at reset value TIMER6RST...
Page 106 GD32F1x0 User Manual This bit is set and reset by software. 0: Disabled TSI clock 1: Enabled TSI clock Reserved Must be kept at reset value PFEN GPIO port F clock enable This bit is set and reset by software. 0: Disabled GPIO port F clock 1: Enabled GPIO port F clock Reserved...
Page 107 GD32F1x0 User Manual SRAMEN SRAM interface clock enable This bit is set and reset by software to enable/disable SRAM interface clock during Sleep mode. 0: Disabled SRAM interface clock during Sleep mode. 1: Enabled SRAM interface clock during Sleep mode Reserved...
Page 108 GD32F1x0 User Manual This bit is set and reset by software. 0: Disabled USART1 clock 1: Enabled USART1 clock Reserved Must be kept at reset value SPI1EN SPI1 clock enable This bit is set and reset by software. 0: Disabled SPI1 clock 1: Enabled SPI1 clock TIMER1EN TIMER1 timer clock enable...
Page 109 GD32F1x0 User Manual Reserved Must be kept at reset value CECEN Hdmi cec interface clock enable This bit is set and reset by software. 0: Disabled Hdmi cec interface clock 1: Enabled Hdmi cec interface clock DACEN DAC interface clock enable This bit is set and reset by software.
Page 110 GD32F1x0 User Manual 0: Disabled SPI2 clock 1: Enabled SPI2 clock 13:12 Reserved Must be kept at reset value WWDGEN Window watchdog clock enable This bit is set and reset by software. 0: Disabled Window watchdog clock 1: Enabled Window watchdog clock 10:9 Reserved Must be kept at reset value...
Page 111 PWREN Power interface clock enable This bit is set and reset by software. 0: Disabled Power interface clock 1: Enabled Power interface clock Reserved Must be kept at reset value CAN2EN CAN2 clock enable This bit is set and reset by software. 0: Disabled CAN2 clock 1: Enabled CAN2 clock CAN1EN...
Page 112 GD32F1x0 User Manual This bit is set and reset by software. 0: Disabled USART2 clock 1: Enabled USART2 clock Reserved Must be kept at reset value SPI3EN SPI3 clock enable This bit is set and reset by software. 0: Disabled SPI3 clock 1: Enabled SPI3 clock SPI2EN SPI2 clock enable...
Page 113 GD32F1x0 User Manual This bit is set and reset by software. 0: Disabled TIMER2 timer clock 1: Enabled TIMER2 timer clock 4.3.9. Backup Domain Control Register (RCC_BDCR) For GD32F130xx and GD32F150xx devices Address offset: 0x20 Reset value: 0x0000 0018, reset by Backup domain Reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Note: The LSEEN, LSEBPS, RTCSRC and RTCEN bits of the Backup domain control register (BDCR) are only reset after a Backup domain Reset.
Page 114 GD32F1x0 User Manual Reserved Must be kept at reset value LSEDRI[1:0] LSE drive capability Set and reset by software. Backup domain reset reset this value. 00: lower driving capability 01: medium low driving capability 10: medium high driving capability 11: higher driving capability (reset value) Note: The LSEDRI is not in bypass mode.
Page 115 GD32F1x0 User Manual This bit is set and reset by software. 0: No reset 1: Resets Backup domain RTCEN RTC clock enable This bit is set and reset by software. 0: Disabled RTC clock 1: Enabled RTC clock 14:10 Reserved Must be kept at reset value RTCSRC[1:0] RTC and LCD clock entry selection...
Page 116 GD32F1x0 User Manual 4.3.10. Global Control/Status Register (RCC_GCSR) Address offset: 0x24 Reset value: 0x0C00 0000, reset flags reset by power Reset only, other reset by system reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) WWDG IWDG RSTFC Reserved RSTF RSTF...
Page 117 GD32F1x0 User Manual 1: Power reset generated EPRSTF External PIN reset flag Set by hardware when an External PIN generated. Reset by writing 1 to the RSTFC bit. 0: No External PIN reset generated 1: External PIN reset generated OBLRSTF Option byte loader reset flag Set by hardware when an option byte loader generated.
Page 118 GD32F1x0 User Manual Reserved. Bits Fields Descriptions 31:25 Reserved Must be kept at reset value TSIRST TSI unit reset This bit is set and reset by software. 0: No reset TSI unit 1: Reset TSI unit Reserved Must be kept at reset value PFRST GPIO port F reset This bit is set and reset by software.
Page 119 GD32F1x0 User Manual Reserved Reserved HSEPREDV[3:0] Bits Fields Descriptions 31:4 Reserved Must be kept at reset value HSEPREDV[3:0] CK_HSE divider previous PLL This bit is set and reset by software. These bits can be written when PLL is disable Note: The bit 0 of HSEPREDV is same as bit 17 of RCC_GCFGR, so modifying bit 17 of RCC_GCFGR aslo modifies bit 0 of RCC_GCFGR2.
Page 120 GD32F1x0 User Manual Reserved ADCSEL Reserved CECSEL Reserved USART1SEL[1:0] Bits Fields Descriptions 31:9 Reserved Must be kept at reset value ADCSEL CK_ADC clock source selection This bit is set and reset by software. 0: CK_ADC select CK_HSI14 1: CK_ADC select CK_APB2 which is divided by 2/4/6/8. Reserved Must be kept at reset value CECSEL...
Page 121 GD32F1x0 User Manual 1: HSI28 select to ADC clock. 15:9 Reserved Must be kept at reset value ADCSEL CK_ADC clock source selection This bit is set and reset by software. 0: CK_ADC select CK_HSI28 or CK_HSI28/2 set by HSI28DIV 1: CK_ADC select CK_APB2 which is divided by 2/4/6/8. Reserved Must be kept at reset value CECSEL...
Page 122 GD32F1x0 User Manual These bits are set by software. The trimming value is there bits (HSI14ADJ) added to the HSI14CALIB[7:0] bits. The trimming value should trim the HSI14 to 14 MHz ± 1%. Reserved Must be kept at reset value HSI14STB HSI14 High Speed Internal Oscillator stabilization Flag Set by hardware to indicate if the HSI14 oscillator is stable and ready for use.
Page 123 GD32F1x0 User Manual Set and reset by software. 0: Internal 28MHz RC oscillator disabled 1: Internal 28 MHz RC oscillator enabled 4.3.15. Global Clock configuration register4 (RCC_GCFGR4) of GD32F170xx and GD32F190xx devices Address offset: 0x80 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved Reserved CKOUT2DIV[5:0]...
Page 124 GD32F1x0 User Manual 4.3.16. Additional Clock control register (RCC_ACCR) Address offset: 0xF8 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved Reserved I2C3EN Bits Fields Descriptions 31:1 Reserved Must be kept at reset value I2C3EN I2C3 unit clock enable This bit is set and reset by software...
Page 125 GD32F1x0 User Manual 4.3.18. Voltage Key register (RCC_VC_KEY) Address offset: 0x100 Reset value: 0x0000 0000. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0 KEY[31:0] RCC_PDR_VC and RCC_DEEPSLEEP_VC key register These bits are written only by software and read as 0. Only after write 0x1A2B3C4D to the RCC_VC_KEY, the RCC_PDR_VC and RCC_DEEPSLEEP_VC register can be written.
Page 126 GD32F1x0 User Manual 100~111 : Reserved For GD32F170xx and GD32F190xx devices Address offset: 0x134 Reset value: 0x0000 0000. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved Reserved DEEPSLEEP_VC[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value DEEPSLEEP_VC[2:0] Deep-sleep mode voltage register These bits is set and reset by software...
Page 127 GD32F1x0 User Manual PDR_S Power down voltage select register This bit is set and reset by software 0: The Power down voltage is 2.6V 1: The Power down voltage is 1.8V...
Page 128 GD32F1x0 User Manual General-purpose and alternate-function I/Os (GPIO and AFIOs) 5.1. Introduction There are up to 55 general purpose I/O pins, (GPIO), named PA0 ~ PA15 and PB0 ~ PB15, PC0 ~ PC15, PD2, PF0/PF1, PF4 ~ PF7 for the device to implement logic input/output functions.
Page 129: Figure 5-1. Basic Structure Of A Standard I/O Port Bit
GD32F1x0 User Manual (GPIOx_OMODE). And the port max speed can be configured by GPIO output speed registers (GPIOx_OSPD). Each port can be configured as floating (no pull-up and pull-down) , pull-up or pull-down function by GPIO pupd registers (GPIOx_PUPD). Table 5-1. GPIO configuration table PAD TYPE CTLRn OMODEn...
Page 130 GD32F1x0 User Manual 5.3.1. GPIO pin configuration During or just after the reset period, the alternative functions are all inactive and the GPIO ports are configured into the input floating mode that input disabled without Pull-Up(PU)/Pull- Down(PD) resistors. But the Serial-Wired Debug pins are in input PU/PD mode after reset: PA14: SWCLK in input pull-down mode PA13: SWDIO in input pull-up mode The GPIO pins can be configured as inputs or outputs.
Page 131: Figure 5-2. Input Floating/Pull Up/Pull Down Configurations
GD32F1x0 User Manual  The weak pull-up and pull-down resistors could be chosen  Every AHB2 clock cycle the data present on the I/O pad is got to the Data Input Register  The Output Buffer is disabled The figure below shows the Configuration of the I/O Port bit. Figure 5-2.
Page 132: Figure 5-3. Output Configuration
GD32F1x0 User Manual Figure 5-3. Output configuration Bit Set/Clear Write Output Registers Output Data Control Registe Read/Write Output driver I/O pin Input Data Read Regist Schmitt trigger Input driver 5.3.6. Analog configuration When GPIO pin is used as analog configuration: ...
Page 133: Figure 5-5. Alternate Function Configuration
GD32F1x0 User Manual  The data present on the I/O pin is sampled into the Data Input Register every AHB2 clock cycle  A read access to the Data Input Register gets the I/O state in open drain mode  A read access to the Data Output register gets the last written value in Push-Pull mode The figure below shows the Alternate Function Configuration of the I/O Port bit.
Page 134 GD32F1x0 User Manual Bits Fields Descriptions 31:30 CTLR15[1:0] Pin 15 configuration bits These bits are set and cleared by software. Refer to CTLR0[1:0]description 29:28 CTLR14[1:0] Pin 14 configuration bits These bits are set and cleared by software. Refer to CTLR0[1:0]description 27:26 CTLR13[1:0] Pin 13 configuration bits...
Page 135 GD32F1x0 User Manual CTLR3[1:0] Pin 3 configuration bits These bits are set and cleared by software. Refer to CTLR0[1:0]description CTLR2[1:0] Pin 2 configuration bits These bits are set and cleared by software. Refer to CTLR0[1:0]description CTLR1[1:0] Pin 1 configuration bits These bits are set and cleared by software.
Page 136 GD32F1x0 User Manual Refer to OM0 description OM12 Pin 12 output mode bit These bits are set and cleared by software. Refer to OM0 description OM11 Pin 11 output mode bit These bits are set and cleared by software. Refer to OM0 description OM10 Pin 10 output mode bit These bits are set and cleared by software.
Page 137 GD32F1x0 User Manual Pin 0 output mode bit These bits are set and cleared by software. 0: Output push-pull mode (reset) 1: Output open-drain mode 5.4.3. GPIO port output speed register (GPIOx_OSPD) (x=A..D,F) Address offset: 0x08 Reset value: 0x0C00 0000 for port A; 0x0000 0000 for others. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) OSPD15[1:0] OSPD14[1:0]...
Page 138 GD32F1x0 User Manual 17:16 OSPD8[1:0] Pin 8 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 15:14 OSPD7[1:0] Pin 7 output max speed bits These bits are set and cleared by software. Refer to OSPD0[1:0] description 13:12 OSPD6[1:0] Pin 6 output max speed bits...
Page 139 GD32F1x0 User Manual PUPD7[1:0] PUPD6[1:0] PUPD5[1:0] PUPD4[1:0] PUPD3[1:0] PUPD2[1:0] PUPD1[1:0] PUPD0[1:0] Bits Fields Descriptions 31:30 PUPD15[1:0] Pin 15 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUPD0[1:0]description 29:28 PUPD14[1:0] Pin 14 pull-up or pull-down bits These bits are set and cleared by software.
Page 140 GD32F1x0 User Manual PUPD4[1:0] Pin 4 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUPD0[1:0]description PUPD3[1:0] Pin 3 pull-up or pull-down bits These bits are set and cleared by software. Refer to PUPD0[1:0]description PUPD2[1:0] Pin 2 pull-up or pull-down bits These bits are set and cleared by software.
Page 141 GD32F1x0 User Manual 5.4.6. GPIO port data output register (GPIOx_DOR) (x=A..D,F) Address offset: 0x14 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) Reserved DOR15 DOR14 DOR13 DOR12 DOR11 DOR10 DOR9 DOR8 DOR7 DOR6 DOR5 DOR4 DOR3 DOR2...
Page 142 GD32F1x0 User Manual 5.4.8. GPIO port configuration lock register (GPIOx_LOCKR) (x=A,B) Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved LK15 LK14 LK13 LK12 LK11 LK10 Bits Fields Descriptions 31:17 Reserved Must be kept at reset value Lock key It can only be setted using the Lock Key Writing Sequence.And can always be read.
Page 143 GD32F1x0 User Manual AFSL3[3:0] AFSL2[3:0] AFSL1[3:0] AFSL0[3:0] Bits Fields Descriptions 31:28 AFSL7[3:0] Pin 7 alternate function selected These bits are set and cleared by software. Refer to AFSL0 [3:0]description 27:24 AFSL6[3:0] Pin 6 alternate function selected These bits are set and cleared by software. Refer to AFSL0 [3:0]description 23:20 AFSL5[3:0]...
Page 144 GD32F1x0 User Manual 5.4.10. GPIO port alternate function selected high register (GPIOx_AFSH) (x=A,B,C) Address offset: 0x24 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) AFSH15[3:0] AFSH14[3:0] AFSH13[3:0] AFSH12[3:0] AFSH11[3:0] AFSH10[3:0] AFSH9[3:0] AFSH8[3:0] Bits Fields Descriptions 31:28 AFSH15[3:0]...
Page 145 GD32F1x0 User Manual 0001: AF1 selected 0010: AF2 selected 0011: AF3 selected 0100: AF4 selected (Port A,B only) 0101: AF5 selected (Port A,B only) 0110: AF6 selected (Port A,B only) 0111: AF7 selected (Port A,B only) 1000 ~ 1111: Reserved 5.4.11.
Page 146 GD32F1x0 User Manual TG15 TG14 TG13 TG12 TG11 TG10 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 TGx[15:0] Port Toggle bit These bits are set and cleared by software. 0: No action on the corresponding DORx bit 1: Toggle the corresponding DORx bit...
Page 147 GD32F1x0 User Manual CRC Calculation Unit 6.1. Introduction A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC calculation unit can be used to calculate 32/16/8 bit CRC code within fixed polynomial.
Page 148: Figure 6-1.Block Diagram Of Crc Calculation Unit
GD32F1x0 User Manual Figure 6-1.Block Diagram of CRC Calculation Unit Data Input Reversible Option Input Data Register Reversible Option CRC Calculation Unit Fixed polynomial 0x4C11DB7 Interface Data Output Reversible Option Output Data Register (32 bit) Reversible Option Data Access Free Purpose 8 bit Register 6.3.
Page 149 GD32F1x0 User Manual 32-bit data is divided in to 2 groups and reverse implement in group inside. Reversed data: 0xD458B23C. 3) word reverse: 32-bit data is divided in to 1 group and reverse implement in group inside. Reversed data: 0xB23CD458 For output data, reverse type is word reverse.
Page 150 GD32F1x0 User Manual This register has to be accessed by word(32-bit) Reserved Reserved FDR[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value FDR[7:0] Free Data Register Bits Software write and read. These bits are unrelated with CRC calculation. This byte can be used for any goals by any other peripheral.
Page 151 GD32F1x0 User Manual cleared itself to 0.This bit will generate no effect to CRC_FDTR. Software write and read. 6.4.4. CRC Initialization Data Register (CRC_IDTR) Address offset: 0x10 Reset value: 0xFFFF FFFF This register has to be accessed by word(32-bit) IDAR [31:16] IDAR [15:0] Bits Fields...
Page 152 GD32F1x0 User Manual Interrupts and events 7.1. Introduction Cortex-M3 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processor core. You can read the Technical Reference Manual of Cortex-M3 for more details about NVIC.
Page 153: Table 7-1. Nvic Exception Types In Cotrex-M3
GD32F1x0 User Manual Table 7-1. NVIC exception types in Cotrex-M3 Exception Vector Priority (a) Vector Address Description Type Number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory BusFault Programmable 0x0000_0014...
Page 154 GD32F1x0 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number IRQ 14 TIMER1 Capture Compare interrupt 0x0000_0078 TIMER2 global interrupt 0x0000_007C IRQ 15 TIMER3 global interrupt 0x0000_0080 IRQ 16 TIMER6 and DAC global interrupt 0x0000_0084 IRQ 17 IRQ 18 Reserved 0x0000_0088 IRQ 19...
Page 155 GD32F1x0 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number IRQ 3 Flash global interrupt 0x0000_004C RCC global interrupt 0x0000_0050 IRQ 4 EXTI Line0-1 interrupt 0x0000_0054 IRQ 5 EXTI Line2-3 interrupt 0x0000_0058 IRQ 6 IRQ 7 EXTI Line4-15 interrupt 0x0000_005C IRQ 8 TSI global interrupt...
Page 156 GD32F1x0 User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number IRQ46 CAN1_SCE 0x0000_00F8 0x0000_00FC IRQ 47 DMA Channel6-7 global interrupt 0x0000_0100 IRQ 48 0x0000_0104- IRQ 49-50 65-66 Reserved 0x0000_0108 IRQ 51 SPI3 global interrupt 0x0000_010C 0x0000_0110- 68-85 Reserved IRQ52-69 0x0000_0154 IRQ70...
Page 157: Figure 7-1. Block Diagram Of Exti
GD32F1x0 User Manual Figure 7-1. Block diagram of EXTI. Polarity Software Control Trigger EXTI Line0~22 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control The EXTI trigger source includes 16 lines from I/O pins and 8 lines for GD32F130xx and GD32F150xx devices (including LVD, RTC, USB, USART, CEC and CMPs, please refer to Table 7-4 for detail) or 7 lines for GD32F170xx and GD32F190xx devices (including LVD,...
Page 158: Table 7-4. Exti Source Of Gd32F130Xx And Gd32F150Xx Devices
GD32F1x0 User Manual Hardware trigger may be used to detect the voltage change of external or internal signals. The software should follow these steps to use this function: Configure EXTI sources in SYSCFG module based on application requirement. Configure EXTI_RTE and EXTI_FTE to enable the rising or falling detection on related pins.
Page 159: Table 7-5. Exti Source Of Gd32F170Xx And Gd32F190Xx Devices
GD32F1x0 User Manual EXTI Line Number Source Attrubute RTC tamper and Timestamp External Reserved Reserved Comparator 1 output External Comparator 2 output External Reserved Reserved Reserved Reserved USART1 Wakeup Internal Reserved Reserved CEC Wakeup Internal Table 7-5. EXTI source of GD32F170xx and GD32F190xx devices EXTI Line Number Source Attrubute...
Page 160 GD32F1x0 User Manual 7.4. Interrupts and EXTI registers 7.4.1. Interrupt Enable register (EXTI_IER) Address offset: 0x00 Reset value: 0x0F90 0000 This register has to be accessed by word(32-bit). Reserved IER27 IER26 IER25 IER24 IER23 IER22 IER21 IER20 IER19 IER18 IER17 IER16 IER15 IER14...
Page 161 GD32F1x0 User Manual 7.4.3. Rising edge trigger enable register (EXTI_RTE) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RTE22 RTE21 Reserved RTE19 RTE18 RTE17 RTE16 RTE15 RTE14 RTE13 RTE12 RTE11 RTE10 RTE9 RTE8 RTE7 RTE6...
Page 162 GD32F1x0 User Manual...
Page 163 GD32F1x0 User Manual Reserved Must be kept at reset value 19: 0 SIEx Interrupt/Event software trigger 0: Deactivate the EXTIx software interrupt/event request 1: Activate the EXTIx software interrupt/event request 7.4.6. Pending register (EXTI_PD) Address offset: 0x14 Reset value: undefined This register has to be accessed by word(32-bit).
Page 164 GD32F1x0 User Manual Direct memory access controller (DMA) 8.1. Introduction The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and memory or between memory and memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 165: Table 8-1. Dma Transfer Operations
GD32F1x0 User Manual controller based on the programmed values in the DMA_PBARx, DMA_MBARx, and DMA_CTLRx registers. For details, see Chapter 8.3.3. The DMA_RCNTx register controls how many transfers to be transmitted on the channel. The PSIZE and MSIZE bits in the DMA_CTLRx register determine how many bytes to be transmitted in a transfer.
Page 166: Table 8-2. Dma Interrupt Event
GD32F1x0 User Manual 8.3.3. Next address generation algorithm PSIZE and MSIZE bits in the DMA_CTLRx register are used for configuring the transfer data size of peripheral and memory. PNAGA and MNAGA bits in the DMA_CTLRx register are used to configure the next address generation algorithm of peripheral and memory. There are two algorithms including the fixed address mode and the increasing address mode.
Page 167: Figure 8-1. Dma Interrupt Generation Logic
GD32F1x0 User Manual Figure 8-1. DMA interrupt generation logic TCIFx TCIEx HTIFx INTERRUPTx HTIEx ERRIFx ERRIEx “x” indicates channel number (x=1…7). Note: The transfer error event occurs when the DMA controller accesses a reserved address space. At the moment, the channel is automatically shut down through hardware clear of the CHEN bit in the DMA_CTLRx register.
Page 168: Figure 8-2. Dma Request Mapping
GD32F1x0 User Manual Figure 8-2. DMA request mapping ADC(1) Hardware TM2_CH3 TM17_CH1(1) priority Channel 1 TM17_UP(1) MEMTOMEM1 ADC(2) SPI1_RX USART1_TX(1) I2C1_TX TM1_CH1 Channel 2 TM2_UP high TM3_CH3 MEMTOMEM2 TM17_CH1(2) TM17_UP(2) SPI1_TX USART1_RX(1) I2C1_RX TM1_CH2 TM2_CH2 TM3_CH4 Channel 3 TM3_UP TM6_UP MEMTOMEM3 DAC1 TM16_CH1(1)
Page 170 GD32F1x0 User Manual 31:28 Reserved Must be kept at reset value Error flag of channel x (x=1…7) 27/23/19/ ERRIFx 15/11/7/3 Hardware set and software cleared by configuring DMA_ICR register. 0: Error has not occurred on channel x 1: Error has occurred on channel x Half transfer complete flag of channel x (x=1…7) 26/22/18/ HTIFx...
Page 171 GD32F1x0 User Manual 13/9/5/1 0: No effect 1: Clear TCIFx bit in the DMA_IFR register Clear global interrupt flag of channel x (x=1…7) 24/20/16/ GICx 12/8/4/0 0: No effect 1: Clear GIFx, ERRIFx, HTIFx and TCIFx bits in the DMA_IFR register 8.4.3.
Page 172 GD32F1x0 User Manual 0: Fixed address mode 1: Increasing address mode PNAGA Next address generation algorithm of peripheral 0: Fixed address mode 1: Increasing address mode CIRC Circulation mode 0: Disable circulation mode. 1: Enable circulation mode Direction of the data transfer on the channel 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral ERRIE...
Page 173 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit) . Note: Do not configure this register when channel is enabled. PBAR[31:16] PBAR[15:0] Bits Fields Descriptions 31:0 PBAR[31:0] Peripheral base address When PSIZE is 01 (16-bit), PBAR[0] is ignored. Access is automatically aligned to a half word address.
Page 174 GD32F1x0 User Manual MBAR[31:16] MBAR[15:0] Bits Fields Descriptions 31:0 MBAR[31:0] Memory base address When MSIZE is 01 (16-bit), MBAR[0] is ignored. Access is automatically aligned to a half word address. When MSIZE is 10 (32-bit), MBAR[1:0] is ignored. Access is automatically aligned to a word address.
Page 175 GD32F1x0 User Manual Timer (TIMERx) Timers (TIMERx) are devided into six sorts. TIMER16/1 TIMER TIMER1 TIMER2/3 TIMER6 TIMER14 TIMER15 TYPE Advanced General(1) Basic General(2) General(3) General(4) Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit 16-bit UP,DOWN, UP,DOWN, Counte mode Center- Center- UP ONLY UP ONLY UP ONLY ONLY...
Page 176 GD32F1x0 User Manual 9.1. Advanced timer (TIMER1) 9.1.1. Introduction The Advanced Timer, known as TIMER1, may be used for a variety of purposes of advanced control. It consists of one 16-bit up/down-counter; four 16-bit capture/compare registers (TIMER1_CHCC), one 16-bit counter auto reload register (TIMER1_CARL) and several control registers.
Page 177: Figure 9-1. Advanced Timer Block Diagram
GD32F1x0 User Manual Figure 9-1. Advanced timer block diagram Polarity Selection Edge Detector Input Filter Trigger Controller TRG_OUTPUT Prescaler ITR0 ITR1 Reset, Enable, Up/Down, Count ITR2 Mode Slave Controller ITR3 Prescaler AutoReload TI1F_ED Register Encoder Interface Counter Repeat TI1FP1 Register TI2FP1 Repetition counter...
Page 178 GD32F1x0 User Manual Figure 9-2. Counter timing diagram with prescaler division change from 1 to 2 PCLK CNT_CLK CNT_REG Reload Pulse Figure 9-3. Counter timing diagram with prescaler division change from 1 to 4 PCLK CNT_CLK CNT_REG FA FB FC Reload Pulse modify PSC Vaule Prescaler CR...
Page 179 GD32F1x0 User Manual is set, the update events generated after the number (TIMERx_CREP+1) of overflow. Else the update event is generated at each counter overflow.The counting direction bit DIR in the TIMER1_CTLR1 register should be set to 0 for the upcounting mode. When the update event is set by the UPG bit in the TIMER1_EVG register, the counter value will be initialized to 0 and generates an update event.
Page 180 GD32F1x0 User Manual Figure 9-4. Counter timing diagram, internal clock divided by 1 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-5. Counter timing diagram, internal clock divided by 2 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF)
Page 181: Figure 9-7. Counter Timing Diagram, Internal Clock Divided By N
GD32F1x0 User Manual Figure 9-6. Counter timing diagram, internal clock divided by 4 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-7. Counter timing diagram, internal clock divided by N...
Page 182: Figure 9-8. Counter Timing Diagram, Update Event When Arse=0
GD32F1x0 User Manual Figure 9-8. Counter timing diagram, update event when ARSE=0 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Auto-reload register modify CARL Vaule Figure 9-9. Counter timing diagram, update event when ARSE=1 PCLK CNT_CLK CNT_REG 63 64 02 03 overflow...
Page 183 GD32F1x0 User Manual Downcounting mode In this mode the counter counts continuously from the counter-reload value, which is defined in the TIMER1_CARLregister, to 0 in a count-down direction. Once the counter reaches 0, the counter restarts to count once again from the counter-reload value. If the repetition counter is set, the update event generated after the number (TIMERx_CREP+1) of underflow.
Page 184 GD32F1x0 User Manual Figure 9-11. Counter timing diagram, internal clock divided by 2 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-12. Counter timing diagram, internal clock divided by 4 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF)
Page 185: Figure 9-13. Counter Timing Diagram, Internal Clock Divided By N
GD32F1x0 User Manual Figure 9-13. Counter timing diagram, internal clock divided by N PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-14. Counter timing diagram, update event when repetition counter is not used PCLK CNT_CLK CNT_REG 5D 5C overflow Update event (UPE)
Page 186: Figure 9-15. Counter Timing Diagram, Internal Clock Divided By 1, Timerx_Carl = 0X5
GD32F1x0 User Manual Setting the UPG bit in the TIMER1_EVG register will initialize the counter value to 0 irrespective of whether the counter is counting up or down in the center-align counting mode and generates an update event. The UPIF bit in the TIMER1_EVG register can be set to 1 when an underflow event at count- down (CAM in TIMER1_CTLR1 is “01”), an overflow event at count-up (CAM in TIMER1_CTLR1 is “10”) or both of them occur (CAM in TIMER1_CTLR1 is “11”).
Page 187: Figure 9-17. Counter Timing Diagram, Internal Clock Divided By 4, Timerx_Carl=0X63
GD32F1x0 User Manual Figure 9-16. Counter timing diagram, internal clock divided by 2 PCLK CNT_CLK CNT_REG underflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-17. Counter timing diagram, internal clock divided by 4, TIMERx_CARL=0x63 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF)
Page 188: Figure 9-18. Counter Timing Diagram, Internal Clock Divided By N
GD32F1x0 User Manual Figure 9-18. Counter timing diagram, internal clock divided by N Figure 9-19. Counter timing diagram, update event with ARSE=1(counter underflow) PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Auto-reload register modify CARL Vaule Auto-reload shadow register...
Page 189: Figure 9-20. Counter Timing Diagram, Update Event With Arse=1 (Counter Overflow)
GD32F1x0 User Manual Figure 9-20. Counter timing diagram, Update event with ARSE=1 (counter overflow) PCLK CNT_CLK CNT_REG 7D 7E 61 60 5D 5C overflow Update event (UPE) Update interrupt flag (UPIF) Auto-reload register modify CARL Vaule Auto-reload shadow register Counter Repetition Counter Repetition is used to generator update event or updates the timer registers only after a given number (N+1) of cycles of the counter, where N is CREP in TIMER1_CREP register.
Page 190 GD32F1x0 User Manual Figure 9-21. Update rate examples depending on mode and TIMERx_CREP Clock selection The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter.  Internal timer clock PCLK The default internal clock source is the APB2 clock CK_APB2 used to drive the counter prescaler when the slave mode is disabled.
Page 191 GD32F1x0 User Manual  Quadrature decoder To select Quadrature Decoder mode the SMC field should be set to 0x1, 0x2 or 0x3 in the TIMER1_SMC register. The Quadrature Decoder function uses two input states of the TIMER1_CH1 and TIMER1_CH2 pins to generate the clock pulse to drive the counter prescaler.
Page 192: Figure 9-23. Capture/Compare Channel (Example: Channel 1 Input Stage)
GD32F1x0 User Manual generate a TIxFPx signal for the input capture function. The effective input event number can be set by the channel input prescaler register (CHx_ICP). Figure 9-23. Capture/compare channel (example: channel 1 input stage) TI1F_Rising TI1FP1 filter Edge Detector downcounter TI1F_Falling TI2FP1...
Page 193: Figure 9-24. Capture/Compare Channel 1 Main Circuit
GD32F1x0 User Manual Figure 9-24. Capture/compare channel 1 main circuit APB BUS MCU-peripheral interface CHCC1 Capture/compare preload register CHCC1 CH1M[0] CH1M[1] CH1M[0] Capture/compare shadow CH1M[1] CH1OSE register CNT>CHCC1 CNT=CHCC1 CH1ICP CH1E Counter CH1G TM_EVG  Output stage The TIMER1 has four channels for compare match, single pulse or PWM output function. Figure 9-25.
Page 194 GD32F1x0 User Manual Input Capture Mode When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (TIMER1_CHCCx) when an effective input signal transition occurs. Once the capture event occurs, the CHxIF flag in the TIMER1_STR register is set. If the CHxIF bit is already set, i.e., the flag has not yet been cleared by software, and another capture event on this channel occurs, the corresponding channel Over-Capture flag, named CHxOF, will be set.Once the capture event occurs, a DMA request is generated depending...
Page 195: Figure 9-27. Output Compare Toggle Mode, Toggle On Oc1
GD32F1x0 User Manual In ouput mode, the channel output set to active level when the comparision between the counter and TIMER1_CHCCx registers match, by set the CHxOM to 001. The channel output set to inactive level when the comparision between the counter and TIMER1_CHCCx registers match, by set the CHxOM to 010.
Page 196: Figure 9-29. Output Compare Pwm Mode1 On Oc1, Center-Aligned Counting Mode
GD32F1x0 User Manual Figure 9-29. Output compare PWM mode1 on OC1, center-aligned counting mode 0039 0039 003A 003B 0100 00FF 00FE 003B 003A 003A Match detected on CHCC1 Interrupt generated if enabled Channel Output Reference Signal When the TIMER1 is used in the compare match output mode, the OCxREF signal (Channel x Output Reference signal) is defined by setting the CHxOM bits.
Page 197: Figure 9-30. Complementary Output With Dead-Time Insertion
GD32F1x0 User Manual in the TIMER1_CHE register. If CHxE, CHxNE and POE bits are 1, dead-time should insertion. The rising edge of OCx output is delayed relative to the rising edge of OCxREF and the rising edge of OCxN output is delayed relative to the falling edge of OCxREF.The delay value is a 8-bit dead-time counter determined by DT field in TIMER1_BKDT register.If the delay value is greater than the width of the active output (OCx or OCxN) then the corresponding pulse is not generated.
Page 198 GD32F1x0 User Manual...
Page 199: Figure 9-34. Single Pulse Mode
GD32F1x0 User Manual Single Pulse Mode Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit CEN in the TIMER1_CTLR1 register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the trigger signals edge or by setting the CEN bit to 1 using software.
Page 200: Figure 9-35. Example Of Counter Operation In Encoder Interface Mode
GD32F1x0 User Manual The DIR bit is modified by hardware automatically during each input source transition. The input source can be either TI1 only, TI2 only or both TI1 and TI2, the selection made by setting the SMC field to 0x01, 0x02 or 0x03. The mechanism for changing the counter direction is shown in the following table.
Page 201: Figure 9-36. Example Of Encoder Interface Mode With Ti1Fp1 Polarity Inverted
GD32F1x0 User Manual Figure 9-36. Example of encoder interface mode with TI1FP1 polarity inverted Slave Controller The TIMER1 can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMC field in the TIMER1_SMC register.
Page 202: Figure 9-38. Control Circuit In Pause Mode
GD32F1x0 User Manual  Pause mode In the Pause Mode, the selected TI1 input signal level is used to control the counter start/stop operation. The counter starts to count when the selected TI1 signal is at a high level and stops counting when the TI1 signal is changed to a low level, here the counter will maintain its present value and will not be reset.
Page 203: Figure 9-40. Timer1 Master/Slave Mode Timer Example
GD32F1x0 User Manual Figure 9-40. Timer1 Master/Slave mode timer example TIMER1 TIMER 15 TRGS Master TRGO1 mode Prescaler Counter control TIMER 2 Master TRGO1 mode Prescaler Counter control TIMER 3 Trigger Slave mode Master Prescaler Counter selection control TRGO1 mode Prescaler Counter control...
Page 204 TIMER1_CNT_REG In this example, we also can use update Event as trigger source instead of enable signal. Refer to figure below. Do as follow: 1. Configure Timer 2 in master mode and send its Update Event (UPE) as trigger output (MMC=010 in the TIMER2_CTLR2 register).
Page 205 GD32F1x0 User Manual figure below. Timer 1 counts on the divided internal clock only when Timer 2 is enable. Both counter clock frequencies are divided by 3 by the prescaler compared to PCLK (fCNT_CLK = fPCLK /3). Do as follow: 1.
Page 206 GD32F1x0 User Manual Figure 9-44. Gating timer 1 with OC1REF of timer 2  Using an external trigger to start 2 timers synchronously We configure the start of Timer 1 is triggered by the enable of Timer 2, and timer 2 is triggered by its TI1 input rises edge.
Page 207 TIMER1_EN TIMER1_CK TIMER1_CNT_REG Timer debug mode When the Cortex™-M3 halted, and the DBG_TIMERx_STOP configuration bit in MCUDBG module set to 1, the TIMERx counter stops. 9.1.4. TIMER1 registers TIMER1 control register 1 (TIMER1_CTLR1) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved CDIV[1:0] ARSE...
Page 208 GD32F1x0 User Manual timer clock (PCLK) and the dead-time and sampling clock (DTS), which is used by the dead-time generators and the digital filters. 00: f PCLK 01: f PCLK 10: f PCLK 11: Reserved ARSE Auto-reload shadow enable 0: The shadow register for TIMERx_CARL register is disabled 1: The shadow register TIMERx_ CARL register is enabled CAM[1:0] Center-aligned mode selection...
Page 209 GD32F1x0 User Manual 1: When enabled, only counter overflow/underflow generates an update interrupt or DMA request. UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: update event enable. The update event is generate and the buffered registers are loaded with their preloaded values when one of the following events occurs: –...
Page 210 GD32F1x0 User Manual Refer to ISO1 bit ISO1N Idle state of channel 1 complementary output 0: When POE bit is reset, OC1N is set low. 1: When POE bit is reset, OC1N is set high This bit can be modified only when LK[1:0] bits in TIMERx_BKDT register is 00. ISO1 Idle state of channel 1 output 0: When POE bit is reset, OC1 is set low.
Page 211 GD32F1x0 User Manual CCUC Capture/compare control shadow register update control When the Capture/compare control shadow registers (for CHxE, CHxNE and CHxOM bits) are enabled (CCSE=1), this bit control when these shadow registers update. 0: The shadow registers update by when CCUG bit is set. 1: The shadow registers update by when CCUG bit is set or an rising edge of TRGI occurs.
Page 212 GD32F1x0 User Manual The frequency of external trigger signal ETIP must not be at higher than 1/4 of TIMERx CLK frequency. When the external trigger signal is a fast clocks, the prescaler can be enabled to reduce ETIP frequency.. 00: Prescaler disable 01: ETIP frequency will be divided by 2 10: ETIP frequency will be divided by 4 11: ETIP frequency will be divided by 8...
Page 213 GD32F1x0 User Manual 110: Filtered channel 2 Input (TI2FP2) 111: External trigger input (ETIF) These bits must not be changed when slave mode is enabled. OCRC OCREF clear source selection 0: OCREF_CLR_INT is connected to the OCREF_CLR input 1: OCREF_CLR_INT is connected to ETIF SMC[2:0] Slave mode control 000: Disable mode.The prescaler is clocked directly by the internal clock when CEN...
Page 214 GD32F1x0 User Manual CCUDE Channel control update DMA request enable 0: Channel control update DMA request disabled 1: Channel control update DMA request enabled CH4DE Channel 4 DMA request enable 0: Channel 4 DMA request disabled 1: Channel 4 DMA request enabled CH3DE Channel 3 DMA request enable 0: Channel 3 DMA request disabled...
Page 215 GD32F1x0 User Manual 1: Channel 1 interrupt enabled UPIE Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled TIMER1 status register (TIMER1_STR) Address offset: 0x10 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved CH4OF CH3OF CH2OF...
Page 216 GD32F1x0 User Manual 0: No trigger event occurred. 1: Trigger interrupt occurred. CCUIF Channel control update interrupt flag This flag is set by hardware when channel control update event occurs, and cleared by software 0: No channel control update interrupt occurred 1: Channel control update interrupt occurred CH4IF Channel 4 interrupt enable...
Page 217 GD32F1x0 User Manual 0: No generate a break event 1: Generate a break event TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STR register is set, related interrupt or DMA transfer can occur if enabled.
Page 218 GD32F1x0 User Manual This register can be accessed by half-word(16-bit) or word(32-bit) CH2OM[2:0] CH1OM[2:0] CH1OSE CH2M[1:0] CH1M[1:0] CH2ICF[3:0] CH2ICP[1:0] CH1ICF[3:0] CH1ICP[1:0] Output compare mode: Bits Fields Descriptions CH2OCE Channel 2 output compare clear enable Refer to CH1OCE description 14:12 CH2OM[2:0] Channel 2 output compare mode Refer to CH1OM description CH2OSE...
Page 219 GD32F1x0 User Manual output compare register TIMER1_CHCC1. 011: Toggle on match. OC1REF toggles when the counter matches the output compare register TIMER1_CHCC1. 100: Force low. OC1REF is forced low level. 101: Force high. OC1REF is forced high level. 110: PWM mode 1. When counting up, OC1REF is high as long as the counter is smaller than TIMER1_CHCC1 else low.
Page 220 GD32F1x0 User Manual only if an internal trigger input is selected through TRGS bits in TIMER_SMC register. Input capture mode: Bits Fields Descriptions 15:12 CH2ICF[3:0] Channel 2 input capture filter control Refer to CH1ICF description 11:10 CH2ICP[1:0] Channel 2 input capture prescaler Refer to CH1ICP description CH2M[1:0] Channel 2 mode selection...
Page 221 GD32F1x0 User Manual 00: Prescaler disable, capture is done on each channel input edge 01: Capture is done every 2 channel input edges 10: Capture is done every 4 channel input edges 11: Capture is done every 8 channel input edges CH1M[1:0] Channel 1 mode selection This bit-field specifies the direction of the channel and the input signal selection.
Page 222 GD32F1x0 User Manual 01: Channel 4 is configured as input, IC4 is mapped on TI4 10: Channel 4 is configured as input, IC4 is mapped on TI3 11: Channel 4 is configured as input, IC4 is mapped on TRC. This mode is working only if an internal trigger input is selected through TRGS bits in TIMER_SMC register.
Page 223 GD32F1x0 User Manual register. CH3ICF[3:0] Channel 3 input capture filter control Refer to CH1ICF description CH3ICP[1:0] Channel 3 input capture prescaler Refer to CH1ICP description CH3M[1:0] Channel 3 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is OFF (CH3E bit in TIMER1_CHE register is reset).
Page 224 GD32F1x0 User Manual CH3E Channel 3 enable Refer to CH1E description CH2NP Channel 2 complementary output polarity Refer to CH1NP description CH2NE Channel 2 complementary output enable Refer to CH1NE description CH2P Channel 2 polarity Refer to CH1P description CH2E Channel 2 enable Refer to CH1E description CH1NP...
Page 225 GD32F1x0 User Manual This bit cannot be modified when LK [1:0] bit-filed in TIMERx_BKDT register is 11 or CH1E Channel 1 enable When channel 1 is configured in input mode, setting this bit enables OC1 signal in active state. When channel 1 is configured in output mode, setting this bit enables the capture event in channel1.
Page 226 GD32F1x0 User Manual This register can be accessed by half-word(16-bit) or word(32-bit) CARL[15:0] Bits Fields Descriptions 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. TIMER1 counter repetition register (TIMER1_CREP) Address offset: 0x30 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved...
Page 227 GD32F1x0 User Manual shadow register updates every update event. TIMER1 channel 2 capture compare register (TIMER1_CHCC2) Address offset: 0x38 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) CHCC2[15:0] Bits Fields Descriptions 15:0 CHCC2[15:0] Capture or compare value of channel2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 228 GD32F1x0 User Manual CHCC4[15:0] Bits Fields Descriptions 15:0 CHCC4[15:0] Capture or compare value of channel 4 When channel 4 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 4 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 229 GD32F1x0 User Manual This bit can be set to enable the BRK and CCS clock failure event inputs. 0: Break inputs disabled 1; Break inputs enabled This bit can be modified onlywhen LK[1:0] bit-filed in TIMERx_BKDT register is 00. Run mode off-state configure When POE bit is set, this bit specifies the output state for the channels which has a complementary output and has been configured in output mode.
Page 230 GD32F1x0 User Manual This bit can be modified only when LK[1:0] bit-filed in TIMERx_BKDT register is 00.
Page 231 GD32F1x0 User Manual TIMER1 configuration register (TIMER1_CFGR) GD32F170xx GD32F190xx devices Address offset: 0xFC Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved CCSEL OUTSEL Bits Fields Descriptions 15:2 Reserved Must be kept at reset value CCSEL Write CC register selection This bit-field set and reset by software.
Page 232: Figure 9-46. General Timer Block Diagram (Timer2 And Timer3)
GD32F1x0 User Manual output, generation of PWM waveform (edge and center-aligned Mode), and single pulse mode output.  Interrupt/DMA generation by update, trigger event, input capture event, output compare match event  Synchronization circuit to control TIMERx with external signals or to interconnect several timers together.
Page 233 GD32F1x0 User Manual Figure 9-47. Counter timing diagram with prescaler division change from 1 to 2 PCLK CNT_CLK CNT_REG Reload Pulse Figure 9-48. Counter timing diagram with prescaler division change from 1 to 4 PCLK CNT_CLK CNT_REG FA FB FC Reload Pulse modify PSC Vaule Prescaler CR...
Page 234 GD32F1x0 User Manual generated at each counter overflow.The counting direction bit DIR in the TIMERx_CTLR1 register should be set to 0 for the upcounting mode. When the update event is set by the UPG bit in the TIMER1_EVG register, the counter value will be initialized to 0 and generates an update event.
Page 235 GD32F1x0 User Manual Figure 9-50. Counter timing diagram, internal clock divided by 2 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-51. Counter timing diagram, internal clock divided by 4 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF)
Page 236: Figure 9-52. Counter Timing Diagram, Internal Clock Divided By N
GD32F1x0 User Manual Figure 9-52. Counter timing diagram, internal clock divided by N Figure 9-53. Counter timing diagram, update event when ARSE=0 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Auto-reload register modify CARL Vaule...
Page 237: Figure 9-54. Counter Timing Diagram, Update Event When Arse=1
GD32F1x0 User Manual Figure 9-54. Counter timing diagram, update event when ARSE=1 PCLK CNT_CLK CNT_REG overflow Downcounting mode In this mode the counter counts continuously from the counter reload value, which is defined in the TIMERx_CARL register, to 0 n a count-down direction. Once the counter reaches 0, the counter restarts to count once again from the counter-reload value.
Page 238 GD32F1x0 User Manual Figure 9-55. Counter timing diagram, internal clock divided by 1 PCLK CNT_CLK CNT_REG 5D 5C overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-56. Counter timing diagram, internal clock divided by 2 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF)
Page 239: Figure 9-58. Counter Timing Diagram, Internal Clock Divided By N
GD32F1x0 User Manual Figure 9-57. Counter timing diagram, internal clock divided by 4 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-58. Counter timing diagram, internal clock divided by N...
Page 240: Figure 9-59. Counter Timing Diagram, Update Event When Counter Is Not Used
GD32F1x0 User Manual Figure 9-59. Counter timing diagram, update event when counter is not used PCLK CNT_CLK CNT_REG 5D 5C overflow Update event (UPE) Update interrupt flag (UPIF) Auto-reload register modify CARL Vaule Center-aligned counting mode In the center-aligned counting mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively.
Page 241: Figure 9-60. Counter Timing Diagram, Internal Clock Divided By 1, Timerx_Carl = 0X5
GD32F1x0 User Manual Figure 9-60. Counter timing diagram, internal clock divided by 1, TIMERx_CARL = 0x5 PCLK CNT_CLK CNT_REG underflow overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-61. Counter timing diagram, internal clock divided by 2 PCLK CNT_CLK CNT_REG underflow Update event (UPE)
Page 242: Figure 9-62. Counter Timing Diagram, Internal Clock Divided By 4, Timerx_Carl=0X63
GD32F1x0 User Manual Figure 9-62. Counter timing diagram, internal clock divided by 4, TIMERx_CARL=0x63 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-63. Counter timing diagram, internal clock divided by N...
Page 243: Figure 9-64. Counter Timing Diagram, Update Event With Arse=1(Counter Underflow)
GD32F1x0 User Manual Figure 9-64. Counter timing diagram, update event with ARSE=1(counter underflow) PCLK CNT_CLK CNT_REG underflow Update event (UPE) Update interrupt flag (UPIF) Auto-reload register modify CARL Vaule Auto-reload shadow register Figure 9-65. Counter timing diagram, Update event with ARSE=1 (counter overflow) PCLK CNT_CLK CNT_REG...
Page 244: Cnt_Clk
GD32F1x0 User Manual Clock selection The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter.  Internal timer clock PCLK The default internal clock source is the APB2 clock CK_APB2 used to drive the counter prescaler when the slave mode is disabled.
Page 245 GD32F1x0 User Manual setting the TRGS field. When the ITI signal is selected as the clock source, the internal edge detection circuitry will generate a clock pulse during each ITI signal rising or falling edge to drive the counter prescaler. ...
Page 247: Figure 9-69. Output Stage Of Capture/Compare Channel (Channel 1)
GD32F1x0 User Manual The TIMERx has four channels for compare match, single pulse or PWM output function. Figure 9-69. Output stage of capture/compare channel (channel 1) Input Capture Mode When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (TIMERx_CHCCx) when an effective input signal transition occurs.
Page 248: Figure 9-70. Output Compare Toggle Mode, Toggle On Oc1
GD32F1x0 User Manual the PWM duty. Output Compare Mode/PWM Mode When the channel is used as a output mode by setting the CCxM in the the channel control register (TIMERx_CHCTLRx) to 00, the channel outputs waveform according to the CHxOM bits in the the the channel control register (TIMERx_CHCTLRx), and the comparision between the counter and TIMERx_CHCCx registers.
Page 249: Figure 9-71. Output Compare Pwm Mode1 On Oc1, Upcounting Mode
GD32F1x0 User Manual Figure 9-71. Output compare PWM mode1 on OC1, upcounting mode 0039 003A 003B 003A Match detected on CHCC1 Interrupt generated if enabled Figure 9-72. Output compare PWM mode1 on OC1, center-aligned counting mode CNT_REG 0039 0039 003A 003B 0100 00FF...
Page 250 GD32F1x0 User Manual setting the CHxOM field to 0x04/0x05. Here the output can be forced to an inactive/active level irrespective of the comparison condition between the counter and the TIMERx_CHCCx values. The OCxREF signal can be forced to 0 when the ETIF signal is derived from the external TIMERx_ETI pin and when it is set to a high level by setting the CHxOCE bit to 1 in the TIMERx_CHCTLR1 register.
Page 251: Figure 9-74. Example Of Counter Operation In Encoder Interface Mode
GD32F1x0 User Manual "-" means "no counting"; "X" means impossible. Note: Figure 9-74. Example of counter operation in encoder interface mode Figure 9-75. Example of encoder interface mode with TI1FP1 polarity inverted Slave Controller The TIMERx can be synchronized with an external trigger in several modes including the Restart mode, the Pause mode and the Trigger mode which is selected by the SMC field in the TIMERx_SMC register.
Page 252: Figure 9-76. Control Circuit In Restart Mode
GD32F1x0 User Manual will no update event will be generated, however the counter and prescaler are still reinitialized when the TI1 rising edge occurs. If the UPDIS bit in the TIMERx_CTLR1 register is cleared to enable the update event to occur, an update event will be generated together with the TI1 rising edge, then all the preloaded registers will be updated.
Page 253: Figure 9-78. Control Circuit In Trigger Mode
GD32F1x0 User Manual Figure 9-78. Control circuit in trigger mode Timer Interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the Master mode while configuring another timer to be in the Slave mode.
Page 255 GD32F1x0 User Manual 0: Count up 1: Count down This bit is read only when the timer is configured in Center-aligned mode or Encoder mode. Single pulse mode. 0: Counter continues after update event. 1: The CEN is cleared by hardware and the counter stops at update event. Update source This bit is used to select the update event sources.
Page 256 GD32F1x0 User Manual Bits Fields Descriptions 15:8 Reserved Must be kept at reset value TI1S Channel 1 trigger input selection 0: The TIMERx_CH1 pin input is selected as channel 1 trigger input. 1: The result of combinational XOR of TIMERx_CH1, CH2 and CH3 pins is selected as channel 1 trigger input.
Page 257 GD32F1x0 User Manual ETPL ECM2E ETPSC[1:0] ETFC[3:0] TRGS[2:0] OCRC SMC[2:0] Bits Fields Descriptions ETPL External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at high level or rising edge. 1: ETI is active at low level or falling edge. ECM2E External clock mode 2 enable In external clock mode 2, the counter is clocked by any active edge on the ETIF...
Page 258 GD32F1x0 User Manual 1010: f /16, N=5. SAMP 1011: f /16, N=6. SAMP 1100: f /16, N=8. SAMP 1101: f /32, N=5. SAMP 1110: f /32, N=6. SAMP 1111: f /32, N=8. SAMP Master-slave mode The effect of an event on the trigger input is delayed in this mode to allow a perfect synchronization between the current timer and its slaves through TRGO.
Page 259 GD32F1x0 User Manual 101: Pause Mode.The trigger input enables the counter clock when it is high and disables the counter when it is low. 110: Trigger Mode.A rising edge of the trigger input enables the counter. The counter cannot be disabled by the slave mode controller. 111: External Clock Mode 1.The counter counts on the rising edges of the selected trigger.
Page 260 GD32F1x0 User Manual 1: Update DMA request enabled Reserved Must be kept at reset value TRGIE Trigger interrupt enable 0: Trigger interrupt disabled 1: Trigger interrupt enabled Reserved Must be kept at reset value. CH4IE Channel4 interrupt enable 0: Channel 4 interrupt disabled 1: Channel4 interrupt enabled CH3IE Channel3 interrupt enable...
Page 261 0: No trigger event occurred 1: Trigger interrupt occurred Reserved Must be kept at reset value CH4IF Channel4 interrupt enable Refer to CH1IF description CH3IF Channel3 interrupt enable Refer to CH1IF description CH2IF Channel2 interrupt enable Refer to CH1IF description CH1IF Channel 1 interrupt flag This flag is set by hardware and cleared by software.
Page 262 GD32F1x0 User Manual Reserved TRGG Res. CH4G CH3G CH2G CH1G Bits Fields Descriptions 15:8 Reserved Must be kept at reset value Break event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the POE bit is cleared and BKIF flag is set, related interrupt or DMA transfer can occur if enabled.
Page 263 GD32F1x0 User Manual 1: Generate an update event TIMERx channel control register 1 (TIMERx_CHCTLR1) Address offset: 0x18 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) CH2OM[2:0] CH1OM[2:0] CH1OSE CH2M[1:0] CH1M[1:0] CH2ICF[3:0] CH2ICP[1:0] CH1ICF[3:0] CH1ICP[1:0] Output compare mode: Bits Fields Descriptions...
Page 264 GD32F1x0 User Manual drives OC1 and OC1N. OC1REF is active high, while OC1 and OC1N active level depends on CH1P and CH1NP bits. 000: Frozen.The OC1REF signal keep stable, independent of the comparison between the output compare register TIMERx_CHCC1 and the counter. 001: Set high on match.OC1REF signal is forced high when the counter matches the output compare register TIMERx_CHCC1.
Page 265 GD32F1x0 User Manual This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is OFF (CH1E bit in TIMERx_CHE register is reset). 00: Channel 1 is configured as output 01: Channel 1 is configured as input, IC1 is mapped on TI1 10: Channel 1 is configured as input, IC1 is mapped on TI2 11: Channel 1 is configured as input, IC1 is mapped on TRC.
Page 266 GD32F1x0 User Manual 1100: f /16, N=8 SAMP 1101: f /32, N=5 SAMP 1110: f /32, N=6 SAMP 1111: f /32, N=8 SAMP CH1ICP[1:0] Channel 1 input capture prescaler This bit-field specifies the ratio of the prescaler on channel 1 input.The prescaler is reset when CH1E bit in TIMERx_CHE register is reset.
Page 267 GD32F1x0 User Manual CH4OFE Channel 4 output compare fast enable Refer to CH1OFE description CH4M[1:0] Channel 4 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is OFF (CH4E bit in TIMERx_CHE register is reset).
Page 268 GD32F1x0 User Manual This bit-field is writable only when the channel is OFF (CH4E bit in TIMERx_CHE register is reset). 00: Channel 4 is configured as output 01: Channel 4 is configured as input, IC4 is mapped on TI4 10: Channel 4 is configured as input, IC4 is mapped on TI3 11: Channel 4 is configured as input, IC4 is mapped on TRC.
Page 269 GD32F1x0 User Manual Refer to CH1E description CH3NP Channel 3 polarity Refer to CH1NP description Reserved Must be kept at reset value CH3P Channel 3 polarity Refer to CH1P description CH3E Channel 3 enable Refer to CH1E description CH2NP Channel 2 polarity Refer to CH1NP description Reserved Must be kept at reset value...
Page 270 GD32F1x0 User Manual CH1E Channel 1 enable When channel 1 is configured in input mode, setting this bit enables OC1 signal in active state. When channel 1 is configured in output mode, setting this bit enables the capture event in channel1. 0: Channel 1 disabled.
Page 271 GD32F1x0 User Manual TIMERx counter auto reload register (TIMERx_CARL) Address offset: 0x2C Reset value: 0x0000 This register has to be accessed by word(32-bit) CARL [31:16] TIMER2 ONLY CARL [15:0] Bits Fields Descriptions 31:16 CARL [31:16] Counter auto reload value. Only TIMER2 has this high 16bit counter value. 15:0 CARL[15:0] Counter auto reload value...
Page 272 GD32F1x0 User Manual Reset value: 0x0000 This register has to be accessed by word(32-bit) CHCC2 [31:16] TIMER2 ONLY CHCC2 [15:0] Bits Fields Descriptions 31:16 CHCC2 Capture or compare value of channel2. Only TIMER2 has this high 16bit counter [31:16] value. 15:0 CHCC2 [15:0] Capture or compare value of channel2...
Page 273 GD32F1x0 User Manual TIMERx channel 4 capture compare register (TIMERx_CHCC4) Address offset: 0x40 Reset value: 0x0000 This register has to be accessed by word(32-bit) CHCC4 [31:16] TIMER2 ONLY CHCC4 [15:0] Bits Fields Descriptions 31:16 CHCC4 Capture or compare value of channel 4. Only TIMER2 has this high 16bit counter [31:16] value.
Page 274 GD32F1x0 User Manual TIMERx DMA transfer register (TIMERx_DTRSF) Address offset: 0x4C Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) DTRSF[15:0] Bits Fields Descriptions 15:0 DTRSF[15:0] DMA transfer When a read or write operation is assigned to this register, the register located at the address range (DBAR + burst counter) x 4 from TIMERx_CTLR1 will be accessed.
Page 275: Figure 9-80. General Timer Block Diagram (Timer6)
GD32F1x0 User Manual 9.3. Basic timer (TIMER6) 9.3.1. Introduction The general timers (TIMER6) consist of one 16-bit counter auto reload register (TIMERx_CARL) and several control registers. It can be used for general timer, and it is also used by DAC(Digital to analog converter). TIMER6’s trgo is connected to DAC which can be drived by this trigger.
Page 276 GD32F1x0 User Manual Figure 9-81. Counter timing diagram with prescaler division change from 1 to 2 PCLK CNT_CLK CNT_REG Reload Pulse Figure 9-82. Counter timing diagram with prescaler division change from 1 to 4 PCLK CNT_CLK CNT_REG FA FB FC Reload Pulse modify PSC Vaule Prescaler CR...
Page 277 GD32F1x0 User Manual generated at each counter overflow. When the update event is set by the UPG bit in the TIMERx_EVG register, the counter value will be initialized to 0 and generates an update event. If set the UPDIS bit in TIMERx_CTLR1 register, the update event is disabled. When an update event occurs, all the registers (autoreload register, prescaler register) are updated.
Page 278 GD32F1x0 User Manual 9.3.4. TIMER6 registers TIMER6 control register 1 (TIMER6_CTLR1) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved ARSE Reserved UPDIS Bits...
Page 279 GD32F1x0 User Manual 0: Counter disable 1: Counter enable The CEN bit must be set by software when timer works in external clock, pause mode and encoder mode. While in trigger mode, the hardware can set the CEN bit automatically. TIMER6 control register 2 (TIMER6_CTLR2) Address offset: 0x04 Reset value: 0x0000...
Page 280 GD32F1x0 User Manual Reserved Must be kept at reset value TIMER6 DMA and interrupt enable register (TIMER6_DIE) Address offset: 0x0C Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved UPDE Reserved UPIE Bits Fields Descriptions 15:9 Reserved Must be kept at reset value UPDE...
Page 281 GD32F1x0 User Manual Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved Bits Fields Descriptions 15:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared if the center-aligned or upcounting mode is selected, else (downcounting) it takes the auto-reload value.
Page 282 GD32F1x0 User Manual filed will be loaded to the corresponding shadow register at every update event. TIMER6 counter auto reload register (TIMER6_CARL) Address offset: 0x2C Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) CARL[15:0] Bits Fields Descriptions 15:0 CARL[15:0]...
Page 283: Figure 9-84. General Timer Block Diagram (Timer14)
GD32F1x0 User Manual 9.4. General timer (TIMER14) 9.4.1. Introduction The general timer (TIMER14) consists of one 16-bit up -counter; one capture/compare register (TIMERx_CHCC), one counter auto reload register (TIMERx_CARL) and several control registers. They can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as output compare or PWM output.
Page 284 GD32F1x0 User Manual be changed on the fly but be taken into account at the next update event. Figure 9-85. Counter timing diagram with prescaler division change from 1 to 2 PCLK CNT_CLK CNT_REG Reload Pulse Figure 9-86. Counter timing diagram with prescaler division change from 1 to 4 PCLK CNT_CLK CNT_REG...
Page 285 GD32F1x0 User Manual counter reaches the counter reload value, the counter restarts to count once again from 0. The update event is generated at each counter overflow. When the update event is set by the UPG bit in the TIMERx_EVG register, the counter value will be initialized to 0 and generates an update event.
Page 286 GD32F1x0 User Manual Figure 9-88. Counter timing diagram, internal clock divided by 2 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-89. Counter timing diagram, internal clock divided by 4 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF)
Page 287: Figure 9-90. Counter Timing Diagram, Internal Clock Divided By N
GD32F1x0 User Manual Figure 9-90. Counter timing diagram, internal clock divided by N Figure 9-91. Counter timing diagram, update event when ARSE=0 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Auto-reload register modify CHAR Vaule...
Page 288: Figure 9-92. Counter Timing Diagram, Update Event When Arse=1
GD32F1x0 User Manual Figure 9-92. Counter timing diagram, update event when ARSE=1 PCLK CNT_CLK CNT_REG 63 64 02 03 overflow Update event (UPE) Update interrupt flag (UPIF) Auto-reload register modify CHAR Vaule Auto-reload shadow register Clock selection Basic timer has the unique clock source which is controlled by RCC. Counter and prescaler counter are clocked by this internal clock, except UPG is asserted.
Page 289 GD32F1x0 User Manual Figure 9-93. Control circuit in normal mode, internal clock divided by 1 Capture/compare channels The TIMER14 has one independent channel which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage.
Page 290: Figure 9-94. Capture/Compare Channel (Example: Input Stage)
GD32F1x0 User Manual Figure 9-94. Capture/compare channel (example: input stage) TI1F_Rising TI1FP1 filter Edge Detector downcounter TI1F_Falling TI2FP1 divider /1, /2, /4, /8 CH1ICF[3:0] CH1P/ CH1NP CHCTLR1 CH1E CH1ICP[1:0] CH1M[ 1:0 ] CHCTLR1 CHCTLR1  Channel controller The GPTM has one independent channels which can be used as capture inputs or compare match outputs.
Page 291: Figure 9-96. Output Stage Of Capture/Compare Channel
GD32F1x0 User Manual The TIMER14 has one channel for compare match or PWM output function. Figure 9-96. Output stage of capture/compare channel Input Capture Mode When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (TIMERx_CHCCx) when an effective input signal transition occurs.
Page 292: Figure 9-97. Output Compare Toggle Mode, Toggle On Oc1
GD32F1x0 User Manual the TIMERx_CHCC1 can measure the PWM period and the TIMERx_CHCC2 can measure the PWM duty. Output Compare Mode/PWM Mode When the channel is used as a output mode by setting the CCxM in the the channel control register (TIMERx_CHCTLRx) to 00, the channel outputs waveform according to the CHxOM bits in the the the channel control register (TIMERx_CHCTLRx), and the comparision between the counter and TIMERx_CHCCx registers.
Page 293: Figure 9-98. Output Compare Pwm Mode1 On Oc1, Upcounting Mode
GD32F1x0 User Manual Figure 9-98. Output compare PWM mode1 on OC1, upcounting mode 0039 003A 003B 003A Match detected on CHCC1 Interrupt generated if enabled Figure 9-99. Output compare PWM mode1 on OC1, center-aligned counting mode CNT_REG 0039 0039 003A 003B 0100 00FF...
Page 294 GD32F1x0 User Manual setting the CHxOM field to 0x04/0x05. Here the output can be forced to an inactive/active level irrespective of the comparison condition between the counter and the TIMERx_CHCCx values. The OCxREF signal can be forced to 0 when the ETIF signal is derived from the external TIMERx_ ETI pin and when it is set to a high level by setting the CHxOCE bit to 1 in the TIMERx_CHCTLR1 register.
Page 295 GD32F1x0 User Manual...
Page 296 GD32F1x0 User Manual 1: update event disable. The buffered registers keep their value, while the counter and the prescaler are reinitialized if the UPG bit is set or if the slave mode controller generates a hardware reset event. Counter enable 0: Counter disable 1: Counter enable The CEN bit must be set by software when timer works in external clock, pause mode...
Page 297 GD32F1x0 User Manual When channel 1 is configured in input mode, this flag is set by hardware when a capture event occurs while CH1IF flag has already been set. This flag is cleared by software. 0: No overcapture interrupt occurred 1: Overcapture interrupt occurred Reserved Must be kept at reset value.
Page 298 GD32F1x0 User Manual...
Page 299 GD32F1x0 User Manual long as the counter is larger than TIMERx_CHCC1 else low. When configured in PWM mode, the OCREF level changes only when the output compare mode switches from “frozen” mode to “PWM” mode or when the result of the comparison changes.
Page 300 GD32F1x0 User Manual 0011: f , N=8 SAMP PCLK 0100: f /2, N=6 SAMP 0101: f /2, N=8 SAMP 0110: f /4, N=6 SAMP 0111: f /4, N=8 SAMP 1000: f /8, N=6 SAMP 1001: f /8, N=8 SAMP 1010: f /16, N=5 SAMP 1011: f...
Page 301 GD32F1x0 User Manual 15:4 Reserved Must be kept at reset value CH1NP Channel 1 complementary output polarity When channel 1 is configured in output mode, this bit specifies the complementary output signal polarity. 0: Channel 1 active high 1: Channel 1 active low Reserved Must be kept at reset value CH1P...
Page 302 GD32F1x0 User Manual PSC[15:0] Bits Fields Descriptions 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 303 GD32F1x0 User Manual TIMERx channel input remap register(TIMERx_RMP) Address offset: 0x50 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved CH1RMP[1:0] Bits Fields Descriptions 15:2 Reserved Must be kept at reset value CH1RMP[1:0] Channel 1 input remap 00: Channel 1 input is connected to GPIO(TIMER14_CH1) 01: Channel 1 input is connected to the RTCCLK 10: Channel 1 input is connected to HSE/32 clock...
Page 304 GD32F1x0 User Manual 9.5. General timer (TIMER15) 9.5.1. Introduction The general timer, known as TIMER15, may be used for a variety of purposes. It consists of one 16-bit up-counter; two 16-bit capture/compare registers (TIMERx_CHCC), one 16-bit counter auto reload register (TIMERx_CARL) and several control registers. They can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output.
Page 305: Figure 9-100. Gereral Timer Block Diagram (Timer15)
GD32F1x0 User Manual Figure 9-100. Gereral timer block diagram (TIMER15) TM15_CK Trigger Controller TRG_OUTPUT ITR0 ITR1 Reset, Enable, Up/Down, Count ITR2 Mode Slave Controller ITR3 Prescaler AutoReload TI1F_ED Register Counter Repeat TI1FP1 Register TI2FP1 Repetition counter Capture Register CH1_N Output Input Filter Edge Detector Prescaler...
Page 306 GD32F1x0 User Manual Figure 9-101. Counter timing diagram with prescaler division change from 1 to 2 PCLK CNT_CLK CNT_REG Reload Pulse Figure 9-102. Counter timing diagram with prescaler division change from 1 to 4 PCLK CNT_CLK CNT_REG FA FB FC Reload Pulse modify PSC Vaule Prescaler CR...
Page 307 GD32F1x0 User Manual is set, the update eventis generated after the number of overflow. Else the update event is generated at each counter overflow. When the update event is set by the UPG bit in the TIMER1_EVG register, the counter value will be initialized to 0 and generates an update event.
Page 308 GD32F1x0 User Manual Figure 9-104. Counter timing diagram, internal clock divided by 2 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-105. Counter timing diagram, internal clock divided by 4 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF)
Page 309 GD32F1x0 User Manual Figure 9-106. Counter timing diagram, internal clock divided by N Figure 9-107. Counter timing diagram, update event when ARSE=0 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Auto-reload register modify CARL Vaule...
Page 310 GD32F1x0 User Manual Figure 9-108. Counter timing diagram, update event when ARSE=1 PCLK CNT_CLK CNT_REG overflow Counter Repetition Counter Repetition is used to generator update event or updates the timer registers only after a given number (N+1) of cycles of the counter, where N is CREP in TIMERx_CREP register. The repetition counter is decremented at each counter overflow in up-counting mode, at each counter underflow in down-counting mode or at each counter overflow and at each counter underflow in center-aligned mode.
Page 311 GD32F1x0 User Manual Clock selection The following describes the Timer Module clock controller which determines the clock source of the internal prescaler counter.  Internal timer clock PCLK The default internal clock source is the APB2 clock CK_APB2 used to drive the counter prescaler when the slave mode is disabled.
Page 312 GD32F1x0 User Manual The counter prescaler can count during each rising or falling edge of the ITI signal. This mode can be selected by setting the SMC field to 0x6 in the TIMERx_SMC register;here the counter will act as an event counter. The input event, known as ITI here, can be selected by setting the TRGS field.
Page 313 GD32F1x0 User Manual When used in the input capture mode, the counter value is captured into the TIMERx_CHCCx shadow register first and then transferred into the TIMERx_CHCCx preload register when the capture event occurs. When used in the compare match output mode, the contents of the TIMER1_CHCCx preload register is copied into the associated shadow register;...
Page 314 GD32F1x0 User Manual Figure 9-114. Output stage of capture/compare channel (channel 2) Input Capture Mode When the channel is used as a capture input, the counter value is captured into the Channel Capture/Compare Register (TIMERx_CHCCx) when an effective input signal transition occurs.
Page 315 GD32F1x0 User Manual Output Compare Mode/PWM Mode When the channel is used as a output mode by setting the CCxM in the the channel control register (TIMERx_CHCTLRx) to 00, the channel outputs waveform according to the CHxOM bits in the the the channel control register (TIMERx_CHCTLRx), and the comparision between the counter and TIMERx_CHCCx registers.
Page 316 GD32F1x0 User Manual Figure 9-116. Output compare PWM mode1 on OC1, upcounting mode 0039 003A 003B 003A Match detected on CHCC1 Interrupt generated if enabled Figure 9-117. Output compare PWM mode1 on OC1, center-aligned counting mode CNT_REG 0039 0039 003A 003B 0100 00FF...
Page 317 GD32F1x0 User Manual setting the CHxOM field to 0x04/0x05. Here the output can be forced to an inactive/active level irrespective of the comparison condition between the counter and the TIMERx_CHCCx values. The OCxREF signal can be forced to 0 when the ETIF signal is derived from the external TIMERx_ ETI pin and when it is set to a high level by setting the CHxOCE bit to 1 in the TIMERx_CHCTLR1 register.
Page 318 GD32F1x0 User Manual Figure 9-120. Dead-time waveforms with delay greater than the positive pulse Break function In this function, the output OCx and OCxN are controlled by the POE, IOS and ROS bits in the TIMERx_BKDT register, ISOx and ISOxN bits in the TIMERx_CTLR2 register and cannot be set both to active level when break occurs.
Page 319 GD32F1x0 User Manual level） Break_In OCxREF OCxN not implemented CCxP=0,ISOx=1 OCxN not implemented CCxP=0,ISOx=0 OCxN not implemented CCxP=1,ISOx=1 OCxN not implemented CCxP=0,ISOx=1 OCxN delay delay delay OCxE=1, CCxP=0,ISOx=0,CCxNE=1,CCxNP=0,ISOxN=1 OCxN delay delay delay OCxE=1, CCxP=0,ISOx=1,CCxNE=1,CCxNP=1,ISOxN=1 OCxN OCxE=1, CCxP=0,ISOx=0,CCxNE=0,CCxNP=0,ISOxN=1 OCxN OCxE=1, CCxP=0,ISOx=1,CCxNE=0,CCxNP=0,ISOxN=0 OCxN OCxE=1, CCxP=0,CCxNE=0,CCxNP=0,ISOx=0,ISOxN=0 or ISOx=0,ISOxN=1 Single Pulse Mode...
Page 320 GD32F1x0 User Manual counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHCCx value. In order to reduce the delay to a minimum value, the user can set the CHxOEF bit in each TIMERx_CHCTLR1 register. After a trigger rising edge occurs in the single pulse mode, the OCxREF signal will immediately be forced to the state which the OCxREF signal will change to, as the compare match event occurs without taking the comparison result into account.
Page 321 GD32F1x0 User Manual bit UPDIS is set to 1 or not. If UPDIS is set to 1 to disable the update event to occur, there will no update event will be generated, however the counter and prescaler are still reinitialized when the TI1 rising edge occurs.
Page 322 GD32F1x0 User Manual Figure 9-125. Control circuit in trigger mode CNT_CLK CNT_REG 5A 5B TRGIF Timer Interconnection The timers can be internally connected together for timer chaining or synchronization. This can be implemented by configuring one timer to operate in the Master mode while configuring another timer to be in the Slave mode.
Page 323 GD32F1x0 User Manual as follow: 1. Configure Timer2 in master mode and select its Update Event (UPE) as trigger output (MMC=010 in the TIMER2_CTLR2 register). Then timer2 driver a periodic signal on each counter overflow. 2. Configure the Timer2 period (TIMER2_CARL registers). 3.
Page 324 GD32F1x0 User Manual 9. Configure Timer15 in trigger mode (SMC=110 in TIMER15_SMC register). 10. Start Timer2 by writing ‘1 in the CEN bit (TIMER2_CTLR1 register). Figure 9-128. Triggering timer15 with update of timer2 PCLK TIMER2_UPE TIMER2_CNT_REG TIMER15_TRGIF TIMER15_EN TIMER15_CNT_REG  Enable timer15 count with timer2’s enable/OC1 Ref.
Page 325 GD32F1x0 User Manual 7. Configure Timer2 in master mode and Output Compare 1 Reference (OC1REF) signal as trigger output (MMC=100 in the TIMER2_CTLR2 register). 8. Configure the Timer 2 OC1REF waveform (TIMER2_CHCTLR1 register). 9. Configure Timer15 to get the input trigger from Timer 2 (TRGS=001 in the TIMER1_SMC register).
Page 326 GD32F1x0 User Manual Figure 9-131. Triggering Timer15 and Timer2 with Timer2’s TI1 input PCLK TIMER2_TI1 TIMER2_TRGIF TIMER2_EN TIMER2_CK TIMER2_CNT_REG TIMER15_TRGIF TIMER15_EN TIMER15_CK TIMER15_CNT_REG Timer debug mode When the Cortex™-M3 halted, and the DBG_TIMERx_STOP configuration bit in MCUDBG module set to 1, the TIMERx counter stops.
Page 327 CDIV[1:0] Clock division The CDIV bits can be configured by software to specify division ratio between the timer clock (PCLK) and the dead-time and sampling clock (DTS), which is used by the dead-time generators and the digital filters. 00: f PCLK 01: f PCLK...
Page 328 GD32F1x0 User Manual 0: update event enable. The update event is generate and the buffered registers are loaded with their preloaded values when one of the following events occurs: – The UPG bit is set – The counter generates an overflow or underflow event –...
Page 329 GD32F1x0 User Manual slave timers for synchronization function. 000: Reset. When the UPG bit in the TIMERx_EVG register is set or a reset is generated by the slave mode controller, a TRGO pulse occurs. And in the latter case, the signal on TRGO is delayed compared to the actual reset. 001: Enable.
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Page 331 GD32F1x0 User Manual cannot be disabled by the slave mode controller. 111: External Clock Mode 1.The counter counts on the rising edges of the selected trigger. Because TI1F_ED outputs 1 pulse for each transition on TI1F, and the pause mode checks the level of the trigger signal, when TI1F_ED is selected as the trigger input, the pause mode must not be used.
Page 332 GD32F1x0 User Manual 1: Channel control update interrupt enabled Reserved Must be kept at reset value. CH2IE Channel 2 interrupt enable 0: Channel 2 interrupt disabled 1: Channel 2 interrupt enabled CH1IE Channel 1 interrupt enable 0: Channel 1 interrupt disabled 1: Channel 1 interrupt enabled UPIE Update interrupt enable...
Page 333 GD32F1x0 User Manual This flag is set by hardware on trigger event and cleared by software. When the slave mode controller is enabled in all modes but pause mode, an active edge on TRGI input generates a trigger event. When the slave mode controller is enabled in pause mode both edges on TRGI input generates a trigger event.
Page 334 GD32F1x0 User Manual can occur if enabled. 0: No generate a break event 1: Generate a break event TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STR register is set, related interrupt or DMA transfer can occur if enabled.
Page 335 GD32F1x0 User Manual CH2OM[2:0] CH1OM[2:0] CH1OSE CH2M[1:0] CH1M[1:0] CH2ICF[3:0] CH2ICP[1:0] CH1ICF[3:0] CH1ICP[1:0] Output compare mode: Bits Fields Descriptions CH2OCE Channel 2 output compare clear enable Refer to CH1OCE description 14:12 CH2OM[2:0] Channel 2 output compare mode Refer to CH1OM description CH2OSE Channel 2 output compare shadow enable Refer to CH1OSE description...
Page 336 GD32F1x0 User Manual compare register TIMERx_CHCC1. 100: Force low. OC1REF is forced low level. 101: Force high. OC1REF is forced high level. 110: PWM mode 1. When counting up, OC1REF is high as long as the counter is smaller than TIMER1_CHCC1 else low. When counting down, OC1REF is low as long as the counter is larger than TIMERx_CHCC1 else high.
Page 337 GD32F1x0 User Manual Input capture mode: Bits Fields Descriptions 15:12 CH2ICF[3:0] Channel 2 input capture filter control Refer to CH1ICF description 11:10 CH2ICP[1:0] Channel 2 input capture prescaler Refer to CH1ICP description CH2M[1:0] Channel 2 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is OFF (CH2E bit in TIMERx_CHE register is reset).
Page 338 GD32F1x0 User Manual 10: Capture is done every 4channel input edges 11: Capture is done every 8 channel input edges CH1M[1:0] Channel 1 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is OFF (CH1E bit in TIMERx_CHE register is reset).
Page 340 GD32F1x0 User Manual Bits Fields Descriptions 15:0 PSC[15:0] Prescaler value of the counter clock The PSC clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 341 GD32F1x0 User Manual This register can be accessed by half-word(16-bit) or word(32-bit) CHCC1[15:0] Bits Fields Descriptions 15:0 CHCC1[15:0] Capture or compare value of channel1 When channel1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel1 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 342 GD32F1x0 User Manual This bit s set by software or automatically by hardware depending on the OAE bit. It is cleared asynchronously by hardware assoon as the break input is active. When a channel is configured in output mode, setting this bit enables the channel outputs (OC and OCN) if the corresponding enable bits (CHxE, CHxNE in TIMERx_CHE register) have been set.
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Page 344 GD32F1x0 User Manual TIMERx DMA transfer register (TIMERx_DTRSF) Address offset: 0x4C Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) DTRSF[15:0] Bits Fields Descriptions 15:0 DTRSF[15:0] DMA transfer When a read or write operation is assigned to this register, the register located at the address range (DBAR + burst counter) x 4 from TIMERx_CTLR1 will be accessed.
Page 345 GD32F1x0 User Manual 9.6. General timer (TIMER16/TIMER17) 9.6.1. Introduction The general timer, known as TIMER16/TIMER17, may be used for a variety of purposes. It consists of one 16-bit up-counter; two 16-bit capture/compare registers (TIMERx_CHCC), one 16-bit counter auto reload register (TIMER1_CARL) and several control registers. They can be used for a variety of purposes including general timer, input signal pulse width measurement or output waveform generation such as single pulse generation or PWM output.
Page 346 GD32F1x0 User Manual Figure 9-132. Gereral timer block diagram (TIMER16/17) TM15_CK Counter Control Prescaler AutoReload Register Counter Repeat Register Repetition counter Capture Register Output Input Filter Edge Detector Prescaler Compare 1 Control CH1_N Register BKIN Polarity Selection Prescaler counter The prescaler can divide the timer clock (PCLK) to the counter clock (CNT_CLK) by any factor between 1 and 65536.
Page 347 GD32F1x0 User Manual Figure 9-134. Counter timing diagram with prescaler division change from 1 to 4 PCLK CNT_CLK CNT_REG FA FB FC Reload Pulse modify PSC Vaule Prescaler CR Prescaler BUF Prescaler CNT Upcounting mode In this mode the counter counts continuously from 0 to the counter-reload value, which is defined in the TIMERx_CARL register, in a count-up direction.
Page 348 GD32F1x0 User Manual Figure 9-135. Counter timing diagram, internal clock divided by 1 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-136. Counter timing diagram, internal clock divided by 2 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF)
Page 349 GD32F1x0 User Manual Figure 9-137. Counter timing diagram, internal clock divided by 4 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Figure 9-138. Counter timing diagram, internal clock divided by N...
Page 350 GD32F1x0 User Manual Figure 9-139. Counter timing diagram, update event when ARSE=0 PCLK CNT_CLK CNT_REG overflow Update event (UPE) Update interrupt flag (UPIF) Auto-reload register modify CARL Vaule Figure 9-140. Counter timing diagram, update event when ARSE=1 PCLK CNT_CLK CNT_REG overflow...
Page 351 GD32F1x0 User Manual Counter Repetition Counter Repetition is used to generator update event or updates the timer registers only after a given number (N+1) of cycles of the counter, where N is CREP in TIMERx_CREP register. The repetition counter is decremented at each counter overflow in up-counting mode, at each counter underflow in down-counting mode or at each counter overflow and at each counter underflow in center-aligned mode.
Page 352 GD32F1x0 User Manual Figure 9-142. Control circuit in normal mode, internal clock divided by 1 Capture/compare channels The TIMER16/TIMER17 has one independent channel which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage.
Page 353 GD32F1x0 User Manual Figure 9-143. Capture/compare channel (example: channel 1 input stage) TI1F_Rising TI1FP1 filter Edge Detector downcounter TI1F_Falling TI2FP1 divider /1, /2, /4, /8 CH1ICF[3:0] CH1P/ CH1NP CHCTLR1 CH1ICP[1:0] CH1M[ 1:0 ] CHCTLR1 CHCTLR1  Channel controller The GPTM has one independent channels which can be used as capture inputs or compare match outputs.
Page 354: Maybe Used To Implement Input Capture Mode
GD32F1x0 User Manual  Output stage TIMER16/TIMER17 has one channels for compare match, single pulse or PWM output function. Figure 9-145. Output stage of capture/compare channel (channel 1) CH1E CH1M[ 1:0 ] CH1P Output enable circuit CNT>CHCC1 Dead-time Output mode controller generator CNT=CHCC1 Output...
Page 355 GD32F1x0 User Manual TIMERx_CHx pins (TIx). For example, PWM signal connect to TI1 input. Select channel 1 capture signal to TI1 by setting CH1M to 01 in the channel control register (TIMERx_CHCTLR1) and set capture on rising edge. Select channel 2 capture signal to TI1 by setting CH2M to 10 in the channel control register (TIMERx_CHCTLR1) and set capture on falling edge.
Page 356 GD32F1x0 User Manual Figure 9-147. Output compare PWM mode1 on OC1, upcounting mode 0039 003A 003B 003A Match detected on CHCC1 Interrupt generated if enabled Figure 9-148. Output compare PWM mode1 on OC1, center-aligned counting mode CNT_REG 0039 0039 003A 003B 0100 00FF...
Page 357 GD32F1x0 User Manual setting the CHxOM field to 0x04/0x05. Here the output can be forced to an inactive/active level irrespective of the comparison condition between the counter and the TIMERx_CHCCx values. The OCxREF signal can be forced to 0 when the ETIF signal is derived from the external TIMERx_ ETI pin and when it is set to a high level by setting the CHxOCE bit to 1 in the TIMERx_CHCTLR1 register.
Page 358 GD32F1x0 User Manual Figure 9-151. Dead-time waveforms with delay greater than the positive pulse Break function In this function, the output OCx and OCxN are controlled by the POE, IOS and ROS bits in the TIMER1_BKDT register, ISOx and ISOxN bits in the TIMER1_CTLR2 register and cannot be set both to active level when break occurs.
Page 359 GD32F1x0 User Manual Figure 9-152. Output behavior in response to a break（The break input is acting on high level） Break_In OCxREF OCxN not implemented CCxP=0,ISOx=1 OCxN not implemented CCxP=0,ISOx=0 OCxN not implemented CCxP=1,ISOx=1 OCxN not implemented CCxP=0,ISOx=1 OCxN delay delay delay OCxE=1, CCxP=0,ISOx=0,CCxNE=1,CCxNP=0,ISOxN=1 OCxN...
Page 360 GD32F1x0 User Manual In the Single Pulse mode, the trigger active edge which sets the CEN bit to 1 will enable the counter. However, there exist several clock delays to perform the comparison result between the counter value and the TIMERx_CHCCx value. In order to reduce the delay to a minimum value, the user can set the CHxOEF bit in each TIMERx_CHCTLR1 register.
Page 361 GD32F1x0 User Manual 9.6.4. TIMER16/TIMER17 registers TIMERx control register 1 (TIMERx_CTLR1) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved CDIV[1:0] ARSE Reserved UPDIS Bits Fields Descriptions 15:10 Reserved Must be kept at reset value CDIV[1:0] Clock division The CDIV bits can be configured by software to specify division ratio between the...
Page 362 GD32F1x0 User Manual 0: Update event enable. The update event is generate and the buffered registers are loaded with their preloaded values when one of the following events occurs: – The UPG bit is set – The counter generates an overflow or underflow event –...
Page 363 GD32F1x0 User Manual When the Capture/compare control shadow shadow registers (for CHxE, CHxNE and CHxOM bits) are enabled (CCSE=1), this bit control when these shadow registers update. 0: The shadow registers update by when CCUG bit is set 1: The shadow registers update by when CCUG bit is set or an rising edge of TRGI occurs When a channel does not have a complementary output, this bit has no effect.
Page 364 GD32F1x0 User Manual Reserved Must be kept at reset value CH1IE Channel 1 interrupt enable 0: Channel 1 interrupt disabled 1: Channel 1 interrupt enabled UPIE Update interrupt enable 0: Update interrupt disabled 1: Update interrupt enabled TIMERx status register (TIMERx_STR) Address offset: 0x10 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit)
Page 365 GD32F1x0 User Manual 1: Channel control update interrupt occurred Reserved Must be kept at reset value. CH1IF Channel 1 interrupt flag This flag is set by hardware and cleared by software. When channel 1 is in input mode, this flag is set when a capture event occurs. When channel 1 is in output mode, this flag is set when a compare event occurs.
Page 366 GD32F1x0 User Manual CH1G Channel 1 capture or compare event generation This bit is set by software in order to generate a capture or compare event in channel 1, it is automatically cleared by hardware. When this bit is set, the CC1IF flag is set, the corresponding interrupt or DMA request is sent if enabled.
Page 367 GD32F1x0 User Manual output compare register TIMERx_CHCC1. 010: Set low on match. OC1REF signal is forced low when the counter matches the c output compare register TIMERx_CHCC1. 011: Toggle on match. OC1REF toggles when the counter matches the c output compare register TIMERx_CHCC1.
Page 368 GD32F1x0 User Manual 10: Channel 1 is configured as input, IC1 is mapped on TI2 11: Channel 1 is configured as input, IC1 is mapped on TRC. This mode is working only if an internal trigger input is selected through TRGS bits in TIMERx_SMC register.
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Page 370 GD32F1x0 User Manual 1: Channel 1 enabled TIMERx counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) CNT[15:0] Bits Fields Descriptions 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter.
Page 371 GD32F1x0 User Manual 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. TIMERx counter repetition register (TIMERx_CREP) Address offset: 0x30 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved CREP[7:0] Bits Fields...
Page 372 GD32F1x0 User Manual This register can be accessed by half-word(16-bit) or word(32-bit) BRKP BRKE LK[1:0] DT[7:0]...
Page 373 GD32F1x0 User Manual 1: When POE bit is reset, he channel output signals (OC/OCN)are enabled, with relationship to CHxE/CHxNE bits in TIMERx_CHE register. This bit cannot be modified when LK[1:0] bit-filed in TIMERx_BKDT register is 10 or LK[1:0] Lock control This bit-filed specifies the write protection property of registers.
Page 374 GD32F1x0 User Manual field specifies the number of transfers. Reserved Must be kept at reset value DBAR[4:0] DMA access base address When register access are done through the TIMERx_DTRSF address, this bit-field specifies the offset of the starting address from the TIMER1_CTLR1 register. TIMERx DMA transfer register (TIMERx_DTRSF) Address offset: 0x4C Reset value: 0x0000...
Page 375 GD32F1x0 User Manual OUTSEL The output value selection. This bit-field set and reset by software. 1: If POE and IOS is 0, the output disabled 0: No effect Infrared ray port (IFRR) 10.1. Introduction Infrared ray port (IFRR) is used to control infrared light LED, and send out infrared data to implement infrared ray remote control.
Page 376 GD32F1x0 User Manual Figure 10-1. IFRR output timechart 1 IFRR_OUT has one APB clock delay from TIMER17_CH1. Note: Figure 10-2. IFRR output timechart 2 Carrier(TIMER16_CH1)’s duty cycle can be changed, and IFRR_OUT has inverted Note: relationship with TIMER17_CH1 when TIMER16_CH1 is high. Figure 10-3.
Page 377 GD32F1x0 User Manual Watchdog (WDG) 11.1. Independent watchdog (IWDG) 11.1.1. Introduction The Watchdog (WDG) Timer is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. The GD32F1x0 has two watchdog peripherals, Independent watchdog and Window watchdog. They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 378 GD32F1x0 User Manual Figure 11-1. Independent watchdog block diagram Status:PUD Reset Prescaler 12-Bit Down /4/8…256 Counter Reloa Control Reload Status: RUD register register The independent watchdog is enabled by writing the value 0xCCCC in the control register (IWDG_CTLR), and the counter starts counting down. When the counter reaches the value 0x000, a reset is generated.
Page 379: Table 11-1. Min/Max Iwdg Timeout Period At 40 Khz (Lsi)
GD32F1x0 User Manual Table 11-1. Min/max IWDG timeout period at 40 kHz (LSI) Min timeout (ms) Max timeout (ms) Prescaler PS[2:0] RL[11:0]= RL[11:0]= divider bits 0x000 0xFFF 409.6 819.2 1/16 1638.4 1/32 3276.8 1/64 6553.6 1/128 13107.2 1/256 110 or 111 26214.4 The IWDG timeout can be more accurately by calibrating the LSI.
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Page 381 GD32F1x0 User Manual bit is reset before changing the reload value. However, after updating the reload value it is not necessary to wait until RUD is reset before continuing code execution except in case of low-power mode entry. Status register (IWDG_STR) Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access...
Page 382 GD32F1x0 User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 WND[11:0] Watchdog counter window value. These bits are used to contain the high limit of the window value to be compared to the downcounter. A reset will occur if the reload operation is performed while the counter is greater than the value stored in this register.
Page 383 GD32F1x0 User Manual 11.2. Window watchdog (WWDG) 11.2.1. Introduction The window watchdog (WWDG) is used to detect system failures due to software malfunctions. After the window watchdog start, the 7-bit downcounter reduce progressively. The watchdog causes a reset when the counter reached 0x3F (the T6 bit becomes cleared). The watchdog also cause a reset if the counter is refreshed before the counter reached the window register value.
Page 384 GD32F1x0 User Manual The software should reload the downcounter by writing the WWDG_CTLR register to prevent an MCU reset, and the WWDG_CTLR register should be written before the downcounter decreases to 0x3F and after the downcounter is lesser than the window value. The reload value must be between 0xFF and 0xC0.
Page 385: Table 11-2. Min-Max Timeout Value At 36 Mhz (Fpclk1)
GD32F1x0 User Manual : APB1 clock period measured in ms PCLK1 Refer to the table below for the minimum and maximum values of the tWWDG. Table 11-2. Min-max timeout value at 36 MHz (fPCLK1) Prescaler Min timeout value Max timeout value PS[1:0] divider CNT[6:0] =0x40...
Page 386 GD32F1x0 User Manual This register can be accessed by half-word (16-bit) or word (32-bit) Reserved...
Page 387 GD32F1x0 User Manual Analog to Digital converter (ADC) 12.1. Introduction The 12 bit ADC is an analog-to-digital converter using successive approximation approach. It has 19 multiplexed channels which are used to measure the signals from 16 external and 3 internal signal sources. Analog watchdog allows the application to detect whether the input voltage exceeds the user's set of high and low threshold.
Page 388 GD32F1x0 User Manual  High performance  12-bit, 10-bit, 8-bit, or 6-bit configurable resolution  ADC conversion time: 0.5μs for 12-bit resolution (2MS/s), about 0.43μs conversion time for 10-bit resolution, about 0.286μs for 6-bit resolution. Faster conversion time can be obtained by lowering the resolution ...
Page 389 GD32F1x0 User Manual  Oversampling ratio adjustable from 2 to 256x  Programmable data shift up to 8-bits  ≤V ≤V ADC input range: V 12.3. Function description Figure 12-1 and Figure 12-2 show the ADC block diagram. Figure 12-1. ADC module block diagram of GD32F130xx and GD32F150xx devices DMA request Trig select Trig select...
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Page 391 GD32F1x0 User Manual ≤ ≤ 5.5 V Input, analog supply Ground for analog power supply equal to ground ADCx_IN[15:0] Analog signals Up to 16 analog channels 1. V and V have to be connected to V and V , respectively. 12.3.1.
Page 392 GD32F1x0 User Manual groups: a regular channel group and an inserted channel group. In the regular group, a sequence of up to 16 conversions can be organized in a specific sequence. The ADC_RSQ1~ADC_RSQ3 registers specify the selected channels of the regular group.
Page 393 GD32F1x0 User Manual enabled, the EOC or EOIC will be set after every circle of the regular or inserted channel group. An interrupt will be generated if the EOCIE or EOICIE bit is set. Figure 12-4. Continuous conversion mode, scan disable CH11 CH16 CH12...
Page 394 GD32F1x0 User Manual Figure 12-6. Scan conversion mode CH11 CH16 CH12 CH17 Regular trigger One circle of regular group, RL=8 CH10 CH10 Sample Inserted trigger Convert EOIC One circle of inserted group, IL=4 Discontinuous mode For regular channel group, the discontinuous conversion mode will be enabled when DISRC bit in the ADC_CTLR1 register is set.
Page 395 GD32F1x0 User Manual Figure 12-7. Discontinuous conversion mode CH11 CH16 CH12 CH17 · · · Regular trigger One circle of regular group, RL=8, DISNUM=3'b010 · · · CH10 CH10 Sample Inserted trigger Convert EOIC One circle of inserted group, IL=3 12.3.5.
Page 396: Table 12-4. External Trigger For Regular Channels Of Adc
GD32F1x0 User Manual resumed from the last aborted conversion. 12.3.7. Data alignment The alignment of data stored after conversion can be specified by DAL bit in the ADC_CTLR2 register. After decreased by the user-defined offset written in the ADC_ICOSx registers, the inserted group data value may be a negative value.
Page 397: Table 12-5. External Trigger For Inserted Channels Of Adc
GD32F1x0 User Manual ETSRC[2:0] Trigger Source Trigger Type TIMER15_CH1 EXTI_11 External signal SWRCST Software trigger Table 12-5. External trigger for inserted channels of ADC ETSIC[2:0] Trigger Source Trigger Type TIMER1_TRGO TIMER1_CH4 TIMER2_TRGO Internal on-chip signal TIMER2_CH1 TIMER3_CH4 TIMER15_TRGO EXTI_15 External signal SWICST Software trigger 12.3.10.
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Page 399: Table 12-6. T Sar Timings Depending On Resolution
GD32F1x0 User Manual Table 12-6. t timings depending on resolution (ADC (ADC (ADC SMPL DRES[1:0] (ns) at (ns) at clock clock clock bits =28MHz =28MHz cycles) cycles) cycles) 12.5 446ns 500ns 10.5 375ns 429ns 304ns 357ns 232ns 286ns 12.3.15. Oversampling for GD32F170xx and GD32F190xx devices The oversampling unit, which is enabled by OVSE bit in the ADC_OVSCR register, provides higher data resolution at the cost of lower output data rate.
Page 400 GD32F1x0 User Manual Figure 12-9. 20-bit to 16-bit result truncation Raw 20-bit data Shifting Truncation and rounding Note: If the intermediate result after the shifting exceeds 16 bits, the upper bits of the result are simply truncated. 12-10 The Figure shows a numerical example of the processing, from a raw 20-bit accumulated data to the final 16-bit result.
Page 401: Table 12-7. Maximum Output Results Vs N And M. Grayed Values Indicates Truncation
GD32F1x0 User Manual The Table 12-7 below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF. Table 12-7. Maximum output results vs N and M. Grayed values indicates truncation Over 1-bit 2-bit 3-bit...
Page 402 GD32F1x0 User Manual 12.4. ADC registers 12.4.1. ADC status register (ADC_STR) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved STRC STIC EOIC rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:5 Reserved Must be kept at reset value...
Page 404 GD32F1x0 User Manual AWSSM When in scan mode, analog watchdog is effective on a single channel 0: Analog watchdog is effective on all channels 1: Analog watchdog is effective on a single channel Scan mode 0: scan mode enable 1: scan mode disable EOICIE Interrupt enable for EOIC 0: EOIC interrupt disable...
Page 405 GD32F1x0 User Manual 31:26 Reserved Must be kept at reset value 25:24 DRES[1:0] ADC resolution 00: 12bit; 01: 10bit; 10: 8bit; 11: 6bit AWREN Analog watchdog on regular channel enable 0: Analog watchdog regular channel disable 1: Analog watchdog regular channel enable AWIEN Analog watchdog on inserted channel enable 0: Analog watchdog inserted channel disable...
Page 406 GD32F1x0 User Manual 0: EOC interrupt disable 1: EOC interrupt enable AWCS[4:0] Analog watchdog channel select 00000: ADC channel0 00001: ADC channel1 00010: ADC channel2 …… 01111: ADC channel15 1xx00: ADC channel16 1xx01: ADC channel17 1xx1x: ADC channel18 “x” means 0 or 1 12.4.3.
Page 407 GD32F1x0 User Manual It is set by software and cleared by software or by hardware after the conversion starts. ETERC External trigger enable for regular channel 0: External trigger for regular channel disable 1: External trigger for regular channel enable 19:17 ETSRC[2:0] External trigger select for regular channel...
Page 408 GD32F1x0 User Manual 1: Initialize calibration register start ADC calibration 0: Calibration done 1: Calibration start Continuous mode 0: Continuous mode disable 1: Continuous mode enable ADCON ADC ON. The ADC will be wake up when this bit is changed from low to high. When this bit is high and “1”...
Page 410 GD32F1x0 User Manual 001: 7.5 cycles 010: 13.5 cycles 011: 28.5 cycles 100: 41.5 cycles 101: 55.5 cycles 110: 71.5 cycles 111: 239.5 cycles 12.4.6. ADC inserted channel data offset register x (ADC_ICOSx) (x=1..4) Address offset: 0x14-0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved 79 Tm1 0 0 1 345.55 477.79 Tm0 31 477.79 Tm0 g[(8)] TJETQq275.95 472.51 28...
Page 411 GD32F1x0 User Manual 31:12 Reserved Must be kept at reset value 11:0 AWHT[11:0] Analog watchdog high threshold These bits define the high threshold for the analog watchdog. 12.4.8. ADC watchdog low threshold register (ADC_AWLT) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved...
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Page 413 GD32F1x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved IL[1:0] ISQ4[4:1] ISQ4[0] ISQ3[4:0] ISQ2[4:0] ISQ1[4:0] Bits Fields Descriptions 31:22 Reserved Must be kept at reset value 21:20 IL[1:0] Inserted channel group length. The total number of conversion in regular group equals to IL[1:0]+1.
Page 414 GD32F1x0 User Manual 12.4.14. ADC regular data register (ADC_RDTR) Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved RDTR[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 RDTR[15:0] Regular channel data These bits contain the conversion result from regular channel, which is read only.
Page 415 GD32F1x0 User Manual OVSS[3:0] Oversampling shift This bit is set and cleared by software. 0000: No shift 0001: Shift 1-bit 0010: Shift 2-bits 0011: Shift 3-bits 0100: Shift 4-bits 0101: Shift 5-bits 0110: Shift 6-bits 0111: Shift 7-bits 1000: Shift 8-bits Other codes reserved Note: Software is allowed to write this bit only when ADCON =0 (which ensures that no conversion is ongoing).
Page 416 GD32F1x0 User Manual Digital-to-analog converter (DAC) 13.1. DAC Introduction The 12-bit DAC module is a voltage output digital-to-analog converter. The DAC can be configured in 8 or 12 bit mode and may be used in conjunction with the DMA controller. The input data of the DAC could be left-aligned or right-aligned.
Page 417: Table 13-1. Dac Pin
GD32F1x0 User Manual Figure 13-1 shows the block diagram of DAC and Table 13-1 gives the pin description. Figure 13-1. DAC block diagram DAC control register DTSELx[2:0] DBOFFx DDMA ENx DTENx SWTRx TIM6_TRGO TIM3_TRGO TIM15_TRGO TIM2_TRGO Buff EXTI_9 DAC_OUT Control logic 12-bit DHRx...
Page 418 GD32F1x0 User Manual output buffer; For GD32F170xx and GD32F190xx devices, there are two output buffers ) which can be used to reduce the impedance of output, so DAC can be directly connected to external loads without operational amplifier. By the DBOFFx bit in the DAC_CTLR register the DAC channel output buffer can be enabled and disabled.
Page 419 GD32F1x0 User Manual the DACx_yyDHR register are automatically transferred to the DACx_ODR register. However, when a hardware trigger is selected (DTENx bit in DAC_CTLR register is set), the transfer is performed after the corresponding trigger occurs. When the data from the DACx_yyDHR register is loaded into the DACx_ODR register, after the time tSETTLING, the analog output is valid, and the value of t is related to the SETTLING...
Page 420: Table 13-2. External Triggers Of Dac
GD32F1x0 User Manual SWTRx is reset by hardware. Table 13-2. External triggers of DAC DTSELx[2:0] Trigger Source Trigger Type TIM6_TRGO TIM3_TRGO reserved Internal on-chip signal TIM15_TRGO TIM2_TRGO reserved EXTI_9 External signal SWTRIG Software trigger 13.3.8. Dual DAC conversion for GD32F170xx and GD32F190xx devices When the two DACs work at the same time, for more effective utilization of bus bandwidth in applications, three dual registers can be used: DACD_R8DHR, DACD_R12DHR, DACD_L12DHR.
Page 421 GD32F1x0 User Manual  Load the dual DAC channel data to the required DACD_DHR register (DACD_R8DHR, DACD_R12DHR, DACD_L12DHR) In this mode, after one APB1 clock cycle, the value of the DHR1 and DHR2 registers is immediately transferred to DAC1_ODR and DAC2_ODR. Simultaneous trigger In this conversion mode, follow the steps below to set the DAC: ...
Page 422 GD32F1x0 User Manual 1: DAC1 DMA mode enabled 11:6 Reserved Must be kept at reset value DTSEL1[2:0] DAC1 trigger selection These bits are only used if bit DTEN1 = 1 and select the external event used to trigger DAC1. 000: Timer 6 TRGO event 001: Timer 3 TRGO event 010: Reserved 011: Timer15 TRGO event...
Page 423 GD32F1x0 User Manual DDMAUDRIE2 DAC2 DMA Underrun Interrupt enable 0: DAC2 DMA Underrun Interrupt disabled 1: DAC2 DMA Underrun Interrupt enabled DDMAEN2 DAC2 DMA enable 0: DAC2 DMA mode disabled 1: DAC2 DMA mode enabled 27:22 Reserved Must be kept at reset value 21:19 DTSEL2[2:0] DAC2 trigger selection...
Page 424 DBOFF1 DAC1 output buffer disable This bit is set and cleared by software to enable/disable DAC1 output buffer. 0: DAC1 output buffer enabled 1: DAC1 output buffer disabled DEN1 DAC1 enable This bit is set and cleared by software to enable/disable DAC1. 0: DAC1 disabled 1: DAC1 enabled 13.4.2.
Page 425 GD32F1x0 User Manual SWTR1 DAC1 software trigger, clear by hardware 0: Software trigger disabled 1: Software trigger enabled For GD32F170xx and GD32F190xx devices Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved SWTR2 SWTR1 Bits...
Page 426 GD32F1x0 User Manual These bits are written by software which specifies 12-bit data for DAC1. 13.4.4. DAC1 12-bit left-aligned data holding register (DAC1_L12DHR) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DHR[11:0] Reserved Bits Fields...
Page 427 GD32F1x0 User Manual 13.4.6. DAC2 12-bit right-aligned data holding register (DAC2_R12DHR) of GD32F170xx and GD32F190xx devices Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved DAC2_DHR[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value 11:0 DAC2_DHR[11:0] DAC2 12-bit right-aligned data...
Page 428 GD32F1x0 User Manual 13.4.8. DAC2 8-bit right-aligned data holding register (DAC2_R8DHR) of GD32F170xx and GD32F190xx devices Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved DAC2_DHR[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value DAC2_DHR[7:0] DAC2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC2.
Page 429 GD32F1x0 User Manual These bits are written by software which specifies 12-bit data for DAC1. 13.4.10. DAC dual mode 12-bit left-aligned data holding register (DACD_L12DHR) of GD32F170xx and GD32F190xx devices Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DAC2_DHR[11:0] Reserved DAC1_DHR[11:0]...
Page 430 GD32F1x0 User Manual 31:16 Reserved Must be kept at reset value 15:8 DAC2_DHR[7:0] DAC2 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC2. DAC1_DHR[7:0] DAC1 8-bit right-aligned data These bits are written by software which specifies 8-bit data for DAC1. 13.4.12.
Page 431 GD32F1x0 User Manual 31:12 Reserved Must be kept at reset value 11:0 DAC2_ODR [11:0]...
Page 432 GD32F1x0 User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value DDMA2UDR DAC2 DMA underrun flag This bit is set by hardware and cleared by software (by writing it to 1). 0: No DMA underrun error condition occurred 1: DMA underrun error condition occurred (the frequency of the current selected trigger that is driving DAC conversion is higher than the DMA service capability rate) 28:14...
Page 433 GD32F1x0 User Manual Inter-integrated circuit (I2C) interface 14.1. Introduction The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol at standard or fast speed as well as CRC calculation and checking, SMBus (system management bus) and PMBus (power management bus).
Page 434: Table 14-1. Definition Of I2C-Bus Terminology
GD32F1x0 User Manual Figure 14-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register Control Registers SMBA Timing and Control Logic Status Flags DMA/ Interrupts Table 14-1. Definition of I2C-bus terminology Term Description Transmitter...
Page 435 GD32F1x0 User Manual standard-mode and up to 400 kbit/s in the fast mode. Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be connected to the I2C-bus, the levels of the logical ‘0’ (LOW) and ‘1’ (HIGH) are not fixed and depend on the associated level of V 14.3.2.
Page 436 GD32F1x0 User Manual master with the longest LOW period. Masters with shorter LOW periods enter a HIGH wait- state during this time. Figure 14-4. Clock synchronization 14.3.5. Arbitration Arbitration, like synchronization, refers to a portion of the protocol required only if more than one master is used in the system.
Page 437 GD32F1x0 User Manual to the following command on I2C bus: transmitting or receiving desired data. Additionally, if General Call is enabled by software, an I2C slave always responses to a General Call Address (0x00). The I2C block support both 7-bit and 10-bit addresses. An I2C master always initiates or end a transfer using START or STOP condition and it’s also responsible for SCL clock generation.
Page 438 GD32F1x0 User Manual finished sending a STOP condition on I2C bus. Programming model in slave transmitting mode As it shows in figure below, software should follow these steps to operate I2C block in slave mode for transmitting some data to the I2C bus: First of all, software should enable I2C peripheral clock as well as configure clock related registers in I2C_CTLR2 to make sure correct I2C timing.
Page 439 GD32F1x0 User Manual Figure 14-8. Programming model for slave transmitting I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge Set ADDSEND Master generates repeated 2) Clear ADDSEND START condition Master sends header...
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Page 441 GD32F1x0 User Manual I2C operates in its default slave state and waits for START condition followed by address on I2C bus. Software set GENSTA bit requesting I2C to generate a START condition to I2C bus. After sending a START condition, the I2C hardware sets the SBSEND bit in I2C status register and enters master mode.
Page 442 GD32F1x0 User Manual Figure 14-10. Programming model for master transmitting I2C Line State Software Flow Hardware Action 1) Software initialization IDLE 2) Set GENSTA Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master...
Page 443 GD32F1x0 User Manual I2C operates in its default slave state and waits for START condition followed by address on I2C bus. Software set GENSTA bit requesting I2C to generate a START condition to I2C bus. After sending a START condition, the I2C hardware sets the SBSEND bit in I2C status register and enters master mode.
Page 444 GD32F1x0 User Manual Figure 14-11. Programming model for master receiving using Solution A Hardware I2C Line State Software Flow Action 1) Software initialization IDLE 2) Set GENSTA START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND...
Page 445 GD32F1x0 User Manual register and enters master mode. Now software should clear the SBSEND bit by reading I2C_STR1 and then writing a 7-bit address or header of a 10-bit address to I2C_DTR. I2C begins to send address or header to I2C bus as soon as SBSEND bit is cleared. If the address sent is a header of 10-bit address, the hardware sets ADD10SEND bit after sending header and software should clear the ADD10SEND bit by reading I2C_STR1 and writing 10-bit lower address to I2C_DTR.
Page 446 GD32F1x0 User Manual Figure 14-12. Programming model for master receiving using Solution B I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set GENSTA Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND...
Page 447 GD32F1x0 User Manual Programming model for DMA mode As is shown in Programming Model, each time TBE or RBNE is asserted, software should write or read a byte, this may cause CPU’s high overload. DMA can be used to process TBE and RBNE flag: each time TBE or RBNE is asserted.
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Page 449: Table 14-2. Event Status Flags
GD32F1x0 User Manual Table 14-2. Event status flags Event Flag Name Description SBSEND START condition sent (master) ADDSEND Address sent or received ADD10SEND Header of 10-bit address sent STPDET STOP condition detected Byte transmission completed I2C_DTR is empty when transmitting RBNE I2C_DTR is not empty when receiving Table 14-3.
Page 450 GD32F1x0 User Manual 1: Issue alert through SMBA pin PECTRANS PEC Transfer Software sets and clears this bit while hardware clears this bit when PEC is transferred or START/STOP condition detectedor I2CEN=0 0: Don’t transfer PEC value 1: Transfer PEC Position of ACK/PEC’s meaning POAP This bit is set and cleared by software and cleared by hardware when I2CEN=0...
Page 451 GD32F1x0 User Manual 1: ARP is enabled SMBSEL SMBusType Selection 0: Device 1: Host Reserved Must keep the reset value SMBEN SMBus/I2C mode switch 0: I2C mode 1: SMBus mode I2CEN I2C peripheral enable 0: I2C is disabled 1: I2C is enabled 14.4.2.
Page 452 GD32F1x0 User Manual Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled, means that interrupt will be generated when BE, LOSTARB, AE, RXORE, PECE, SMBTO or SMBALTS flag asserted. Reserved Must be kept the reset value I2CCLK[5:0] I2C Peripheral clock frequency I2CCLK[5:0] should be the frequency of input APB clock in MHz which is at least 2.
Page 453 GD32F1x0 User Manual Bits Fields Descriptions 15:8 Reserved Must be kept the reset value ADDRESS2[7:1] Second I2C address for the slave in Dual-Address mode DUADEN Dual-Address mode switch 0: Dual-Address mode disabled 1: Aual-Address mode enabled 14.4.5. I2C transfer buffer register (I2C_DTR) Address offset: 0x10 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit)
Page 454 GD32F1x0 User Manual 1: Timeout event occurs (SCL is low for 25 ms) Reserved Must keep the reset value PECE PEC error when receiving data This bit is set by hardware and cleared by writing 0. 0: Received PEC and calculated PEC match 1: Received PEC and calculated PEC don’t match, I2C will send NACK careless of ACKEN bit.
Page 455 GD32F1x0 User Manual Reserved Must be kept the reset value STPDET STOP condition detected in slave mode This bit is set by hardware and cleared by reading I2C_STR1 and then writing CTLR1 0: STOP condition not detected in slave mode 1: STOP condition detected in slave mode ADD10SEND Header of 10-bit address is sent in master mode...
Page 456 GD32F1x0 User Manual DUMODF Dual Flag in slave mode indicating which address is matched in Dual-Address mode This bit is cleared by hardware after a STOP or a START condition or I2CEN=0 0: OAR1 address matches 1: OAR2 address matches HSTSMB SMBus Host Header detected in slave mode This bit is cleared by hardware after a STOP or a START condition or I2CEN=0...
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Page 458 GD32F1x0 User Manual Reserved RFRIE RFFIE TFRIE TFFIE Reserved STOE SAME r_w0 r_w0 r_w0 r_w0 Bits Fields Descriptions Rxframe rise flag, cleared by software write 0 Rxframe fall flag, cleared by software write 0 Txframe rise flag, cleared by software write 0 Txframe fall flag, cleared by software write 0 11:10 Reserved...
Page 459 GD32F1x0 User Manual Serial peripheral interface/Inter-IC sound(SPI/I2S) 15.1. Introduction The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol data transmit and receive function in both master and slave mode. For GD32F130xx and GD32F150xx devices, the SPI Interface supports single wire configuration in both master and slave mode.
Page 460 GD32F1x0 User Manual  Full-duplex synchronous transfers on three lines  Simplex synchronous transfers on two lines  NSS work in software mode or hardware mode for both master and slave  SPI bus busy status flag  Transmission and reception flags with interrupt capability ...
Page 461 GD32F1x0 User Manual overrun error flag (RXORE)  DMA capability for both transmission and reception 15.3. SPI function description 15.3.1. Pin configuration (Single wire, default) The SPI is connected to external devices through 2-4 pins in different modes:  MISO: This pin is used to receive data in master mode (Master In) or transmit data in slave mode (Slave Out).
Page 462 GD32F1x0 User Manual Data is transferred from master to slave by MOSI line and transferred from slave to master by MISO line. The clock is created in master and transferred to slave by SCK. In hardware mode (SWNSSEN bit is cleared), the NSS is driven high in master mode or driven low in slave mode;...
Page 463 GD32F1x0 User Manual Figure 15-2. SPI data clock timing diagram SCKPH=0 SCKPL= 1 SCKPL= 0 MISO MOSI (SLAVE) Capture SCKPH=1 SCKPL= 1 SCKPL= 0 MISO MOSI (SLAVE) Capture Data frame format Data can be shifted out either MSB-first or LSB-first depending on the value of the LF bit in the SPI_CTLR1 Register.
Page 464 GD32F1x0 User Manual  MISO: This pin is used to transmit data in quad write mode and receive data in quad read mode.  IO2: This pin is used to transmit data in quad write mode and receive data in quad read mode.
Page 465 GD32F1x0 User Manual Program the NSS mode (SWNSSEN bit in the SPI_CTLR1 register). In hardware mode (SWNSSEN=0), the NSS pin must be connected to a low level signal during transmit sequence. In software mode (SWNSSEN=1), the SWNSS bit in the SPI_CTLR1 register must be cleared during transmit sequence.
Page 466 GD32F1x0 User Manual transmit on its MOSI pin, the other bits are loaded from transmit buffer to shift-register. The TBE bit is set after the data is loaded from transmit buffer to shift-register. A continuous data can be transmitted if the data is put in the transmit buffer. Write DTR register when the TBE bit is set.
Page 467 GD32F1x0 User Manual Software Write DTR Hadware Set TBE again MOSI D1[4] D1[0] D2[4] D2[0] MISO D1[5] D1[1] D2[5] D2[1] D1[6] D1[2] D2[6] D2[2] D1[7] D1[3] D2[7] D2[3] Quad read operation SPI works in quad read mode when QMOD and QRD both set in SPI_QWCR register. In this mode, MOSI, MISO, IO2 and IO3 are all used as input pins.
Page 468 GD32F1x0 User Manual Hadware Set TBE Software Write DTR Software Write DTR Software Read DTR RBNE MOSI D1[4] D1[0] D2[4] D2[0] MISO D1[5] D1[1] D2[5] D2[1] D1[6] D1[2] D2[6] D2[2] D1[7] D1[3] D2[7] D2[3] Leave quad wire mode or disable SPI Before leaving quad wire mode or disabling SPI, software should first check that TBE bit is set and TRANS bit is cleared, then clear the QMOD bit in SPI_QWCR register or SPIEN bit in SPI_CTLR1 register.
Page 469 GD32F1x0 User Manual from master to slave, the MOSI pin of master outputs the data and the MOSI pin of slave receives the data, the MISO pins are not used. If the RO bit is set in master and cleared in slave, the data is transmitted from slave to master, the MISO pin of slave outputs the data and the MISO pin of master receives the data, the MOSI pins are not used.
Page 470 GD32F1x0 User Manual In receive-only mode, the software should write the CRCNT bit after the second last data has been received (The last data is being received at that time). The CRC value of the received data is received after the last data and is compared with the SPI_RCR, the CRCE is set if they are different.
Page 471 GD32F1x0 User Manual This TRANS flag is set and cleared by hardware. It indicates the state of the communication layer of the SPI. The TRANS flag is useful to detect the end of a transfer if the software wants to disable the SPI. This avoids corrupting the last transfer. For this, the procedure described below must be strictly respected.
Page 472 GD32F1x0 User Manual 15.3.10. Disabling the SPI When a transfer is finished, the software stops the SPI by clearing the SPIEN bit. In some configurations, the last transfer is ongoing after the SPIEN is cleared. To avoid corrupting the last transfer, follow the steps below: Full-duplex mode Wait until RBNE=1 to receive the last data Wait until TBE=1...
Page 473 GD32F1x0 User Manual Interrupt event Event flag Enable Control bit Rx Overrun Error RXORE CRC error CRCE 15.4. I2S function description 15.4.1. General description The block diagram of I2S is shown in the following figure. Figure 15-6. I2S block diagram SYSCLK SPI_MISO / I2S_MCK...
Page 474 GD32F1x0 User Manual transmission and reception on I2S_SD. 15.4.2. Supported audio standards The I2S audio standard is selected by the I2SSTD bits in the SPI_I2SCTLR register. Four audio standards are supported, including I2S Phillips standard, MSB justified standard, LSB justified standard, and PCM standard. All standards except PCM handle audio data time- multiplexed on two channels (the left channel and the right channel).
Page 475 GD32F1x0 User Manual Figure 15-9. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 15-10. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) When the packet type is 32-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DTR register are needed to complete a frame.
Page 476 GD32F1x0 User Manual Figure 15-14. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) When the packet type is 16-bit data packed in 32-bit frame, only one write or read operation to or from the SPI_DTR register is needed to complete a frame. The 16 remaining bits are forced by hardware to 0x0000 to extend the data to 32-bit format.
Page 477 GD32F1x0 User Manual Figure 15-19. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 15-20. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) Figure 15-21. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 15-22. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) LSB justified standard For LSB justified standard, I2S_WS and I2S_SD are updated on the falling edge of I2S_CK.
Page 478 GD32F1x0 User Manual When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DTR register are needed to complete a frame. In transmission mode, if 0x8899AA is going to be sent, the first data written to the SPI_DTR register should be 0xXX88 (the 8 MSB could be any value, but forced to 0x00 instead by hardware), and the second one should be 0x99AA.
Page 479 GD32F1x0 User Manual Figure 15-29. PCM standard short frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 15-30. PCM standard short frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 15-31. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 15-32.
Page 480 GD32F1x0 User Manual below. Figure 15-35. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=0) Figure 15-36. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) Figure 15-37. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 15-38.
Page 481: Table 15-2. I2S Bitrate Calculation Formulas
GD32F1x0 User Manual Figure 15-41. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 15-42. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) 15.4.3. Clock generator Figure 15-43. Block diagram of I2S clock generator I2S_MCK MCKOE CHLEN...
Page 482: Table 15-3. Audio Sampling Frequency Calculation Formulas
GD32F1x0 User Manual configured according to the formulas listed in the following table. Table 15-3. Audio sampling frequency calculation formulas MCKOE CHLEN Formula I2SCLK / (32 * (DIV * 2 + OF)) I2SCLK / (64 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) The configuration and precision of audio sampling frequencies in common use are listed in...
Page 483: Table 15-5. Direction Of I2S Interface Signals For Each Operation Mode
GD32F1x0 User Manual CHLEN = 0 CHLEN = 1 Target SYSCLK MCKOE Real Real Fs(Hz) (MHz) Error Error Fs(Hz) Fs(Hz) 11025 11029.41 0.04% 11029.41 0.04% 8000 8007.11 0.09% 7978.72 0.27% 8000 8035.71 0.45% 8035.71 0.45% 8000 7978.72 0.27% 7978.72 0.27% 8000 8152.17 1.90%...
Page 484: Table 15-6. I2S Interrupt
GD32F1x0 User Manual  Transmitting On-Going flag (TRANS) This TRANS flag is set and cleared by hardware. It indicates the state of the communication layer of the I2S. The TRANS flag is useful to detect the end of a transfer if the software wants to disable the I2S.
Page 485 GD32F1x0 User Manual Initialization sequence I2S initialization sequence contains the five steps shown below. In order to initialize I2S working in master mode, all the five steps should be done. In order to initialize I2S working in slave mode, only step 2, step 3, step 4 and step 5 should be done. ...
Page 486 GD32F1x0 User Manual Master reception sequence The RBNE flag is used to control the reception sequence. As is mentioned before, the RBNE flag indicates the receive buffer is not empty, and may generate an interrupt if the RBNEIE bit in the SPI_CTLR2 register is set. The reception sequence begins immediately when the I2SEN bit in the SPI_I2SCTLR register is set.
Page 487 GD32F1x0 User Manual Slave transmission sequence The transmission sequence in slave mode is similar to that in master mode. The difference between them is described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 488 GD32F1x0 User Manual SCKP BDOE CRCEN CRCNT FF16 RO SWNSSEN SWNSS SPIEN PSC [2:0] MSTMODE SCKPL Bits Fields Descriptions Bidirectional Enable 0: 2 line unidirectional transmit mode 1: 1 line bidirectional transmit mode. The information transfer between the MOSI pin in master and the MISO pin in slave.
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Page 490 GD32F1x0 User Manual 0: Error interrupt is disabled. 1: Error interrupt is enabled. An interrupt is generated when the CRCE bit or the CONFE bit or the RXORE bit or the TXURE bit is set. Reserved Must be kept at reset value. NSSDRV Drive NSS Output 0: NSS output is disabled.
Page 491 GD32F1x0 User Manual 0: No configuration fault occurred 1: Configuration fault occurred. (In master mode, the NSS pin is pulled low in NSS hardware mode or SWNSS bit is low in NSS software mode.) This bit is set by hardware and cleared by a read or write operation on the SPI_STR register followed by a write access to the SPI_CTLR1 register.
Page 492 GD32F1x0 User Manual DTR[7:0] is used for transmission and reception, transmit buffer and receive buffer are 8- bits. If the Data frame format is set to 16-bit data, the DTR[15:0] is used for transmission and reception, transmit buffer and receive buffer are 16-bit. 15.5.5.
Page 493 GD32F1x0 User Manual TCR[15:0] Bits Fields Descriptions 15:0 TCR[15:0] When the CRCEN bit of SPI_CTLR1 is set, the hardware computes the CRC value of the transmitted bytes and save them in TCR register. If the Data frame format is set to 8-bit data, CRC calculation is done based on CRC8 standard, and save the value in TCR[7:0], when the Data frame format is set to 16-bit data, CRC calculation is done based on CRC16 standard, and save the value in TCR[15:0].
Page 494 GD32F1x0 User Manual PCMSM PCM frame synchronization mode 0: Short frame synchronization 1: long frame synchronization This bit has a meaning only when PCM standard is used. This bit should be configured when I2S is disenabled. This bit is not used in SPI mode. Reserved Must be kept at reset value I2SSTD[1:0]...
Page 495 GD32F1x0 User Manual Bits Fields Descriptions 15:10 Reserved Must be kept at reset value MCKOE I2S_MCK output enable 0: I2S_MCK output is disenable 1: I2S_MCK output is enable This bit should be configured when I2S is disenabled. This bit is not used in SPI mode. Odd factor for the prescaler 0: Real divider value is DIV * 2 1: Real divider value is DIV * 2 + 1...
Page 496 GD32F1x0 User Manual This bit should be only be configured when SPI is not busy (TRANS bit cleared) This bit is only available in SPI2. QMOD Quad wire mode enable. 0: SPI is in single wire mode 1: SPI is in quad wire mode This bit should only be configured when SPI is not busy (TRANS bit cleared).
Page 497 GD32F1x0 User Manual Comparator (CMP) 16.1. Introduction The general purpose comparators, CMP1 and CMP2, can work either standalone (all terminal are available on I/Os) or together with the timers. They can be used for a variety of functions including wakeup from low-power mode when triggered by an analog signal, analog signal conditioning and cycle-by-cycle current control loop when combined with the DAC and a PWM output from a timer.
Page 498 GD32F1x0 User Manual Figure 16-1. CMP block diagram of GD32F130xx and GD32F150xx devices Note: V is 1.2V. REFINT Figure 16-2. CMP block diagram of GD32F170xx and GD32F190xx devices Note: V is 1.2V. REFINT...
Page 499 GD32F1x0 User Manual 16.3.1. Comparator clock and reset The CMP clock provided by the clock controller is synchronous with the PCLK. The CMP share common reset and clock enable bits with SYSCFG. 16.3.2. Comparator inputs and outputs The I/Os must be configured in analog mode in the GPIOs registers before they are selected as comparators inputs.
Page 500 GD32F1x0 User Manual having specific functional safety requirements, it is a need to insure that the comparator’s configuration cannot be changed in case of spurious register access or program counter corruption. For this consideration, the comparator control and status register (CMP_CSR) can be entered into the write protect state by setting CMPxLK bit to 1, which should be done once the programming is completed.
Page 501 GD32F1x0 User Manual 11: High hysteresis CMP2PL Polarity of comparator 2 output This bit is used to select the comparator 2 output. 0: Output is not inverted 1: Output is inverted 26:24 CMP2OSEL[2:0] Comparator 2 output selection These bits are used to select the destination of the comparator 2 output. 000: No selection 001: TIMER 1 break input 010: TIMER 1 channel1 Input capture...
Page 502 GD32F1x0 User Manual 0: Comparator 2 disabled 1: Comparator 2 enabled CMP1LK Comparator 1 lock This bit allows to have all control bits of comparator 1 as read-only. This bit is write- once. It can only be cleared by a system reset once It is set by software. 0: CMP_CSR[15:0] bits are read-write 1: CMP_CSR[15:0] bits are read-only CMP1O...
Page 503 GD32F1x0 User Manual 101: PA5 110: PA0 111: Reserved CMP1M[1:0] Comparator 1 mode These bits are used to control the operating mode of the comparator 1 adjust the speed/consumption. 00: High speed / full power 01: Medium speed / medium power 10: Low speed / low power 11: Very-low speed / ultra-low power CMP1SW...
Page 504 GD32F1x0 User Manual 0: Non-inverting input below inverting input and the output is low 1: Non-inverting input above inverting input and the output is high 29:28 CMP2HST[1:0] Comparator 2 hysteresis These bits are used to control the hysteresis level. 00: No hysteresis 01: Low hysteresis 10: Medium hysteresis 11: High hysteresis...
Page 505 GD32F1x0 User Manual 00: High speed / full power 01: Medium speed / medium power 10: Low speed / low power 11: Very-low speed / ultra-low power Reserved Must be kept at reset value CMP2EN Comparator 2 enable 0: Comparator 2 disabled 1: Comparator 2 enabled CMP1LK Comparator 1 lock...
Page 506 GD32F1x0 User Manual These bits are used to select the source connected to the CMP1_M input of the comparator 1. 000: V REFINT 001: V REFINT 010: V *3/4 REFINT 011: V REFINT 100: PA4 (DAC1) 101: PA5 (DAC2) 110: PA0 111: Reserved CMP1M[1:0] Comparator 1 mode...
Page 507 GD32F1x0 User Manual Universal synchronous asynchronous receiver transmitter (USART) 17.1. Introduction The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides a flexible full duplex data exchange using synchronous or asynchronous transfer. The USART is used for transferring data between serial interfaces, and it is also commonly used for RS232 standard communication.
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Page 509: Table 17-1. Usart Important Pins Description
GD32F1x0 User Manual – Receive data register full – Idle line detected – Overrun error – Framing error – Noise error – Parity error – Address/character match – Receiver timeout interrupt – End of block interrupt – Wakeup from Deep-sleep mode While USART1 is fully implemented, USART2 is only partially implemented with the following features not supported.
Page 510 GD32F1x0 User Manual Figure 17-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controler Flow nCTS Controler USART Control Registers USART Address Transmitter Transimit clock...
Page 511: Table 17-2. Stop Bits Configuration
GD32F1x0 User Manual Set the TEN bit in USART_CTLR1. Wait for the TBE being asserted. Write the data to in the USART_DR register. Wait until TC=1 to finish. It is necessary to wait for the TC bit asserted before disabling the USART or entering the power saving mode.
Page 512 GD32F1x0 User Manual DMA read in multibuffer communication can also clear the RBNE bit. Refer to the following procedure for the USART receiving: Write the WL bit in USART_CTLR1 to set the data bits length. Set the stop bits length in USART_CTLR2. Enable DMA (DENR bit) in USART_CTLR3 if multibuffer communication is selected.
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Page 514 GD32F1x0 User Manual sequence. The USART manages this mechanism using the character match function by programming the LF ASCII code in the ADDR field and activating the addrress match interrupt (AMIE=1). When a LF has been received or can check the CR/LF in the DMA buffer, the software will be informed.
Page 515 GD32F1x0 User Manual 17.3.10. Synchronous mode The USART can be used for full-duplex synchronous serial communications only in master mode, by setting the CKEN bit in USART_CTLR2. The LMEN bit in USART_CTLR2 and SCEN, HDEN, IREN bits in USART_CTLR3 should be reset in synchronous mode. The CK pin is the synchronous USART transmitter clock output, and can be only activated when the TEN bit is enabled.
Page 516 GD32F1x0 User Manual should be reset in smartcard mode. A clock is provided to the smartcard if the CKEN bit is set. The clock can be divided for other use. The frame consists of 1 start bit, 9 data bits (1 parity bit included) and 1.5 stop bits. The smartcard mode is a half-duplex communication protocol.
Page 517 GD32F1x0 User Manual deactivate the parity error transmission. When requesting a read from the smartcard, the USART_RTR register should be programmed with the BWT (block wait time) - 11 value and RBNEIE must be set. A timeout interrupt will be generated, if no answer is received from the card before the expiration of this period.
Page 518 GD32F1x0 User Manual CKEN bits in USART_CTLR2 and HDEN, SCEN bits in USART_CTLR3 should be reset in IrDA mode. In IrDA SIR physical layer, an infrared light pulse (a Return to Zero signal) represent the logic ‘0’. The pulse width should be 3/16 of a bit period. The IrDA could not detect the pulse if the pulse width is less than 1 PSC clock.
Page 519 GD32F1x0 User Manual Figure 17-8. IrDA data modulation 17.3.13. Hardware flow control Using the nCTS input and the nRTS output to control the serial data flow is called hardware flow control. The RTS flow control is enabled by writing ‘1’ to the RTSEN bit in USART_CTLR3 and the CTS flow control is enabled by write ‘1’...
Page 520 GD32F1x0 User Manual Figure 17-10. Hardware flow control RTS flow control nRTS start stop idle start data 1 data 2 stop idle CTS flow control nCTS USART_DR empty data 2 empty data 3 empty stop start stop idle start data 1 data 2 stop RS485 Driver Enable...
Page 521: Table 17-3. Usart Interrupt Requests
GD32F1x0 User Manual bytes to be transferred, channel priority, DMA interrupts are written to. The RBNE event occurs as soon as the data is received. 17.3.15. Wakeup from Deep-sleep mode The USART is able to wake up the MCU from Deep-sleep mode by the standard RBNE interrupt or the WUM interrupt.
Page 522 GD32F1x0 User Manual Interrupt event Event flag Enable Control bit End of Block EBIE Wakeup from Deep-sleep mode WUIE All of the interrupt events are ORed together before being sent to the interrupt controller, so the USART can only generate a single interrupt request to the controller at any given time. Software can service multiple interrupt events in a single interrupt service routine Figure 17-11.
Page 523 GD32F1x0 User Manual AMIE PCEN PEIE TBEIE TCIE RBNEIE IDIE UESM Bits Fields Descriptions 31:28 Reserved Must be kept at reset value EBIE End of Block interrupt enable 0: End of Block interrupt is disabled 1: End of Block interrupt is enabled This bit is reserved in USART2.
Page 524 GD32F1x0 User Manual Wakeup method in mute mode 0: Idle Line 1: Address Mark This bit field cannot be written when the USART is enabled (UEN=1). PCEN Parity control enable 0: Parity control disabled 1: Parity control enabled This bit field cannot be written when the USART is enabled (UEN=1). Parity mode 0: Even parity 1: Odd parity...
Page 525 GD32F1x0 User Manual This bit is reserved in USART2. USART enable 0: USART prescaler and outputs disabled 1: USART prescaler and outputs enabled 17.4.2. USART control register 2 (USART_CTLR2) Address offset: 0x04 Reset value: 0x0000_0000 This register has to be accessed by word (32-bit) ADDR[7:0] RTEN ABDM[1:0]...
Page 526 GD32F1x0 User Manual This bit is reserved in USART2. ABDEN Auto baud rate enable 0: Auto baud rate detection is disabled 1: Auto baud rate detection is enabled This bit is reserved in USART2. MSBF Most significant bit first 0: Data is transmitted/received with the LSB first 1: Data is transmitted/received with the MSB first This bit field cannot be written when the USART is enabled (UEN=1).
Page 527 GD32F1x0 User Manual This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved in USART2. Clock polarity 0: Steady low value on CK pin outside transmission window in synchronous mode 1: Steady high value on CK pin outside transmission window in synchronous mode This bit field cannot be written when the USART is enabled (UEN=1).
Page 528 GD32F1x0 User Manual This register has to be accessed by word (32-bit) Reserved WUIE WUM[1:0] SCRTNUM[2:0] Reserved DDRE OVRD OSBM CTSIE CTSEN RTSEN DENT DENR SCEN NACK HDEN IRLP IREN ERIE Bits Fields Descriptions 31:23 Reserved Must be kept at reset value WUIE Wakeup from Deep-sleep mode interrupt enable 0: Wakeup from Deep-sleep mode interrupt is disabled...
Page 529 GD32F1x0 User Manual Driver enable mode This bit is used to activate the external transceiver control, through the DE signal, which is output on the RTS pin. 0: DE function is disabled 1: DE function is enabled This bit field cannot be written when the USART is enabled (UEN=1). DDRE Disable DMA on reception error 0: DMA is not disabled in case of reception error.
Page 530 GD32F1x0 User Manual 0: DMA mode is disabled for transmission 1: DMA mode is enabled for transmission DENR DMA enable for reception 0: DMA mode is disabled for reception 1: DMA mode is enabled for reception SCEN Smartcard mode enable 0: Smartcard Mode disabled 1: Smartcard Mode enabled This bit field cannot be written when the USART is enabled (UEN=1).
Page 531 GD32F1x0 User Manual Reserved BRR [15:4] BRR[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:4 BRR[15:4] Integer of baud-rate divider DIV_INT[11:0] = BRR[15:4] BRR [3:0] Fraction of baud-rate divider If OM = 0, USARTDIV [3:0] = BRR [3:0]; If OM = 1, USARTDIV [3:1] = BRR [2:0], BRR [3] must be reset.
Page 532 GD32F1x0 User Manual In IrDA normal mode. 00000001: can be set this value only In smartcard mode, the prescaler value for dividing the system clock is stored in PSC[4:0] bits. And the bits of PSC[7:5] must be kept at reset value. The division factor is twice as the prescaler value.
Page 533 GD32F1x0 User Manual the timeout measurement is started from the start bit of the last received character. These bits can be written on the fly. The RTF flag will be set if the new value is lower than or equal to the counter. These bits must only be programmed once per received character.
Page 534 GD32F1x0 User Manual Reserved ABDF ABDE Reserved CTSF LBDF RBNE IDLEF Bits Fields Descriptions 31:23 Reserved Must be kept at reset value Receive enable acknowledge flag This bit, which is set/reset by hardware, reflects the receive enable state of the USART core logic.
Page 535 GD32F1x0 User Manual Set by software, by writing 1 to the SBKCMD bit in the USART_CMD register. Clear by hardware during the stop bit of break transmission. ADDR match flag 0: ADDR do not match the received character 1: ADDR matches the received character, An interrupt is generated if AMIE=1in the USART_CTLR1 register.
Page 536 GD32F1x0 User Manual The timeout corresponds to the CWT or BWT timings in smartcard mode. This bit is reserved in USART2 CTS level This bit equals to the inverted level of the nCTS input pin. 0: nCTS input pin is in high level 1: nCTS input pin is in low level CTSF CTS change flag...
Page 537 GD32F1x0 User Manual USART_CMD register. IDLEF IDLE line detected flag 0: No Idle Line is detected 1: Idle Line is detected. An interrupt will occur if the IDLEIE bit is set in USART_CTLR1 Set by hardware when an Idle Line is detected. It will not be set again until the RBNE bit has been set itself.
Page 538 GD32F1x0 User Manual This register has to be accessed by word (32-bit) Reserved Reserved Reserved Reserved Reserved CTSC LBDC Reserved Reserved IDLEC OREC Bits Fields Descriptions 31:21 Reserved Must be kept at reset value Wakeup from Deep-sleep mode clear Writing 1 to this bit clears the WUF bit in the USART_STR register. This bit is reserved in USART2.
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Page 540 GD32F1x0 User Manual Bits Fields Descriptions 31:9 Reserved Must be kept at reset value TDTR[8:0] Transmit Data value The transmit data character is contained in these bits. The value written in the MSB (bit 7 or bit 8 depending on the data length) will be replaced by the parity, when transmitting with the parity is enabled (PE bit set to 1 in the USART_CTLR1 register).
Page 541 GD32F1x0 User Manual MCU Debug (MCUDBG) 18.1. Introduction The MCUDBG module helps debugger to debug power saving mode, TIMER, I2C, RTC, WWDG, IWDG and bxCAN. When corresponding bit set, provide clock when in power saving mode or hold the state for TIMER, WWDG, IWDG, RTC , I2C or bxCAN. ( The contents of bxCAN is only for GD32F170xx and GD32F190xx devices) 18.2.
Page 542 GD32F1x0 User Manual 18.3. MCUDBG registers 18.3.1. MCUDBG ID code register (MCUDBG_IDR) Address: 0xE004 2000 This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] MCUDBG ID code register These bits can be read by software, These bits are unchanged constant. 18.3.2.
Page 543 GD32F1x0 User Manual 0: No effect 1: Hold the Timer 6 counter for debug when core halted Reserved Must be kept at reset value I2C3_HOLD I2C3 hold register This bit is set and reset by software. 0: No effect 1: Hold the I2C3 SMBUS timeout for debug when core halted I2C2_HOLD I2C2 hold register This bit is set and reset by software.
Page 544 GD32F1x0 User Manual 0: No effect 1: At the standby mode, the system clock and HCLK are provided by CK_HSI, a system reset generated when exit stanby mode DEEPSLEEP_HOLD Deep-sleep mode hold register This bit is set and reset by software. 0: No effect 1: At the Deep-sleep mode, the system clock and HCLK are provided by CK_HSI...
Page 545 GD32F1x0 User Manual 0: No effect 1: Hold the Timer 6 counter for debug when core halted Reserved Must be kept at reset value I2C3_HOLD I2C3 hold register This bit is set and reset by software. 0: No effect 1: Hold the I2C3 SMBUS timeout for debug when core halted I2C2_HOLD I2C2 hold register This bit is set and reset by software.
Page 546 GD32F1x0 User Manual 0: No effect 1: Hold the IWDG counter clock for debug when core halted STDBY_HOLD Standby mode hold register This bit is set and reset by software. 0: No effect 1: At the standby mode, the system clock and HCLK are provided by CK_HSI, a system reset generated when exit stanby mode DEEPSLEEP_HOLD Deep-sleep mode hold register...
Page 547 GD32F1x0 User Manual TIMER15_HOLD Timer 15 hold register This bit is set and reset by software. 0: No effect 1: Hold the Timer 15 counter for debug when core halted 15:11 Reserved Must be kept at reset value RTC_HOLD RTC hold register This bit is set and reset by software.
Page 548 GD32F1x0 User Manual Universal serial bus full-speed device interface (USB 2.0 FS) This chapter applies to GD32F150xx devices, mainly describes the USB full-speed device controller and its interface. As this module is different from other serial ports, so the higher complexity of it requires developers to know about its background knowledge.
Page 549: Table 19-1. Gd32F150Xx Usb Implementation
GD32F1x0 User Manual avoided and the USB clock can be slowed down or stopped. It will be resumed when detect activity at the USB bus. 19.2. Main features  USB 2.0 full-speed device controller  Support USB 2.0 Link Power Management (LPM) ...
Page 550: Table 19-2. Gd32F150Xx Usb Signal Pinouts
GD32F1x0 User Manual 48MHz clock of USB controller can be generated by MCU internal or external crystal oscillator, through PLL frequency multiplication:  Regard two frequency division of 8MHz internal oscillator as the input of the PLL, then 12 frequencies doubling of the clock ...
Page 551 GD32F1x0 User Manual Figure 19-1. USB peripheral block diagram DP DM connector PCLK USB PHY （>12MHz） Analog transceiver USB clock （48MHz） Control registers Suspend Endpoint and logic TX-RX Timer selection Interrupt registers S.I.E Control and logic Packet buffer interface EPnCSR registers Packet Register...
Page 552 GD32F1x0 User Manual transmission and reception. It could select proper buffer for endpoints to meet SIE demand and locate them in the right memory addresses according to endpoint register data. It progressive increase address with each byte exchanging until the end of data packet, as well as to follow up on the number of exchanged bytes for preventing buffer overrun.
Page 553 GD32F1x0 User Manual  Interrupt Mapper: This module is used to select interrupts which are generated by the possible USB events and map them to different lines of the NVIC. 19.3.2. Buffer USB buffer transfers data between MCU core and SIE. It is implemented by a special virtual dual port SRAM memory, and it is mapped to the APB1 peripheral memory, from 0x4000 6000 to 0x4000 6400.
Page 554 GD32F1x0 User Manual 16-bits mode. Figure 19-2. An example with buffer descriptor table usage (USB_BAR = 0) 0xFF IN Endpoint 1 Double buffer 0 IN Endpoint 1 Double buffer 1 Endpoint 0 Reception buffer Endpoint 0 Transmission buffer COUNT1_TX1 0x0E ADDR1_TX1 0x0C COUNT1_TX0...
Page 555: Table 19-3. Double-Buffering Buffer Flag Definition
GD32F1x0 User Manual real-time performance. Therefore, the dual buffer is needed. Double buffer endpoint Double buffer endpoint use two buffers to send and receive datas, one of them is used by hardware, and the other one is used by application. In the course of using double buffer, USB peripherals need to know which buffer is used by applications for avoiding conflict.
Page 556 follows:  Firstly, depending on the basis of the endpoint attributes, synchronous endpoint and double buffering endpoint has a high priority, the other endpoints are low priority  Then, according to the same attribute endpoint’s endpoint number to arrange, the smaller the endpoint number, the higher the priority Application should conform to the above priority policy order for processing endpoint interrupt request.
Page 557 GD32F1x0 User Manual otherwise the same interrupt is triggered again. Even if the multiple interrupt flags are set, only one interrupt will be triggered. The sequence to check each interrupt flag of the interrupt flag register in the interrupt service program, which determines the priority of each interrupt event, processing procedures in accordance with this priority to handle the interrupt event.
Page 558 GD32F1x0 User Manual  Clear the IFR register to remove the redundant pending interrupt and then enable other unit Reset interrupt Once reset occurs, the USB module will reset the internal protocol state machine, and the sending and receiving parts will be banned until the reset interrupt bit is cleared. All the configuration registers will keep the original state and will not be reset to ensure that correct execution can transfer immediately after reset, however, device address and endpoint register will be reset.
Page 559 GD32F1x0 User Manual 图 19-1.USB transaction and the interrupt event From host From host To host SETUP token data Set STIF From host To host From host IN token data Set STIF Reset interrupt SOF interrupt RSTIF SOFIF From host From host To host OUT token no data...
Page 560 GD32F1x0 User Manual This is a buffer overrun condition. A STALL handshake is sent, and this transaction fails. If an addressed endpoint is not valid, a NAK or STALL handshake packet is sent instead of the ACK according to bits RX_STA in the USB_EPnCSR register, no data is written in the reception memory buffers.
Page 561 GD32F1x0 User Manual fails, the next SETUP packet transmission will be triggered. The RX_STA bit of the control endpoint cannot be set to '00 (disabled) state. When the SETUP token is received, the USB receives the data, performs the requested data transmission and sends back an ACK handshake packet.
Page 562 GD32F1x0 User Manual bus.  A configured device can draw only up to what is specified in the Max Power field of the configuration descriptor. The maximum value is 500mA.  A suspended device should draw a maximum of 500uA. 2.
Page 563 GD32F1x0 User Manual signal is detected, sleep state will exit. 19.4. USB registers 19.4.1. USB control register (USB_CTLR) Address offset: 0x40 Reset value: 0x0003 This register can be accessed by half-word(16-bit) or word(32-bit) STIE PMOUIE ERRIE WKUPIE SPSIE RSTIE SOFIE ESOFIE Reserved RSREQ SETSPS...
Page 564 GD32F1x0 User Manual Reserved Must be kept at reset value RSREQ The software set a resume request to the USB host, and the USB host should drive the resume sequence according the USB specifications 0: No resume request 1: Send resume request. SETSPS The software should set suspend state when SPSIF bit in USB_IFR register is set 0: Not set suspend state.
Page 565 GD32F1x0 User Manual This bit set by hardware in the SUSPEND state to indicate that activity is detected. The software writes 0 to clear this bit. SPSIF Suspend state interrupt flag When no traffic happen in 3 ms, hardware set this bit to indicate a SUSPEND request. The software writes 0 to clear this bit.
Page 566 GD32F1x0 User Manual 12:11 SOFLN[1:0] SOF lost number Increment every ESOFIF happens by hardware. Cleared once the reception of SOF. 10:0 FCNT[10:0] Frame number counter The Frame number counter incremented every SOF received. 19.4.4. USB device address register (USB_AR) Address offset: 0x4C Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved...
Page 567 GD32F1x0 User Manual Reserved Must be kept at reset value 19.4.6. USB endpoint n control/status register (USB_EPnCSR), n=[0..7] Address offset: 0x00 to 0x1C Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) RX_ST RX_DTG RX_STA[1:0] SETUP EP_CTL[1:0] EP_KCTL TX_ST TX_DTG...
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Page 569 GD32F1x0 User Manual 15:1 TXARn[15:1] Transmission buffer address Start address of the packet buffer containing data to be sent when receive next IN token. TXARn[0] Must be set to 0 19.4.8. USB Transmission byte count register n (USB_TXCNTn) Address offset: [USB_BAR] + n*16 + 4 USB local Address: [USB_BAR] + n*8 + 2 This register can be accessed by half-word(16-bit) or word(32-bit) Reserved...
Page 570: Table 19-9. Sub-Endpoints Status
GD32F1x0 User Manual BLKSIZ BLKNUM[4:0] RXCNTRn[9:0] Bits Fields Descriptions BLKSIZ Block size 0: Block size is 2 bytes 1: Block size is 32 bytes 14:10 BLKNUM[4:0] Block number The number of blocks allocated to the packet buffer. RXCNTRn[9:0] Reception bytes count The number of bytes to be received at next OUT/SETUP token.
Page 571 GD32F1x0 User Manual NYET: NYET handshake status VALID: enable endpoint for reception LPM token 19.4.12. USB LPM control register (USB_LPMCNTR) Address offset: 0x140 Reset value: 0x0000 This register can be accessed by half-word(16-bit) or word(32-bit) LPMSTIE Reserved Bits Fields Descriptions LPMSTIE LPM token successful transfer interrupt enable This bit set and reset by software...
Page 572 GD32F1x0 User Manual Real-time Clock(RTC) 20.1. Introduction The RTC provides a time which includes hour/minute/second/sub-second and a calendar includes year/month/day/week day. The time and calendar are expressed in BCD code except sub-second. Sub-second is expressed in binary code. Hour adjust for daylight saving time. Works in power saving mode and smart wakeup for software configurable.
Page 573 GD32F1x0 User Manual 20.3. Function Description 20.3.1. Block Diagram Figure 20-1.Block diagram of RTC Alarm Logic RTC_ALRMR RTC_ALRMSSR Block Diagram 512Hz RTC_ALARM RTC_OUT RTC_CALIB Output Selection Logic ck_spre (Default 1 Hz) 7-bit 15-bit Digital Smooth Asynchronous Synchronous HSE/32 ck_apre Calibration Prescaler Prescaler Calenda...
Page 574 GD32F1x0 User Manual reference clock input: RTC_REFIN(50 or 60 Hz) 20.3.2. RTC Pin PC13, PC14 and PC15 can be directly controlled by RTC through the register RTC_TAFCR and RTC_CTLR. The function priority of PC13 is obey the below table: PC13 PC13 PC13 COEN...
Page 575 GD32F1x0 User Manual GPIO (1) OD means open drain, PP means push-pull Note: (2) ‘X’ means no effect The function priority of PC15 is obey the below table: PC15 LSEEN in LSEBPS in PC15 PC15 Function RCC_BDCR RCC_BDCR MODE VALUE Oscillator Analog Input...
Page 576 GD32F1x0 User Manual update mechanism is not performed in Deep-Sleep mode and Standby mode. When exiting these modes, software must clear RSYNF bit and wait it is asserted(the max wait time is 2 RTC clock)if software wants to read calendar register under BYPSHAD=0 situation. When reading calendar registers(RTC_SSR,RTC_TSR,RTC_DSR) under Note: BYPSHAD=0, the frequency of the APB clock (f...
Page 577 GD32F1x0 User Manual Circularly reading INITE bit. The initialization phase mode is really entered if INITE is set to 1. It takes around 2 RTCCLK clock cycles (because of clock synchronization). Program both the asynchronous and synchronous prescaler factors in RTC_PSCR register.
Page 579 GD32F1x0 User Manual correct. To ensure the correctness and consistency of the calendar value, software must perform reading operation as this: read all calendar registers continuously, if the last twice data are the same, the data is coherent and correct. 20.3.8.
Page 580 GD32F1x0 User Manual PREDIV_S means the lower PREDIV_A and at the same time the lower PREDIV_A means the higher power consuming. Before using synchronization shift function, the software must check the 15-bit of SS in Note: RTC_SSR(SS[15]) and confirm it is 0. After writing RTC_SHIFTCTLR register, the SOPF bit in RTC_ISTR will set at once.
Page 581 GD32F1x0 User Manual 20.3.11. RTC Smooth digital calibration RTC calibration function is a way to calibrate the RTC frequency based RTC clock cycle number in a configurable period time. This calibration is equally executed in a period time and after finish calibrating once, the cycle number of the RTC clock in the period time will be added or subtracted some individual RTCCLK cycles.
Page 582 GD32F1x0 User Manual corresponding PREDIV_S should be set as following rule: PREDIV_A = 2: 2 less than nominal PREDIV_S(8189 with 32.768KHz) PREDIV_A = 1: 4 less than nominal PREDIV_S(16379 with 32.768KHz) PREDIV_A = 0: 8 less than nominal PREDIV_S(32759 with 32.76KHz) When the PREDIV_A is less than 3,the formula of calibration frequency is as follows: *[1+(256-CALM)/(2 +CALM-256)]...
Page 583 GD32F1x0 User Manual When a time-stamp event occurs on RTC_TS pin, the calendar value will be saved in time- stamp registers(RTC_TDR/RTC_TTR/RTC_TSSSR) and the time-stamp flag(TSF) is set to 1 by hardware. Time-stamp event can generate an interrupt if time-stamp interrupt enable(TSIE) is set.
Page 584 GD32F1x0 User Manual under edge detection mode, the internal pull-up resistors on the tamper detection input pin are deactivated. Because of detecting the tamper event will reset the backup registers(RTC_BKPxR), writing to the backup register should ensure that the tamper event reset and the writing operation will not occur at the same time, a recommend way to avoid this situation is disable the tamper detection before writing to the backup register and re-enable tamper detection after finish writing.
Page 585 GD32F1x0 User Manual 20.3.16. RTC power saving mode management Mode Active in Mode Exit Mode Sleep RTC interrupts Deep- Yes: if clock source RTC alarm/tamper event/timestamp event/wake up sleep is LSE or LSI Yes: if clock source Standby RTC alarm/tamper event/timestamp event/wake up is LSE or LSI 20.3.17.
Page 586 GD32F1x0 User Manual Reserved MT[2:0] MU[3:0] Reserved ST[2:0] SU[3:0] Bits Fields Descriptions 31:23 Reserved Must be kept at reset value AM/PM notation 0: AM or 24-hour format 1: PM 21:20 HT[1:0] Hour tens in BCD code 19:16 HU[3:0] Hour units in BCD code Reserved Keep at reset value 14:12...
Page 587 GD32F1x0 User Manual 15:13 WDU[2:0] Week day units 0x0: Reserved 0x1: Monday … 0x7: Sunday Month tens in BCD code 11:8 MU[2:0] Month units in BCD code Reserved Must be kept at reset value DT[1:0] Date tens in BCD code DU[3:0] Date units in BCD code 20.4.3.
Page 588 GD32F1x0 User Manual 0: Disable invert output RTC_ALARM 1: Enable invert output RTC_ALARM Calibration output selection Valid only when COEN=1 and prescalers are at default values 0: Calibration output is 512 Hz 1: Calibration output is 1Hz Backup This bit is flexible used by software. Often can be used to recording the daylight saving hour adjust.
Page 589 GD32F1x0 User Manual 0: Reading calendar from shadow registers 1: Reading calendar from current real-time calendar Note: If frequency of APB1 clock is less than seven times the frequency of RTCCLK, this bit must set to 1. REFCLKEN Reference clock detection function enable 0: Disable reference clock detection function 1: Enable reference clock detection function Note: Can only be written in initialization state...
Page 590 GD32F1x0 User Manual can clear this bit by writing 0 into this bit. TSOVF Time-stamp overflow flag This bit is set by hardware when a time-stamp event is detected if TSF bit is set before. Cleared by software writing 0. Time-stamp flag Set by hardware when time-stamp event is detected.
Page 591 GD32F1x0 User Manual Set by hardware if alarm register can be write after AE bit has reset. 0: Alarm registers programming is not allowed 1: Alarm registers programming is allowed 20.4.5. RTC prescaler register (RTC_PSCR) Address offset: 0x10 System reset: not effected Backup domain reset value: 0x007F 00FF This register can only be wrote in initialization mode.
Page 592 GD32F1x0 User Manual Bits Fields Descriptions DMSK Alarm date mask bit 0: Not mask date/day field 1: Mask date/day field WDSEL Week day selection 0: DU[3:0] indicates the date units 1: DU[3:0] indicates the week day and DT[3:0] has no means. 29:28 DT[1:0] Date tens in BCD code...
Page 593 GD32F1x0 User Manual Reserved WPKEY[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value WPKEY[7:0] Key for write protection 20.4.8. RTC sub second register (RTC_SSR) Address offset : 0x28 System reset value : 0x0000 0000 when BYPSHAD = 0. Not affected when BYPSHAD = 1.
Page 594 GD32F1x0 User Manual Reserved SFS[14:0] Bits Fields Descriptions One second add 0: Not add 1 second 1: Add one second to the clock/calendar. This bit is jointly use with SFS bit to add a fraction of a second to the clock. 30:15 Reserved Must be kept at reset value...
Page 595 GD32F1x0 User Manual 21:20 HT[1:0] Hour tens in BCD code 19:16 HU[3:0] Hour units in BCD code Reserved Must be kept at reset value 14:12 MT[2:0] Minute tens in BCD code 11:8 MU[3:0] Minute units in BCD code Reserved Must be kept at reset value ST[2:0] Second tens in BCD code SU[3:0]...
Page 596 GD32F1x0 User Manual 20.4.12. RTC timestamp sub second register(RTC_TSSSR) Address offset: 0x38 Backup domain reset: 0x0000 0000 System reset: no effect This register will record the calendar date when TSF is set to 1. Reset TSF bit will also clear this register. This register has to be accessed by word(32-bit) Reserved SS[15:0]...
Page 597 GD32F1x0 User Manual 1: One RTCCLK pulse is equivalently inserted every 2 pulses. This bit should be used in conjunction with CMSK bit. If the input clock frequency is 32.768KHz, the number of RTCCLK pulses added during 32s calibration window is (512 * CALP) - CMSK CWND8 Calibration window select 8 seconds...
Page 598 GD32F1x0 User Manual 0: PC14 is controlled by GPIO configuration. 1: PC14 is forced to push-pull output if LSEEN=0. PC14VAL PC14 value PC14 outputs this value when PC14MODE=1 and LSEEN=0. PC13MDE 0: PC13 is controlled by GPIO configuration. 1: PC13 is forced to push-pull output if all RTC alternate functions are disabled.. PC13VAL Alarm output type control/PC13 output value When RTC alternate function enabled, output RTC_ALARM:...
Page 599 GD32F1x0 User Manual 0x6: Sample once every 512 RTCCLK(64Hz if RTCCLK=32.768KHz) 0x7: Sample once every 256 RTCCLK(128Hz if RTCCLK=32.768KHz) TAPTS Make tamper function used for timestamp function 0: No effect 1: TSF is set when tamper event detected even TSEN=0 Reserved Must be kept at reset value TAP2TRIG...
Page 600 GD32F1x0 User Manual Reserved MSKSS[3:0] Reserved Reserved SS[14:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value 27:24 MSKSS[3:0] Mask control bit of SS 0x0: Mask alarm sub second setting. The alarm asserts at every second time point if all the rest alarm fields are matched.
Page 601 GD32F1x0 User Manual BKP[31:16] BKP[15:0] Bits Fields Descriptions 31:0 BKP[31:0] Backup domain registers. These registers can be wrote or read by software. The content remains valid even in power saving mode because they can powered-on by V . Tamper detection flag TAMPxF assertion or disable Flash readout protection will reset these registers.
Page 602 GD32F1x0 User Manual Touch Sensing Interface(TSI) 21.1. Introduction Touch Sensing Interface (TSI) provides a convenient solution for touch keys, sliders and capacitive proximity sensing applications. The controller builds on charge transfer method. Placing a finger near fringing electric fields adds capacitance to the system and TSI is able to measure this capacitance change using charge transfer method.
Page 603 GD32F1x0 User Manual etc. Detecting the change of a system is the key problem and goal in these technologies. The TSI module is designed to use charge transfer method which detects the capacitive change of an electrode when touched by or a finger close to it. In order to detect the capacitive change, TSI performs a charge transfer sequence including several charging, transfer steps.
Page 604: Table 21-1. Pin And Analog Switch State In A Charge-Transfer Sequence
GD32F1x0 User Manual Table 21-1. Pin and analog switch state in a charge-transfer sequence Step Name ASW1 ASW2 Pin1 Pin2 Discharge Close Close Input Floating Pull Down Buffer Time1 Open Open Input Floating Input Floating Charge Open Open Output High Input Floating Extend Charge Open...
Page 605 GD32F1x0 User Manual 5. Buffer Time2 Buffer time with ASW1 and ASW2 open, PIN1 is configured to input floating. 6. Charge transfer ASW1 and ASW2 are closed and PIN1 is configured to input floating to transfer charge from C to C .
Page 606 GD32F1x0 User Manual 21.3.4. Charge transfer sequence FSM A hardware FSM is designed in chip to perform the charge transfer sequence described in the previous section as shown in Figure 21-4. Figure 21-4. FSM flow of a charge-transfer sequence IDLE(discharge) Started Buffer Time1 Charge...
Page 607: Table 21-2. Duration Time Of Extend Charge State In Each Cycle
GD32F1x0 User Manual As shown in Figure 21-4, after 27 cycles, V (the voltage of sample pin) reaches (the threshold voltage). There is also a max cycle number defined by MCN in TSI_CTLR register. When the cycle number reaches MCN, FSM returns to IDLE state and stops after Compare State, whether reaches V or not.
Page 608 21.3.7. ASW and hysteresis mode A channel or sample pin’s analog switch is controlled by charge-transfer sequence when FSM is running, as shown in Table 21-1. When the FSM is IDLE, these pins’ analog switches are controlled by GxPy bits in TSI_ASW register. All free pin’s analog switches are controlled by GxPy bits too.
Page 609: Table 21-4. Tsi Pins
GD32F1x0 User Manual TSI stops because all enabled samplers’ CTCF CCTCF bit in TSI_CEFR sample pins reach V TSI stops because the cycle number CMNE bit in TSI_CEFR reaches the maximum value. 21.3.10. TSI GPIOs Table 21-4. TSI pins TSI Group TSI Pins GPPIN pins PIN1...
Page 610 GD32F1x0 User Manual R4t( )-304.3qQ8001 15001 15001 15001 15001 15001 4001g 6/F581 60747.434509.76 54 0 7 TJ1 ( d21d217S04 0.48 reLaL(.96 31320.5 744.6S47C.365S 29.0WfM8 g 6.365S 29.01 15001 4001 wwww CDT[3:0] CTDT[3:0] CTDT[349.49 734.21.66 744.94 0.480087744.915 744.494 Tmf*421.80.5 7448 rere-US04 0.48 reLaL4.48 r 15.6 reW* n ECDT[6:0] ECEN CTD3.
Page 611 GD32F1x0 User Manual 1: TSI module is disabled 21.4.2. TSI interrupt from error or flag interrupt enable register(TSI_IER) Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by word(32-bit). Reserved Reserved MNEIE CRCFIE Bits Fields Descriptions 31:2 Reserved Must be kept at reset value MNEIE...
Page 612 GD32F1x0 User Manual 1: Clear MNE CCTCF Clear charge-transfer complete flag 0: Reserved 1: Clear CTCF 21.4.4. TSI status register(TSI_STR) Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by word(32-bit). Reserved Reserved CTCF Bits Fields Descriptions 31:2 Reserved Must be kept at reset value...
Page 613 GD32F1x0 User Manual Reserved G6P4 G6P3 G6P2 G6P1 G5P4 G5P3 G5P2 G5P1 G4P4 G4P3 G4P2 G4P1 G3P4 G3P3 G3P2 G3P1 G2P4 G2P3 G2P2 G2P1 G1P4 G1P3 G1P2 G1P1 Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:0 GxPy Pin hysteresis mode This bit is set and cleared by software.
Page 614 GD32F1x0 User Manual G4P4 G4P3 G4P2 G4P1 G3P4 G3P3 G3P2 G3P1 G2P4 G2P3 G2P2 G2P1 G1P4 G1P3 G1P2 G1P1 Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:0 GxPy Sample pin mode This bit is set and cleared by software. 0: Pin GxPy is not a sample pin 1: Pin GxPy is a sample pin 21.4.8.
Page 615 GD32F1x0 User Manual Reserved Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 21:16 Group complete This bit is set by hardware when charge-transfer sequence for an enabled group is complete. It is cleared by hardware when a new charge-transfer sequence starts. 0: Charge-transfer for group x is not complete 1: Charge-transfer for group x is complete 15:6...
Page 616 LSE oscillator HSI oscillator with settled prescaler (HSI/244)  For ultra low-power applications ,HDMI-CEC controller can work in Deep-sleep mode  Programmable SFT(Signal Free Time) value for arbitration priority: User configure Auto configure by controller as HDMI-CEC protocol specification  Programmable own address(OADR) ...
Page 617 GD32F1x0 User Manual 27KΩ pull-up resister connected to a +3.3V supply voltage. When the CEC device is in the output state, in order to allow a wired-and connection it must have an open-drain or open- collector. Using HDMI-CEC controller needs configuring CEC pin as alternate function open drain and a 27kΩ...
Page 619 GD32F1x0 User Manual Time (ms) The bit start event. T6 as the latest time that a device is allowed to return to a high 1.7ms impedance state(logical 0). 2.05ms T7 as the earliest time for the start of a following bit. 2.4ms As a nominal data bit period.
Page 620 GD32F1x0 User Manual the periods mentioned above to send their own messages after the current device has finished sending its current message. If SFT is not 0x0,the corresponding user configure SFT will be performed. 22.3.5. SFT option bit description SFT option bit support another way for saving bus inactive time through setting more SFT counter’s start time point.
Page 621 GD32F1x0 User Manual Another frame error situation is that the CEC bus pin voltage is different from CEC pad when HDMI-CEC controller is under initiator state(TE flag asserted). Bit Rising Error(RBRE) RBRE flag can be asserted if rising edge detected during the RBRE checking window and RBRE flag will also generate CEC interrupt if the RBREIE=1.
Page 622: Table 22-2. Error Handling Timing Parameter Table
GD32F1x0 User Manual 1.5ms 2.4ms 0.6ms 2.4ms Nominal sample time 1.05 ms Table 22-2. Error Handling Timing Parameter Table Symbol RTOL Time(ms) Description The bit start event. 0.3ms When indicating a logical 1,T1as the earliest time for a low - 0.4ms high transition.
Page 623: Table 22-3. Te Timing Parameter Table
GD32F1x0 User Manual TX arb-bit=0/1 Legend: Checking Window TX data=0 High Impedence Logic Low Impedence 1.5ms 2.4ms TX ack TX data=1 High Impedence Logic Low Impedence 0.6ms 2.4ms Nominal sample time 1.05 ms Table 22-3. TE Timing Parameter Table Symbol RTOL Time(ms) Description...
Page 624 GD32F1x0 User Manual Interrupt event in HDMI-CEC Event flag Interrupt enable bit Transmission end TEND TENDIE TX Byte buffer underrun TUIE TX error TEIE TX acknowledge error TAEIE RX Byte Received RBRIE Reception end REND RENDIE RX Overrun ROIE RX-Bit rising error RBRE BREIE RX-Short Bit Period Error...
Page 625 GD32F1x0 User Manual Start-bit will performance one CEC line. Software can abort sending the message through clear CECON bit under SOM=1. 0: No CEC transmission is on-going 1: CEC transmission is pending or executing CECON Enable/disable HDMI-CEC controller bit. CECON bit is configured by software. 0: Disable HDMI-CEC controller.
Page 626 GD32F1x0 User Manual This bit is set and cleared by software. 0: SFT counter starts counting when SOM is asserted 1: SFT counter starts automatically after transmission/reception en BCNG Do not generate Error-bit in broadcast message This bit is set and cleared by software. 0: In broadcast mode, RBRE and RLBPE will generate Error-bit on CEC line and if LSTNM=1, RSBPE will also generate Error-bit 1: Error-bit is not generated in the same condition as above...
Page 627 GD32F1x0 User Manual 0x7: 7.5 nominal data bit periods 22.4.3. CEC Data of Transaction Register (CEC_TDTR) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved txdata[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value txdata[7:0] Tx data register This bit is write only.
Page 628 GD32F1x0 User Manual 22.4.5. CEC Interrupt Status Register(CEC_ISTR) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved TEND LSTARB RLBPE RSBPE RBRE REND rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1...
Page 629 GD32F1x0 User Manual controller and CEC device sending the start bit at the same time but the controller’s initiator address priority is lower. If LSTARB is asserted, the controller will get into reception state and after finish receiving the message the controller will retry to send message. During receiving and sending message, the SOM will keep set.
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Page 631 GD32F1x0 User Manual This bit is set by and cleared by software. 0: RLBPE interrupt disable 1: RLBPE interrupt enable RSBPEIE RSBPE Interrupt Enable. This bit is set by and cleared by software. 0: RSBPE interrupt disable 1: RSBPE interrupt enable RBREIE RBRE Interrupt Enable.
Page 632 GD32F1x0 User Manual LCD controller (LCD) This chapter applies to GD32F170xx and GD32F190xx devices. 23.1. Introduction The LCD controller directly drives LCD displays by creating the AC segment and common voltage signals automatically. It can drive the monochrome passive liquid crystal display (LCD) which composed of a plurality of segments (pixels or complete symbols) that can be converted to visible or invisible.
Page 633 GD32F1x0 User Manual Figure 23-1. LCD Block Diagram COM0...7 control signal ANALOG matrix SEG0...31 data data The LCD REG is the register of LCD controller, which configured by APB bus, and generate interrupt to CPU. It includes LCD_CTLR, LCD_CFGR, LCD_SFR, LCD_ICR, LCD_DATAx registers.
Page 634: Table 23-1. The Odd Frame Voltage
GD32F1x0 User Manual The SOF bit in LCD_SFR register is set by the hardware at the start of the frame, and the LCD interrupt is executed if the SOFIE bit in LCD_CFGR is set. SOF is cleared by writing 1 to the SOFC bit in LCD_ICR register.
Page 635 GD32F1x0 User Manual BIAS Static 1/2 bias 1/3 bias 1/4 bias COM inactive 1/2 VLCD 1/3 VLCD 1/4 VLCD SEG active SEG inactive VLCD VLCD 2/3 VLCD 1/2 VLCD Table 23-2. The even frame voltage BIAS Static 1/2 bias 1/3 bias 1/4 bias COM active 1/2 VLCD...
Page 636 GD32F1x0 User Manual Figure 23-3. 1/4 Bias, 1/6 Duty VLCD 3/4VLCD COM0 1/2VLCD 1/4VLCD VLCD 3/4VLCD COM2 1/2VLCD 1/4VLCD VLCD 3/4VLCD COM3 1/2VLCD 1/4VLCD VLCD 3/4VLCD COM5 1/2VLCD 1/4VLCD VLCD 3/4VLCD SEG2 1/2VLCD 1/4VLCD VLCD 3/4VLCD SEG4 1/2VLCD 1/4VLCD DEAD time: The dead time is using DD bits in LCD_CFGR register.
Page 637 GD32F1x0 User Manual 23.3.5. Double buffer memory The double buffer memory is used to ensure the coherency of the displayed information. The application access the first buffer according to modify the LCD_DATAx registers. After writing the displayed information into the LCD_DATAx registers, the application need to set the UPRF bit in LCD_SR register, then the hardware will transfer the data from the first buffer to the seconed buffer, during this time, the UPRF keeps set and the LCD_DATAx registers are write protected.
Page 638 GD32F1x0 User Manual External decoupling: The VLCD intermediate voltage rails (VLCDrail1, VLCDrail2, VLCDrail3 in the figure 23-5) can be connect to the GPIOs by configuring the LCD_DECA bits of the SYSCFG_R2 register. Adding decoupling capacitors on these GPIOs helps to get a steady voltage resulting in a higher contrast.
Page 639 GD32F1x0 User Manual 00: 1/4 Bias (5 voltage levels: VSS, 1/4VLCD, 1/2VLCD, 3/4VLCD, VLCD) 01: 1/2 Bias (3 voltage levels: VSS, 1/2VLCD, VLCD) 10: 1/3 Bias (4 voltage levels: VSS, 1/3VLCD, 2/3VLCD, VLCD) 11: Reserved DUTY[2:0] Duty select These bits determine the duty cycle. Duty is the number defined as 1/(number of common terminals on a given LCD display).
Page 640 GD32F1x0 User Manual Set these bits define the prescaler of LCD clock. 0000: f in_clk 0001: f in_clk 0010: f in_clk 1111: f /32768 in_clk 21:18 DIV[3:0] LCD clock divider Set these bits define the division factor of the DIV divider. 0000: f 0001: f 0010: f...
Page 641 GD32F1x0 User Manual Set these bits configure the length of the dead time between frames. 000: No dead time 001: 1 phase dead time 010: 2 phase dead time 111: 7 phase dead time PULSE[2:0] Pulse ON duration Set these bits define the pulse duration in terms of PRE pulses. 000: 0 001: 1/f 010: 2/f...
Page 642 GD32F1x0 User Manual Reserved SYNF VRDYF UPDF UPRF Bits Fields Descriptions 31:6 Reserved Must be kept at reset value SYNF LCD_CFGR register synchronization flag This bit is set when LCD_CFGR register update to LCD clock domain, and It is cleared by hardware when writing to the LCD_CFGR register. 0: LCD_CFGR Register not yet synchronized 1: LCD_CFGR Register synchronized to LCD clock domain VRDYF...
Page 643 GD32F1x0 User Manual Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved UPDC Reserved SOFC Reserved Bits Fields Descriptions 31:4 Reserved Must be kept at reset value UPDC LCD data update done clear bit Set this bit to clear the UPDF flag in LCD_SFR register. 0: No effect 1: Clear UPDF flag Reserved...
Page 644 GD32F1x0 User Manual Operational amplifiers (OPAMP)/Programmable Cur rent and Voltage Reference (IVREF) This chapter applies to GD32F170xx and GD32F190xx devices. 24.1. Operational amplifiers (OPAMP) 24.1.1. Introduction There are three operational amplifiers in the MCU and the operational amplifiers can be able to route to external or internal follower.
Page 645 GD32F1x0 User Manual Figure 24-1. OPAMP1 Signal Route Figure 24-2. OPAMP2 Signal Route Figure 24-3. OPAMP3 Signal Route DAC2 OPAMP3 switch matrix OPAMP_CTLR register can select the routing for the three operational amplifiers. For OPAMP1-3, S3/S4 is used to connect DAC1/DAC2 to their positive input. The OPAx_PD bit can be used to power down all operational amplifiers.
Page 646 GD32F1x0 User Manual Calibration Before leaving factory, the default factory trimming values are stored in nonvolatile memory and used to initialize the operational amplifier offset. But also the chip support software using the user value to trim the operational amplifier offset. During trimming operation, all switches related to the inputs of each operational amplifier must be disconnected.
Page 647 GD32F1x0 User Manual Offset analog cal-high Offset analog cal-low 24.1.4. OPAMP registers OPAMP control register (OPAMP_CTLR) Address offset: 0x5C Reset value: 0x0001 0101 This register has to be accessed by word(32-bit) OPA_ OPA3CAL OPA2CAL OPA1CAL S4OPA OPA3 OPA3 OPA3CA OPA3 RANG Reserved CAL_H...
Page 648 GD32F1x0 User Manual 1: OPAMP3 low power mode on OPA3CAL_H OPAMP3 offset calibration for N diff 0: OPAMP3 offset calibration for N diff OFF 1: OPAMP3 offset calibration for N diff ON if OPA3CAL_L = 0 OPA3CAL_L OPAMP3 offset calibration for P diff 0: OPAMP3 offset calibration for P diff OFF 1: OPAMP3 offset calibration for P diff ON if OPA3CAL_H = 0 S3OPA3...
Page 649 GD32F1x0 User Manual S1OPA2 S1 switch enable for OPAMP2 0: S1 switch opened 1: S1 switch closed T3OPA2 T3 switch enable for OPAMP2 0: T3 switch opened 1: T3 switch closed OPA2PD OPAMP2 power down 0: OPAMP2 enabled 1: OPAMP2 disabled OPA1LPM OPAMP1 low power mode 0: OPAMP1 low power mode off...
Page 650 GD32F1x0 User Manual This register has to be accessed by word (32-bit) OT_USER Reserved OA3_TRIM_HIGH[4:0] OA3_TRIM_LOW[4:0] OA2_TRIM_HIGH[4:1] OA2_ TRIM_HIG OA2 _TRIM_LOW[4:0] OA1 _TRIM_HIGH[4:0] OA1 _TRIM_LOW[4:0] H[0] Bits Fields Descriptions OT_USER This bit is set and cleared by software; it is always read as 0. It is used to select if the OPAMPx offset is trimmed by the preset factory-programmed trimming values or the user programmed trimming value.
Page 651 GD32F1x0 User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value OA3_TRIM_LP_HIG OPAMP3, low-power mode 5-bit offset trim value for NMOS pairs 29:25 H[4:0] OA3_TRIM_ OPAMP3, low-power mode 5-bit offset trim value for PMOS pairs 24:20 LP_LOW[4:0] OA2_TRIM_ OPAMP2, low-power mode 5-bit offset trim value for NMOS pairs 19:15...
Page 652 GD32F1x0 User Manual 24.2.3. Function description Signal routing IREF When IREF is used, the PB0 pin should be configured to analog input mode. When VREF is used, the PB1 pin should be configured as an analog I/O and external VREF decoupling capacitors are recommended.
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Page 654 GD32F1x0 User Manual Controller Area Network (bxCAN) This chapter applies to GD32F170xx and GD32F190xx devices. 25.1. Introduction CAN bus (for controller area network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. The Basic Extended CAN (bxCAN), interfaces the CAN network.
Page 655 GD32F1x0 User Manual 25.3. Function description Figure below shows the CAN block diagram. Figure 25-1. CAN module block diagram Transmit Receive CAN1 CAN1 Tx/Rx mailbox[0..2] FIFO[0..1] Transmit Receive CAN2 CAN2 Tx/Rx mailbox[0..2] FIFO[0..1] 25.3.1. Working mode The bxCAN interface has three working modes: ...
Page 656 GD32F1x0 User Manual Initial working mode The bxCAN enters initial working mode whenever the options of CAN bus communication need to be changed. Set IWM bit in CAN_CTLR register to enter initial working mode or clear it in order to leave. Normal working mode After initialization, the bxCAN can enter normal working mode and is ready to communicate with other CAN communication nodes.
Page 657 GD32F1x0 User Manual Set LCM and SCM bit in CAN_BTR register to enter loopback and silent communication mode or clear them to leave. Loopback and silent communication mode is useful on self-test. The TX pin holds logical one. The RX pin holds high impedance state. Normal communication mode Normal communication mode is the default communication mode unless the LCM or SCM bit in CAN_BTR register is set.
Page 658 GD32F1x0 User Manual Figure 25-3. State of transmission mailbox Transmit status and error The CAN_TSTR register includes the transmit status and error bits: MTF, MTFNE, MAL, MTE.  MTF: mailbox transmits finished. Typically, MTF is set when the frame in the transmit mailbox has been sent.
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Page 660 GD32F1x0 User Manual CAN_RFR0 and CAN_RFR1. If at least one frame has been stored in the receive FIFO0, set RFD bit in CAN_RFR0 to read one frame from receive FIFO. The frame data is placed in the registers (CAN_RFMIR0, CAN_RFMPR0, CAN_RFMD0R0, CAN_RFMD1R0) until the RFD bit in CAN_RFR0 register is cleared.
Page 661 GD32F1x0 User Manual Figure 25-6. 16-bit filter Mask mode In mask mode the identifier registers are associated with mask registers specifying which bits of the identifier are handled as “must match” or as “don’t care”. 32-bit mask mode example is shown in figure below.
Page 662 The automatic retransmission is disabled in the time-triggered CAN communication. 25.3.7. Communication parameters Nonautomatic retransmission mode This mode has been implemented in order to fulfill the requirement of the time-triggered communication option of the CAN standard. To configure the hardware in this mode the ARD bit in the CAN_CTLR register must be set.
Page 663 GD32F1x0 User Manual synchronization purposes a further time segment, the propagation delay segment, is needed in addition to the time reserved for synchronization, the phase buffer segments. The propagation delay segment takes into account the signal propagation on the bus as well as signal delays caused by transmitting and receiving nodes.
Page 664 GD32F1x0 User Manual �� = �� = �� + �� + �� _�� 1 ��2 with: �� = 1 × �� _�� = (1 + ��. ��1) × �� 1 �� = (1 + ��. ��2) × �� 2 ��...
Page 665 GD32F1x0 User Manual 25.3.9. bxCAN interrupts Four interrupt vectors are dedicated to bxCAN. Each interrupt source can be independently enabled or disabled seting or reseting related bits in CAN_IER. The interrupt sources can be classified into:  transmit interrupt  FIFO0 interrupt ...
Page 666 GD32F1x0 User Manual – Enter into sleep mode. 25.3.10. bxCAN PHY mode If set PHYEN bit in CAN_PHYCR register, integrated CAN PHY is enabled. At this time the internal transceiver will begin to work. This mode only used for bxCAN1. The connection outside of MCU chip is refer to the figure as follows: Figure 25-12.
Page 667 GD32F1x0 User Manual Reset value: 0x0001 0002 This register has to be accessed by word(32-bit). Reserved Reserved ABOR RFOD Bits Fields Descriptions 31:17 Reserved Must be kept at reset value Debug freeze 0: CAN reception and transmission working during debug 1: CAN reception and transmission stop working during debug Software reset 0: Normal operation.
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Page 669 GD32F1x0 User Manual 1: Wakeup event is coming. This bit is set while the interrupt is enabling. Error interrupt flag 0: No error interrupt 1: Any error interrupt has happened while the interrupt is enabling Sleep working state 0: CAN is not the state of sleep working mode 1: CAN is the state of sleep working mode Initial working state 0: CAN is not the state of initial working mode...
Page 670 GD32F1x0 User Manual 1: Transmit mailbox 1 empty TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24 NUM[1:0] These bits are the number of the transmit FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.
Page 671 1: Mailbox 0 transmit finished 25.4.4. CAN receive FIFO0 register (CAN_RFR0) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Reserved RFD0 RFO0 RFF0 Reserved RFL0[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value RFD0 Receive FIFO 0 dequeue...
Page 672 GD32F1x0 User Manual 1: The receive FIFO 0 is full Reserved Must be kept at reset value RFL0[1:0] Receive FIFO 0 length These bits are the length of the receive FIFO0. 25.4.5. CAN receive FIFO1 register (CAN_RFR1) Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 673 GD32F1x0 User Manual This register has to be accessed by word(32-bit). Reserved SWIE Reserve RFOIE RFFIE RFNEIE RFOIE RFFIE RFNEIE TMEI Reserved Bits Fields Descriptions 31:18 Reserved Must be kept at reset value SWIE Sleep working interrupt enable 0: Sleep working interrupt disable 1: Sleep working interrupt enable Wakeup interrupt enable 0: Wakeup interrupt disable...
Page 674 GD32F1x0 User Manual RFFIE1 Receive FIFO1 full interrupt enable 0: Receive FIFO1 full interrupt disable 1: Receive FIFO1 full interrupt enable RFNEIE1 Receive FIFO1 not empty interrupt enable 0: Receive FIFO1 not empty interrupt disable 1: Receive FIFO1 not empty interrupt enable RFOIE0 Receive FIFO0 overfull interrupt enable 0: Receive FIFO0 overfull interrupt disable...
Page 675 GD32F1x0 User Manual can set these bits to 0b111. 000: No Error 001: Stuff Error 010: Form Error 011: Acknowledgment Error 100: Bit recessive Error 101: Bit dominant Error 110: CRC Error 111: Set by software Reserved Must be kept at reset value Bus-off error Whenever the bxCAN enters buf-off state, the bit will be set by the hardware.
Page 676 GD32F1x0 User Manual 25:24 SJW[1:0] Resynchronization jump width Resynchronization jump width time quantum= SJW[1:0]+1 Reserved Must be kept at reset value 22:20 BS2[2:0] Bit segment 2 Bit segment 2 time quantum=BS2[2:0]+1 19:16 BS1[3:0] Bit segment 1 Bit segment 1 time quantum=BS1[3:0]+1 15:10 Reserved Must be kept at reset value...
Page 677 GD32F1x0 User Manual Transmit enable 0: Transmit disable 1: Transmit enable This bit is set by the software when one frame will be transmitted and reset by the hardware when the transmit mailbox is empty. 25.4.10. CAN transmit mailbox property register (CAN_TMPRx) (x=0..2) Address offset: 0x184, 0x194, 0x1A4 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit).
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Page 679 GD32F1x0 User Manual SFID[10:0]/EFID[28:18] EFID[17:13] EFID[12:0] Reserved Bits Fields Descriptions 31:21 SFID[10:0]/EFID[28:18] The frame identifier SFID[10:0]: Standard format frame identifier EFID[28:18]: Extended format frame identifier 20:16 EFID[17:13] The frame identifier EFID[17:13]: Extended format frame identifier 15:3 EFID[12:0] The frame identifier EFID[12:0]: Extended format frame identifier Frame format 0: Standard format frame...
Page 680 GD32F1x0 User Manual 15:8 FI[7:0] Filtering index The index of the filter by which the frame is passed. Reserved Must be kept at reset value DLC[3:0] Data length code DLC[3:0] is the number of bytes in a frame. 25.4.15. CAN receive FIFO mailbox data0 register (CAN_RFMD0Rx) (x=0..1) Address offset: 0x1B8, 0x1C8 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit).
Page 681 GD32F1x0 User Manual 31:24 DB7[7:0] Data byte 7 23:16 DB6[7:0] Data byte 6 15:8 DB5[7:0] Data byte 5 DB4[7:0] Data byte 4 25.4.17. CAN filter control register (CAN_FCTLR) Address offset: 0x200 Reset value: 0x2A1C 0E01 This register has to be accessed by word(32-bit). Reserved Reserved HBC2F[5:0]...
Page 682 GD32F1x0 User Manual Bits Fields Descriptions 31:28 Reserved Must be kept at reset value 27:0 Filter mode 0: Filter x with Mask mode 1: Filter x with List mode 25.4.19. CAN filter scale register (CAN_FSR) Address offset: 0x20C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit).
Page 683 GD32F1x0 User Manual 27:0 FAFx Filter associated FIFO 0: Filter x associated with FIFO0 1: Filter x associated with FIFO1 25.4.21. CAN filter working register (CAN_FWR) Address offset: 0x21C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved Bits Fields...
Page 684 GD32F1x0 User Manual 0: Mask match disable 1: Mask match enable List mode 0: List identifier bit is 0 1: List identifier bit is 1 25.4.23. CAN PHY control register (CAN_PHYCR) Address offset: 0x3FC Reset value: 0x0000 0300 This register has to be accessed by word(32-bit). Reserved Reserved POMODE...
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