GigaDevice Semiconductor GD32F403 Series User Manual

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GigaDevice Semiconductor Inc.

GD32F403xx

Arm

Cortex

-M4 32-bit MCU

User Manual

Revision 2.6

( Jul. 2022 )

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Summary of Contents for GigaDevice Semiconductor GD32F403 Series

Page 1 GigaDevice Semiconductor Inc. GD32F403xx Cortex -M4 32-bit MCU ® ® User Manual Revision 2.6 ( Jul. 2022 )
Page 2: Table Of Contents
GD32F403xx User Manual Table of Contents Table of Contents......................... 2 List of Figures ........................16 List of Table ........................23 1. System and memory architecture ................26 1.1. ® Cortex ® -M4 processor ...................26 1.2. System architecture .....................27 1.3. Memory map.......................29 1.3.1.
Page 3 GD32F403xx User Manual 2.4.5. Control register 0(FMC_CTL0) ......................51 2.4.6. Address register 0 (FMC_ADDR0) ..................... 52 2.4.7. Option byte status register (FMC_OBSTAT) ..................53 2.4.8. Erase/Program Protection register (FMC_WP) ................53 2.4.9. Unlock key register 1(FMC_KEY1)..................... 54 2.4.10. Status register 1 (FMC_STAT1) ......................54 2.4.11.
Page 4 GD32F403xx User Manual 5.2.3. Function overview........................... 78 5.3. Register definition....................83 5.3.1. Control register (RCU_CTL)......................... 83 5.3.2. Clock configuration register 0 (RCU_CFG0) ..................85 5.3.3. Clock interrupt register (RCU_INT) ....................88 5.3.4. APB2 reset register (RCU_APB2RST) ....................92 5.3.5. APB1 reset register (RCU_APB1RST) ....................94 5.3.6.
Page 5 GD32F403xx User Manual 7.6.1. Interrupt enable register (EXTI_INTEN) ..................131 7.6.2. Event enable register (EXTI_EVEN) ....................131 7.6.3. Rising edge trigger enable register (EXTI_RTEN) ................132 7.6.4. Falling edge trigger enable register (EXTI_FTEN)................132 7.6.5. Software interrupt event register (EXTI_SWIEV) ................132 7.6.6. Pending register (EXTI_PD).......................133 8.
Page 6 GD32F403xx User Manual 8.5.9. Event control register (AFIO_EC) .....................154 8.5.10. AFIO port configuration register 0 (AFIO_PCF0) ................154 8.5.11. EXTI sources selection register 0 (AFIO_EXTISS0) ..............157 8.5.12. EXTI sources selection register 1 (AFIO_EXTISS1) ..............159 8.5.13. EXTI sources selection register 2 (AFIO_EXTISS2) ..............160 8.5.14.
Page 7 GD32F403xx User Manual 11.2. JTAG/SW function description .................. 184 11.2.1. Switch JTAG or SW interface......................184 11.2.2. Pin assignment ............................184 11.2.3. JTAG daisy chained structure ......................185 11.2.4. Debug reset............................185 11.2.5. JEDEC-106 ID code..........................185 11.3. Debug hold function description................185 11.3.1. Debug support for power saving mode....................185 11.3.2.
Page 8 GD32F403xx User Manual 12.7.4. Sample time register 0 (ADC_SAMPT0) ..................210 12.7.5. Sample time register 1 (ADC_SAMPT1) ..................211 12.7.6. Watchdog high threshold register (ADC_WDHT)................212 12.7.7. Watchdog low threshold register (ADC_WDLT) ................212 12.7.8. Routine sequence register 0 (ADC_RSQ0)..................213 12.7.9. Routine sequence register 1 (ADC_RSQ1)..................213 12.7.10.
Page 9 GD32F403xx User Manual 14.1.4. Register definition ..........................235 Window watchdog timer (WWDGT) ..............238 14.2. 14.2.1. Overview ..............................238 14.2.2. Characteristics............................238 14.2.3. Function overview..........................238 14.2.4. Register definition ..........................241 Real-time Clock(RTC) .................... 243 15.1. Overview ....................... 243 15.2. Characteristics ......................243 15.3. Function overview ....................243 15.3.1.
Page 10 GD32F403xx User Manual 16.3.2. Characteristics............................345 16.3.3. Block diagram ............................346 16.3.4. Function overview..........................347 16.3.5. TIMERx registers(x=8, 11) ........................358 16.4. General level2 timer (TIMERx, x=9, 10, 12, 13)............370 16.4.1. Overview ..............................370 16.4.2. Characteristics............................370 16.4.3. Block diagram ............................370 16.4.4. Function overview..........................372 16.4.5. TIMERx registers(x=9, 10, 12, 13)....................379 16.5.
Page 11 GD32F403xx User Manual 17.4.8. Control register 3 (USART_CTL3) ....................423 17.4.9. Receiver timeout register (USART_RT) ..................424 17.4.10. Status register 1 (USART_STAT1) ....................425 Inter-integrated circuit interface (I2C)..............427 18.1. Overview ......................427 18.2. Characteristics ....................427 18.3. Function overview ....................427 18.3.1. SDA and SCL lines ..........................428 18.3.2.
Page 12 GD32F403xx User Manual 19.3.5. SPI operation modes ...........................460 19.3.6. DMA function............................469 19.3.7. CRC function............................469 19.3.8. SPI interrupts ............................469 19.4. I2S function overview....................471 19.4.1. I2S block diagram ..........................471 19.4.2. I2S signal description...........................471 19.4.3. I2S audio standards ..........................472 19.4.4. I2S clock ..............................480 19.4.5.
Page 13 GD32F403xx User Manual 20.6.4. Single block or multiple block read ....................535 20.6.5. Stream write and stream read (MMC only)..................536 20.6.6. Erase ...............................537 20.6.7. Bus width selection..........................538 20.6.8. Protection management ........................539 20.6.9. Card Lock/Unlock operation .......................539 20.7. Specific operations....................541 20.7.1. SD I/O specific operations ........................541 20.7.2.
Page 14 GD32F403xx User Manual 22.3. Function overview ....................603 22.3.1. Working mode............................603 22.3.2. Communication modes........................604 22.3.3. Data transmission ..........................605 22.3.4. Data reception ............................607 22.3.5. Filtering function............................608 22.3.6. Time-triggered communication ......................612 22.3.7. Communication parameters .......................612 22.3.8. Error flags ...............................614 22.3.9. CAN interrupts ............................614 22.4.
Page 15 GD32F403xx User Manual 23.5.3. USB device function..........................640 23.5.4. OTG function overview ........................641 23.5.5. Data FIFO ...............................642 23.5.6. Operation guide.............................644 23.6. Interrupts ......................649 23.7. Register definition ....................651 23.7.1. Global control and status registers ....................651 23.7.2. Host control and status registers.......................672 23.7.3.
Page 16: List Of Figures
GD32F403xx User Manual List of Figures ® Figure 1-1. The structure of the Cortex -M4 processor ...............27 Figure 1-2. GD32F403xx series system architecture ..............29 Figure 2-1. Process of page erase operation ................42 Figure 2-2. Process of mass erase operation ................43 Figure 2-3.
Page 17 GD32F403xx User Manual Figure 13-1. DAC block diagram ....................219 Figure 13-2. DAC LFSR algorithm .................... 221 Figure 13-3. DAC triangle noise wave ..................221 Figure 14-1. Free watchdog block diagram................233 Figure 14-2. Window watchdog timer block diagram..............238 Figure 14-3.
Page 18 GD32F403xx User Manual Figure 16-38. Output-compare under three modes..............318 Figure 16-39. EAPWM timechart ....................319 Figure 16-40. CAPWM timechart ....................319 Figure 16-41. Restart mode ..................... 321 Figure 16-42. Pause mode....................... 321 Figure 16-43. Event mode ....................... 322 Figure 16-44. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60......323 Figure 16-45.
Page 19 GD32F403xx User Manual Figure 16-13. IrDA SIR ENDEC module..................409 Figure 16-14. IrDA data modulation ..................410 Figure 16-15. ISO7816-3 frame format ..................411 Figure 16-16. USART interrupt mapping diagram..............413 Figure 18-1. I2C module block diagram ..................428 Figure 18-2. Data validation ....................429 Figure 18-3.
Page 20 GD32F403xx User Manual Figure 19-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) ....475 Figure 19-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) ....475 Figure 19-29. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) ....475 Figure 19-30. MSB justified standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ....475 Figure 19-31.
Page 21 GD32F403xx User Manual Figure 20-2. SDIO multiple blocks read operation ..............500 Figure 20-3. SDIO multiple blocks write operation ..............500 Figure 20-4. SDIO sequential read operation ................500 Figure 20-5. SDIO sequential write operation ................501 Figure 20-6. SDIO block diagram ..................... 501 Figure 20-7.
Page 22 GD32F403xx User Manual Figure 22-3. State of transmit mailbox ..................606 Figure 22-4. Reception register ....................607 Figure 22-5. 32-bit filter......................609 Figure 22-6. 16-bit filter......................609 Figure 22-7. 32-bit mask mode filter..................609 Figure 22-8. 16-bit mask mode filter..................609 Figure 22-9.
Page 23: List Of Table
GD32F403xx User Manual List of Table Table 1-1. The interconnection relationship of the AHB interconnect matrix.........27 Table 1-2. Memory map of GD32F403xx devices .................30 Table 1-3. Boot modes ......................34 Table 2-1. GD32F403xx base address and size for flash memory ..........39 Table 2-2.
Page 24 GD32F403xx User Manual Table 16-1. Timers (TIMERx) are divided into five sorts............. 252 Table 16-2. Complementary outputs controlled by parameters ..........269 Table 16-3. Counting direction versus encoder signals............. 272 Table 16-4. Slave mode example table ..................275 Table 16-5. Slave mode example table ..................320 Table 16-6．Slave mode example table ..................
Page 25 GD32F403xx User Manual Table 20-22. Response R7 ....................... 523 Table 20-23. Card status ......................525 Table 20-24. SD status ......................528 Table 20-25. Performance move field ..................529 Table 20-26. AU_SIZE field ...................... 530 Table 20-27. Maximum AU size ....................530 Table 20-28.
Page 26: System And Memory Architecture
GD32F403xx User Manual System and memory architecture The devices of GD32F403xx series are 32-bit general-purpose microcontrollers based on the ® ® ® ® Cortex -M4 processor. The Arm Cortex -M4 processor includes three AHB buses ® ® known as I-Code, D-Code and System buses. All memory accesses of the Arm Cortex processor are executed on the three buses according to the different purposes and the target memory spaces.
Page 27: System Architecture
GD32F403xx User Manual ® Figure 1-1. The structure of the Cortex -M4 processor Cortex-M4 processor Cortex-M4 core Interrupts and Nested Power control Vectored Interrupt Controller Floating Point (NVIC) Unit(FPU) Wake-up Interrupt Controller (WIC) Data Flash Patch Memory Watchpoint Breakpoint Protection And Trace (FPB) Unit(MPU)
Page 28 GD32F403xx User Manual IBUS DBUS SBUS DMA0 DMA1 APB1 APB2 As is shown above, there are several masters connected with the AHB interconnect matrix, ® including IBUS, DBUS, SBUS, DMA0 and DMA1. IBUS is the instruction bus of the Cortex M4 core, which is used f or instruction/vector f etches f rom the Code region (0x0000 0000 ~ ®...
Page 29: Memory Map
GD32F403xx User Manual Figure 1-2. GD32F403xx series system architecture SW/JTAG TPIU POR/ PDR Flash Flash Ibus Memory ARM Cortex-M4 Memory Controller : 168MHz Processor Dbus Fmax:168MHz USBFS SDIO 1.2V NVIC Master Slave AHB Peripherals 8MHz GP DMA 12 chs SRAM SRAM Controller Master...
Page 30: Table 1-2. Memory Map Of Gd32F403Xx Devices
GD32F403xx User Manual ® which is the maximum address range of the Cortex -M4 since the bus address width is 32- ® bit. Additionally, a pre-def ined memory map is provided by the Cortex -M4 processor to reduce the software complexity of repeated implementation of different device vendors. In the ®...
Page 31 GD32F403xx User Manual Pre-defined Address Peripherals Regions 0x4002 0C00 - 0x4002 0FFF Reserved 0x4002 0800 - 0x4002 0BFF Reserved 0x4002 0400 - 0x4002 07FF DMA1 0x4002 0000 - 0x4002 03FF DMA0 0x4001 8400 - 0x4001 FFFF Reserved 0x4001 8000 - 0x4001 83FF SDIO 0x4001 7C00 - 0x4001 7FFF Reserved...
Page 32 GD32F403xx User Manual Pre-defined Address Peripherals Regions 0x4000 C000 - 0x4000 C3FF Reserved 0x4000 8000 - 0x4000 BFFF Reserved 0x4000 7C00 - 0x4000 7FFF Reserved 0x4000 7800 - 0x4000 7BFF Reserved 0x4000 7400 - 0x4000 77FF 0x4000 7000 - 0x4000 73FF 0x4000 6C00 - 0x4000 6FFF 0x4000 6800 - 0x4000 6BFF CAN1...
Page 33: Bit-Banding
GD32F403xx User Manual Pre-defined Address Peripherals Regions 0x2001 8000 - 0x2001 FFFF Reserved 0x2000 0000 - 0x2001 7FFF SRAM 0x1FFF F810 - 0x1FFF FFFF Reserved 0x1FFF F800 - 0x1FFF F80F Option Bytes 0x1FFF B000 - 0x1FFF F7FF Boot loader 0x1FFF 7A10 - 0x1FFF AFFF Reserved 0x1FFF 7800 - 0x1FFF 7A0F Reserved...
Page 34: On-Chip Sram Memory
GD32F403xx User Manual ◼ byte_offset is the number of the byte in the bit-band region that contains the targeted bit. ◼ bit_number is the bit position (0-7) of the targeted bit. For example, to access bit 7 of address 0x2000 0200, the bit-band alias is: bit_word_addr = 0x2200 0000 + (0x200 * 32)+ (7 * 4)= 0x2200 401C (1-2) Writing to address 0x2200 401C will cause bit 7 of address 0x2000 0200 change while a read...
Page 35 GD32F403xx User Manual beginning at 0x0800 0000) or the system memory (original memory space beginning at 0x1FFF F000) is aliased in the boot memory space which begins at the address 0x0000 0000. When the on-chip SRAM, whose memory space is beginning at 0x2000 0000, is selected as the boot source, in the application initialization code, you have to relocate the vector table in SRAM using the NVIC exception table and offset register.
Page 36: Device Electronic Signature
GD32F403xx User Manual 1.5. Device electronic signature The device electronic signature contains memory size inf ormation and the 96-bit unique device ID. It is stored in the information block of the Flash memory. The 96-bit unique device ID is unique f or any device. It can be used as serial numbers, or part of security keys, etc. Memory density information 1.5.1.
Page 37: System Configuration Registers
GD32F403xx User Manual The value is f actory programmed and can never be altered by user. UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Base address: 0x1FFF F7F0 The value is f actory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits...
Page 38 GD32F403xx User Manual 1：Code execution efficiency enhancement Reserved Must be kept at reset value. NOTE: Only bit[7] can be read-modify-write, other bits are not permitted.
Page 39: Flash Memory Controller (Fmc)
GD32F403xx User Manual Flash memory controller (FMC) 2.1. Introduction The f lash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time while CPU executes instructions stored in the f irst 256K bytes of the f lash.
Page 40: Read Operations
GD32F403xx User Manual size Block Name Address Range (bytes) Page 255 0x0807 F800 - 0x0807 FFFF Page 256 0x0808 0000 - 0x0808 0FFF Page 257 0x0808 1000 - 0x0808 1FFF Page 895 0x082F F000 - 0x082F FFFF Informati GD32F403xx Boot loader area 0x1FFF B000- 0x1FFF F7FF 18KB on Block...
Page 41: Page Erase
GD32F403xx User Manual Page erase 2.3.4. The FMC provides a page erase f unction which is used to initialize the contents of a main f lash memory page to a high state. Each page can be erased independently without affecting the contents of other pages.
Page 42: Mass Erase
GD32F403xx User Manual Figure 2-1. Process of page erase operation Start Unlock the Is the LK bit is 0 FMC_CTL Is the BUSY bit is 0 Set the PER bit, Write FMC_ADDR Send the command to FMC by set START bit Is the BUSY bit is 0 Finish For GD32F403xx with f lash more than 512KB, FMC_STAT0 ref lects the operation status of...
Page 43: Figure 2-2. Process Of Mass Erase Operation
GD32F403xx User Manual Set MER bit in FMC_CTL0 register if erase Bank0 o nly. Set MER bit in FMC_CTL1 register if erase Bank1 only. Set MER bits in in FMC_CTL0 register and FMC_CTL1 register if erase entire flash; Send the mass erase command to the FMC by setting the START bit in FMC_CTL register;...
Page 44: Main Flash Programming
GD32F403xx User Manual Main flash programming 2.3.6. The FMC provides a 32-bit word/16-bit half word/bit programming function which is used to modify the main f lash memory contents. The f ollowing steps show the register access sequence of the word programming operation. Unlock the FMC_CTLx registers if necessary;...
Page 45: Option Bytes Erase
GD32F403xx User Manual Figure 2-3. Process of word program operation Start Unlock the Is the LK bit is 0 FMC_CTL Is the BUSY bit is 0 Set the PG bit Perform word/half word write by DBUS Is the BUSY bit is 0 Finish For GD32F403xx with flash more than 512KB, the program procedure applied to bank1 is similar to the procedure applied to bank0.
Page 46: Option Bytes Modify
GD32F403xx User Manual Read and verify the Flash memory if required using a DBUS access. When the operation is executed successful, the ENDF in FMC_STAT0 register is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTL0 register is set. Option bytes modify 2.3.8.
Page 47: Page Erase/Program Protection
GD32F403xx User Manual Address Name Description 0x1fff f802 USER [7:4]: reserved [3]: BB 0: boot from bank1 or bank0 if bank1 is void, when configured boot from main memory 1: boot from bank0, when configured boot from main memory [2]: nRST_STDBY 0: generator a reset instead of entering standby mode 1: no reset when entering standby mode [1]: nRST_DPSLP...
Page 48: Security Protection
GD32F403xx User Manual bit is set and the ERRIE bit is also set to 1 to enable the corresponding interrupt, then the Flash operation error interrupt will be triggered by the FMC to draw the attention of the CPU. The page protection function can be individually enabled by configuring the WP [31:0] bit field to 0 in the option bytes.
Page 49: Fmc Registers
GD32F403xx User Manual 2.4. FMC registers FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved WSCNT[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value.
Page 50: Option Byte Unlock Key Register (Fmc_Obkey)
GD32F403xx User Manual Write KEY[31:0] with keys to unlock FMC_CTL0 register. Option byte unlock key register (FMC_OBKEY) 2.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) OBKEY[31:16] OBKEY[15:0] Bits Fields Descriptions 31:0 OBKEY[31:0] FMC_ CTL0 option bytes operation unlock register These bits are only be written by software.
Page 51: Control Register 0(Fmc_Ctl0)
GD32F403xx User Manual Reserved Must be kept at reset value. PGERR Program error flag bit When program to the flash while it is not 0xFFFF, this bit is set by hardware. The software can clear it by writing 1. Reserved Must be kept at reset value.
Page 52: Address Register 0 (Fmc_Addr0)
GD32F403xx User Manual register. This bit can be set by software. START Send erase command to FMC bit This bit is set by software to send erase command to FMC. This bit is cleared by hardware when the BUSY bit is cleared. OBER Option bytes erase command bit This bit is set or clear by software.
Page 53: Option Byte Status Register (Fmc_Obstat)
GD32F403xx User Manual Bits Fields Descriptions 31:0 ADDR[31:0] Flash erase/program command address bits These bits are configured by software. ADDR bits are the address of flash erase/program command . Option byte status register (FMC_OBSTAT) 2.4.7. Address offset: 0x1C Reset value: 0x0XXX XXXX This register has to be accessed by word(32-bit) Reserved DATA[15:6]...
Page 54: Unlock Key Register 1(Fmc_Key1)
GD32F403xx User Manual Bits Fields Descriptions 31:0 WP[31:0] Store WP of option bytes block after system reset. Unlock key register 1(FMC_KEY1) 2.4.9. Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) KEY[31:16] KEY[15:0] Bits Fields Descriptions 31:0...
Page 55: Control Register 1(Fmc_Ctl1)
GD32F403xx User Manual The software can clear it by writing 1. Reserved Must be kept at reset value. PGERR Program error flag bit When program to the flash while it is not 0xFFFF, this bit is set by hardware. The software can clear it by writing 1. Reserved Must be kept at reset value.
Page 56: Address Register 1 (Fmc_Addr1)
GD32F403xx User Manual This bit is set by software to send erase command to FMC. This bit is cleared by hardware when the BUSY bit is cleared. Reserved Must be kept at reset value Main flash mass erase for bank1 command bit This bit is set or cleared by software.
Page 57: Product Id Register (Fmc_Pid)
GD32F403xx User Manual Resrved Reserved BPEN WSEN Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. BPEN FMC bit program enable register This bit set and reset by software. 0: No effect, write page must check if flash is “FF” 1: Write page donot check the flash is FF.
Page 58: Power Management Unit (Pmu)
GD32F403xx User Manual Power management unit (PMU) 3.1. Overview The power consumption is regarded as one of the most important issues for the devices of GD32F403xx series. Power management unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption.
Page 59: Backup Domain
GD32F403xx User Manual Figure 3-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR WKUP WKUPR BREG BKP PAD WKUPN NRST WKUPF SLEEPING Cortex-M4 FWDGT SLEEPDEEP HXTAL POR / PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain IRC8M IRC40K 3.3V...
Page 60: Vdd
GD32F403xx User Manual wakeup event. After entering the power saving mode for a certain amount of time, the RTC will wake up the device when the time match event occurs. The details of the RTC configuration and operation will be described in the Real-time Clock(RTC).
Page 61: Figure 3-3. Waveform Of The Lvd Threshold
GD32F403xx User Manual Figure 3-2. Waveform of the POR / PDR 600mV hyst RSTTEMPO Power Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register(PMU_CTL). The LVD is enabled by setting the LVDEN bit, and LVDF bit, which in the Power status register(PMU_CS), indicates if V is higher or lower than the LVD threshold.
Page 62: Power Domain
GD32F403xx User Manual Generally, digital circuits are powered by V , while most of analog circuits are powered by . To improve the ADC and DAC conversion accuracy, the independent power supply V is implemented to achieve better performance of analog circuits. V can be externally connected to V through the external filtering circuit that avoids noise on V...
Page 63 GD32F403xx User Manual power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, and PCLK2) or gating the clocks of the unused peripherals or configuring the LDO output voltage by LDOVS bits in PMU_CTL register. The LDOVS bits should be configured only when the PLL is off, and the programmed value is selected to drive 1.2V domain after the PLL opened.
Page 64: Table 3-1. Power Saving Mode Summary
GD32F403xx User Manual Normal-driver / Normal-power: The Deep-sleep mode is not in low-driver mode by configure LDEN to 00 in the PMU_CTL register, and not in low-power mode depending on the LDOLP bit reset in the PMU_CTL register. Normal-driver / Low-power: The Deep-sleep mode is not in low-driver mode by configure LDEN to 00 in the PMU_CTL register.
Page 65 GD32F403xx User Manual Mode Sleep Deep-sleep Standby mode) normal driver mode or low driver mode) SLEEPDEEP = 1 SLEEPDEEP = 1 Configuration SLEEPDEEP = 0 STBMOD = 1, WURST STBMOD = 0 Entry WFI or WFE WFI or WFE WFI or WFE Any interrupt for WFI Any interrupt from EXTI NRST pin...
Page 66: Pmu Registers
GD32F403xx User Manual 3.4. PMU registers PMU base address: 0x4000 7000 Control register (PMU_CTL) 3.4.1. Address offset: 0x00 Reset value: 0x0000 C000 (reset by wakeup from Standby mode) This register can be accessed by half-word(16-bit) or word(32-bit) LDEN[1:0] Reserved HDEN LDOVS[1:0] Reserved LDNP...
Page 67 GD32F403xx User Manual 01: LDO output voltage low mode 10: LDO output voltage mid mode 11: LDO output voltage high mode 13:12 Reserved Must be kept at reset value. LDNP Low-driver mode when use normal power LDO 0: normal driver when use normal power LDO 1: Low-driver mode enabled when LDEN is 11 and use normal power LDO LDLP Low-driver mode when use low power LDO.
Page 68: Control And Status Register (Pmu_Cs)
GD32F403xx User Manual 1: Enter the Standby mode when the Cortex ® -M4 enters SLEEPDEEP mode LDOLP LDO Low Power Mode 0: The LDO operates normally during the Deep-sleep mode 1: The LDO is in low power mode during the Deep-sleep mode Control and status register (PMU_CS) 3.4.2.
Page 69 GD32F403xx User Manual 0: Disable WKUP pin function 1: Enable WKUP pin function If WUPEN is set before entering the Standby mode, a rising edge on the WKUP pin wakes up the system from the Standby mode. As the WKUP pin is active high, the WKUP pin is internally configured to input pull down mode.
Page 70: Backup Registers (Bkp)
GD32F403xx User Manual Backup registers (BKP) 4.1. Introduction The Backup registers are located in the Backup domain that remains powered-on by V even if V power is shut down, they are f orty two 16-bit (84 bytes) registers for data protection of user application data, and the wake-up action f rom Standby mode or system reset do not af f ect these registers.
Page 71 GD32F403xx User Manual and it can be independently enabled on TAMPER pin by setting corresponding TPEN bit in the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is logically ANDed with the TPEN bit, used for tamper detection signal. So the tamper detection conf iguration should be set before enable TAMPER pin.
Page 72: Bkp Registers
GD32F403xx User Manual 4.4. BKP registers Backup data register x (BKP_DATAx) (x= 0..41) 4.4.1. Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) DATA [15:0] Bits Fields Descriptions 15:0 DATA[15:0]...
Page 73: Tamper Pin Control Register (Bkp_Tpctl)
GD32F403xx User Manual This bit is reset only by a Backup domain reset. ASOEN RTC alarm or second signal output enable 0: Disable RTC alarm or second output 1: Enable RTC alarm or second output When enable, the TAMPER pin will output the RTC output. This bit is reset only by a Backup domain reset.
Page 74 GD32F403xx User Manual Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved TPIE Bits Fields Descriptions 15:10 Reserved Must be kept at reset value. Tamper interrupt flag 0: No tamper interrupt occurred 1: A tamper interrupt occurred This bit is reset by writing 1 to the TIR bit or the TPIE bit being 0.
Page 75: Reset And Clock Unit (Rcu)
GD32F403xx User Manual Reset and clock unit (RCU) 5.1. Reset control unit (RCTL) Overview 5.1.1. GD32F403 reset control includes the control of three kinds of reset: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the backup domain.
Page 76: Clock Control Unit (Cctl)
GD32F403xx User Manual source (external or internal reset). Figure 5-1. The system reset circuit NRST Filter POWER_RSTn WWDGT_RSTn min 20 us Sys tem Res et FWDGT_RSTn pulse generator SW_RSTn OB_STDBY_RSTn OB_DPSLP_RSTn Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control register or backup domain power on reset (V or V power on, if both supplies have...
Page 77: Figure 5-2. Clock Tree
GD32F403xx User Manual Figure 5-2. Clock tree CK_IRC48M CK_CTC 48 MHz 48 MHz IRC48M CK48MSEL CK_USBFS USB OTG Prescaler (to USBFS) 1,1.5,2,2.5 SCS[1:0] 3,3.5,4 CK_IRC8M 8 MHz CK_AHB ×2,3,4 CK_EXMC CK_PLL CK_SYS IRC8M 168 MHz max Prescaler 168 MHz max (to EXMC) EXMC enable ÷1,2...512...
Page 78: Characteristics
GD32F403xx User Manual The CTC is clocked by the clock of IRC48M. The IRC48M can be automatically trimmed by CTC unit. The I2S is clocked by the clock of CK_SYS or PLL2*2 which def ined by I2SxSEL bit in RCU_CFG1 register. The RTC is clocked by LXTAL clock or IRC40K clock or HXTAL clock divided by 128 (defined which select by RTCSRC bit in backup domain control register (RCU_BDCTL).
Page 79: Figure 5-4. Hxtal Clock Source In Bypass Mode
GD32F403xx User Manual speed external crystal oscillator is stable. When the HXTAL is powered up, it will not be released f or use until this HXTALSTB bit is set by the hardware. This specific delay period is known as the oscillator “Start-up time”. As the HXTAL becomes stable, an interrupt will be generated if the related interrupt enable bit HXTALSTBIE in the interrupt register RCU_INT is set.
Page 80 GD32F403xx User Manual to indicate if the internal 48M RC oscillator is stable. An interrupt can be generated if the related interrupt enable bit, IRC48MSTBIE, in the RCU_ADDINT register, is set when the IRC48M becomes stable. The IRC48M clock is used for the clocks of USBFS. The f requency accuracy of the IRC48M can be calibrated by the manuf acturer, but its operating frequency is still not enough accurate because the USB need the f requency must between 48MHz with 500ppm accuracy.
Page 81: Table 5-1. Clock Output 0 Source Select
GD32F403xx User Manual f or the real time clock circuit or the free watchdog timer. The IRC40K offers a low cost clock source as no external components are required. The IRC40K RC oscillator can be switched on or off by using the IRC40KEN bit in the reset source/clock register (RCU_RSTSCK). The IRC40KSTB f lag in the reset source/clock register RCU_RSTSCK will indicate if the IRC40K clock is stable.
Page 82: Table 5-2. 1.2V Domain Voltage Selected In Deep-Sleep Mode
GD32F403xx User Manual Clock Source 0 Selection bits Clock Source 1010 EXT1 1011 CK_PLL2 Voltage control The 1.2V domain voltage in Deep-sleep mode can be controlled by DSLPVS[2:0] bit in the Deep-sleep mode voltage register (RCU_DSV). Table 5-2. 1.2V domain voltage selected in deep-sleep mode DSLPVS[2:0] Deep-sleep mode voltage(V)
Page 83: Register Definition
GD32F403xx User Manual 5.3. Register definition RCU base address: 0x4002 1000 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0000 xx83 where x is undefined. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). HXTALB HXTALST HXTALE Reserved PLL2STB PLL2EN PLL1STB PLL1EN PLLSTB Reserved...
Page 84 GD32F403xx User Manual 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock. Reset by hardware when entering Deep-sleep or Standby mode. 0: PLL is switched off 1: PLL is switched on 23:20...
Page 85: Clock Configuration Register 0 (Rcu_Cfg0)
GD32F403xx User Manual Reserved Must be kept at reset value. IRC8MSTB IRC8M Internal 8MHz RC Oscillator stabilization flag Set by hardware to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable 1: IRC8M oscillator is stable IRC8MEN Internal 8MHz RC oscillator enable Set and reset by software.
Page 86 GD32F403xx User Manual 1001: CK_PLL2 clock divided by 2 selected 1010: EXT1 selected 1011: CK_PLL2 clock selected 23:22 USBFSPSC[1:0] USBFS clock prescaler selection Set and reset by software to control the USBFS clock prescaler value. The USBFS clock must be 48MHz. These bits can’t be reset if the USBFS clock is enabled. 000: CK_USBFS = CK_PLL / 1.5 001: CK_USBFS = CK_PLL 010: CK_USBFS = CK_PLL / 2.5...
Page 87 GD32F403xx User Manual 011010: (PLL source clock x 27) 011011: (PLL source clock x 28) 011100: (PLL source clock x 29) 011101: (PLL source clock x 30) 011110: (PLL source clock x 31) 011111: (PLL source clock x 32) 100000: (PLL source clock x 33) 100001: (PLL source clock x 34) …...
Page 88: Clock Interrupt Register (Rcu_Int)
GD32F403xx User Manual 111: (CK_AHB / 16) selected 10:8 APB1PSC[2:0] APB1 prescaler selection Set and reset by software to control the APB1 clock division ratio. Note: The CK_APB1 output frequency must not exceed 84 MHz. 0xx: CK_AHB selected 100: (CK_AHB / 2) selected 101: (CK_AHB / 4) selected 110: (CK_AHB / 8) selected 111: (CK_AHB / 16) selected...
Page 89 GD32F403xx User Manual This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K Reserved CKMIC STBIC STBIC STBIC STBIC STBIC STBIC STBIC PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K PLL2 PLL1 HXTAL IRC8M LXTAL IRC40K Reserved CKMIF STBIE...
Page 90 GD32F403xx User Manual IRC40KSTBIC IRC40K stabilization interrupt clear Write 1 by software to reset the IRC40KSTBIF flag. 0: Not reset IRC40KSTBIF flag 1: Reset IRC40KSTBIF flag Reserved Must be kept at reset value. PLL2STBIE PLL2 stabilization interrupt enable Set and reset by software to enable/disable the PLL2 stabilization interrupt. 0: Disable the PLL2 stabilization interrupt 1: Enable the PLL2 stabilization interrupt PLL1STBIE...
Page 91 GD32F403xx User Manual Set by hardware when the PLL2 is stable and the PLL2STBIE bit is set. Reset when setting the PLL2STBIC bit by software. 0: No PLL2 stabilization interrupt generated 1: PLL2 stabilization interrupt generated PLL1STBIF PLL1 stabilization interrupt flag Set by hardware when the PLL1 is stable and the PLL1STBIE bit is set.
Page 92: Apb2 Reset Register (Rcu_Apb2Rst)
GD32F403xx User Manual APB2 reset register (RCU_APB2RST) 5.3.4. Address offset: 0x0C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). TIMER10 TIMER9 TIMER8 Reserved Reserved ADC2RS USART0 TIMER7R TIMER0R ADC1RS ADC0RS SPI0RST PGRST PFRST PERST PDRST PCRST PBRST...
Page 93 GD32F403xx User Manual 1: Reset the TIMER7 SPI0RST SPI0 reset This bit is set and reset by software. 0: No reset 1: Reset the SPI0 TIMER0RST Timer 0 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER0 ADC1RST ADC1 reset...
Page 94: Apb1 Reset Register (Rcu_Apb1Rst)
GD32F403xx User Manual 0: No reset 1: Reset the GPIO port B PARST GPIO port A reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port A Reserved Must be kept at reset value. AFRST Alternate function I/O reset This bit is set and reset by software.
Page 95 GD32F403xx User Manual 1: Reset backup interface CAN1RST CAN1 reset This bit is set and reset by software. 0: No reset 1: Reset the CAN1 CAN0RST CAN0 reset This bit is set and reset by software. 0: No reset 1: Reset the CAN0 24:23 Reserved Must be kept at reset value.
Page 96 GD32F403xx User Manual 1: Reset the SPI2 SPI1RST SPI1 reset This bit is set and reset by software. 0: No reset 1: Reset the SPI1 13:12 Reserved Must be kept at reset value. WWDGTRST WWDGT reset This bit is set and reset by software. 0: No reset 1: Reset the WWDGT 10:9...
Page 97: Ahb Enable Register (Rcu_Ahben)
GD32F403xx User Manual 0: No reset 1: Reset the TIMER2 Reserved Must be kept at reset value AHB enable register (RCU_AHBEN) 5.3.6. Address offset: 0x14 Reset value: 0x0000 0014 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved USBFSE FMCSPE SRAMSP...
Page 98: Apb2 Enable Register (Rcu_Apb2En)
GD32F403xx User Manual Reserved Must be kept at reset value. FMCSPEN FMC clock enable when sleep mode This bit is set and reset by software to enable/disable FMC clock during Sleep mode. 0: Disabled FMC clock during sleep mode 1: Enabled FMC clock during sleep mode Reserved Must be kept at reset value.
Page 99 GD32F403xx User Manual 1: Enabled TIMER10 clock TIMER9EN TIMER9 clock enable This bit is set and reset by software. 0: Disabled TIMER9 clock 1: Enabled TIMER9 clock TIMER8EN TIMER8 clock enable This bit is set and reset by software. 0: Disabled TIMER8 clock 1: Enabled TIMER8 clock 18:16 Reserved...
Page 100: Apb1 Enable Register (Rcu_Apb1En)
GD32F403xx User Manual PGEN GPIO port G clock enable This bit is set and reset by software. 0: Disabled GPIO port G clock 1: Enabled GPIO port G clock PFEN GPIO port F clock enable This bit is set and reset by software. 0: Disabled GPIO port F clock 1: Enabled GPIO port F clock PEEN...
Page 101 GD32F403xx User Manual UART4E UART3E USART2 USART1 Reserved DACEN PMUEN BKPIEN CAN1EN CAN0EN Reserved I2C1EN I2C0EN Reserved WWDGT TIMER13 TIMER12 TIMER11 TIMER6E TIMER5E TIMER3E TIMER2E SPI2EN SPI1EN Reserved Reserved Reserved Reserved Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. DACEN DAC clock enable This bit is set and reset by software.
Page 102 GD32F403xx User Manual 1: Enabled I2C0 clock UART4EN UART4 clock enable This bit is set and reset by software. 0: Disabled UART4 clock 1: Enabled UART4 clock UART3EN UART3 clock enable This bit is set and reset by software. 0: Disabled UART3 clock 1: Enabled UART3 clock USART2EN USART2 clock enable...
Page 103: Backup Domain Control Register (Rcu_Bdctl)
GD32F403xx User Manual 0: Disabled TIMER12 clock 1: Enabled TIMER12 clock TIMER11EN TIMER11 clock enable This bit is set and reset by software. 0: Disabled TIMER11 clock 1: Enabled TIMER11 clock TIMER6EN TIMER6 clock enable This bit is set and reset by software. 0: Disabled TIMER6 clock 1: Enabled TIMER6 clock TIMER5EN...
Page 104 GD32F403xx User Manual Bits Fields Descriptions 31:17 Reserved Must be kept at reset value. BKPRST Backup domain reset This bit is set and reset by software. 0: No reset 1: Resets Backup domain RTCEN RTC clock enable This bit is set and reset by software. 0: Disabled RTC clock 1: Enabled RTC clock 14:10...
Page 105: Reset Source/Clock Register (Rcu_Rstsck)
GD32F403xx User Manual 0: Disable LXTAL 1: Enable LXTAL Reset source/clock register (RCU_RSTSCK) 5.3.10. Address offset: 0x24 Reset value: 0x0C00 0000, all reset flags reset by power reset only, RSTFC/IRC40KEN reset by system reset. This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). WWDGT FWDGT Reserved RSTFC...
Page 106: Ahb Reset Register (Rcu_Ahbrst)
GD32F403xx User Manual Reset by writing 1 to the RSTFC bit. 0: No power reset generated 1: Power reset generated EPRSTF External pin reset flag Set by hardware when an external pin reset generated. Reset by writing 1 to the RSTFC bit. 0: No external pin reset generated 1: External pin reset generated Reserved...
Page 107: Clock Configuration Register 1 (Rcu_Cfg1)
GD32F403xx User Manual This bit is set and reset by software. 0: No reset 1: Reset the USBFS 11:0 Reserved Must be kept at reset value. Clock configuration register 1 (RCU_CFG1) 5.3.12. Address offset: 0x2C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). PLL2MF[ PLLPRES ADCPSC[...
Page 108 GD32F403xx User Manual 15:12 PLL2MF[3:0] The PLL2 clock multiplication factor These bits and bit 31 of RCU_CFG1 are written by software to define the PLL2 multiplication factor. 000xx: reserve 0010x: reserve 00110: (PLL2 source clock x 8) 00111: (PLL2 source clock x 9) 01000 :(PLL2 source clock x 10) 01001: (PLL2 source clock x 11) 01010: (PLL2 source clock x 12)
Page 109 GD32F403xx User Manual 1110 :(PLL1 source clock x 16) 1111: (PLL1 source clock x 20) PREDV1[3:0] PREDV1 division factor This bit is set and reset by software. These bits can be written when PLL1 and PLL2 are disable. 0000: PREDV1 input source clock not divided 0001: PREDV1 input source clock divided by 2 0010: PREDV1 input source clock divided by 3 0011: PREDV1 input source clock divided by 4...
Page 110: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32F403xx User Manual Deep-sleep mode voltage register (RCU_DSV) 5.3.13. Address offset: 0x34 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit), half-word(16-bit) and word(32-bit). Reserved Reserved DSLPVS[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. DSLPVS[2:0] Deep-sleep mode voltage select These bits are set and reset by software.
Page 111: Additional Clock Interrupt Register (Rcu_Addint)
GD32F403xx User Manual These bits are load automatically at power on. 23:18 Reserved Must be kept at reset value. IRC48MSTB Internal 48MHz RC oscillator clock stabilization flag Set by hardware to indicate if the IRC48M oscillator is stable and ready for use. 0: IRC48M is not stable 1: IRC48M is stable IRC48MEN...
Page 112: Apb1 Additional Reset Register (Rcu_Addapb1Rst)
GD32F403xx User Manual IRC48MSTBIE Internal 48 MHz RC oscillator stabilization interrupt enable Set and reset by software to enable/disable the IRC48M stabilization interrupt 0: Disable the IRC48M stabilization interrupt 1: Enable the IRC48M stabilization interrupt 13:7 Reserved Must be kept at reset value. IRC48MSTBIF IRC48M stabilization interrupt flag Set by hardware when the Internal 48 MHz RC oscillator clock is stable and the...
Page 113 GD32F403xx User Manual Reserved Reserved Reserved Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. CTCEN CTC clock enable This bit is set and reset by software. 0: Disabled CTC clock 1: Enabled CTC clock 26:0 Reserved Must be kept at reset value.
Page 114: Clock Trim Controller (Ctc)
GD32F403xx User Manual Clock trim controller (CTC) 6.1. Overview The Clock Trim Controller (CTC) is used to trim internal 48MHz RC oscillator (IRC48M) automatically by hardware. If using IRC48M clock to USBFS, the IRC48M must be 48 MHz with 500ppm. The internal oscillator without such a high degree of accuracy needs to be trimmed.
Page 115: Ref Sync Pulse Generator
GD32F403xx User Manual Figure 6-1. CTC overview PCLK1 APB1 BUS Register REFSEL REFPSC SWREFPUL 1'b0 CTC_SYNC Prescale (/1,/2,/4, ,/128) LXTAL 1'b0 REF sync pulse CK_IRC48M RLVALUE 48MHz Counter REFDIR REFCAP TRIMVALUE TRIMVALUE Comparator adjustment CKLIM REF sync pulse generator 6.3.1. Firstly, the reference signal source can select GPIO, LXTAL clock output by setting REFSEL bits in CTC_CTL1 register.
Page 116: Frequency Evaluation And Automatically Trim Process
GD32F403xx User Manual zero, and then up- counting to 128 x CKLIM (def ined in CTC_CTL1 register), and then stop until next REF sync pulse detected. If any REF sync pulse detected, the current CTC trim counter value is captured to REFCAP in status register (CTC_STAT), and the counter direction is captured to REFDIR in status register (CTC_STAT).
Page 117: Software Program Guide
GD32F403xx User Manual CTC_CTL0 register is 1. If the AUTOTRIM bit in CTC_CTL0 register set, the TRIMVALUE in CTC_CTL0 register is not changed. ◼ CKLIM ≤ Counter < 3 x CKLIM when REF sync pulse is detected. The CKOKIF in CTC_STAT register set, and an interrupt generated if CKOKIE bit in CTC_CTL0 register is 1.
Page 118 GD32F403xx User Manual CKLIM = ( �� ) × 0.12% ÷ 2 ÷ �� (6-2) �� The typical step size is 0.12%. Where the �� is the f requency of correct clock (IRC48M), �� the �� is the f requency of reference sync pulse. ��...
Page 119: Register Definition
GD32F403xx User Manual 6.4. Register definition CTC base address: 0x4000 C800 Control register 0 (CTC_CTL0) 6.4.1. Address offset: 0x00 Reset value: 0x0000 2000 This register has to be accessed by word (32-bit) Reserved SWREF AUTO CKWARN Reserved TRIMVALUE[5:0] CNTEN Reserved EREFIE ERRIE CKOKIE TRIM...
Page 120: Control Register 1 (Ctc_Ctl1)
GD32F403xx User Manual 0: CTC trim counter disabled 1: CTC trim counter enabled. Reserved Must be kept at reset value. EREFIE EREFIF interrupt enable 0: EREFIF interrupt disable 1: EREFIF interrupt enable ERRIE Error (ERRIF) interrupt enable 0: ERRIF interrupt disable 1: ERRIF interrupt enable CKWARNIE Clock trim warning (CKWARNIF) interrupt enable...
Page 121: Status Register (Ctc_Stat)
GD32F403xx User Manual 00: GPIO selected 01: LXTAL clock selected 10: Reserved, equals 0 selected 11: Reserved, equals 0 selected Reserved Must be kept at reset value. 26:24 REFPSC[2:0] Reference signal source prescaler These bits are set and cleared by software 000: Reference signal not divided 001: Reference signal divided by 2 010: Reference signal divided by 4...
Page 122 GD32F403xx User Manual When a reference sync pulse occurred, the CTC trim counter value is captured to REFCAP bits. REFDIR CTC trim counter direction when reference sync pulse When a reference sync pulse occurred during the counter is working, the CTC trim counter direction is captured to REFDIR bit.
Page 123: Interrupt Clear Register (Ctc_Intc)
GD32F403xx User Manual This bit is set by hardware when an error occurred. If any error of TRIMERR, REFMISS or CKERR occurred, this bit will be set. When the ERRIE in CTC_CTL0 register is set, an interrupt occurs. This bit is cleared by writing 1 to ERRIC bit in CTC_INTC register.
Page 124 GD32F403xx User Manual This bit is written by software and read as 0. Write 1 to clear EREFIF bit in CTC_STAT register. Write 0 is no effect. ERRIC ERRIF interrupt clear bit This bit is written by software and read as 0. Write 1 to clear ERRIF, TRIMERR, REFMISS and CKERR bits in CTC_STAT register.
Page 125: Interrupt/Event Controller (Exti)
GD32F403xx User Manual Interrupt/event controller (EXTI) Overview 7.1. Cortex-M4 integrates the Nested Vectored Interrupt Controller (NVIC) f or efficient exception and interrupts processing. NVIC f acilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processer core. More details about NVIC could referred to the technical reference manual of cortex-M4.
Page 126: Table 7-1. Nvic Exception Types In Cortex-M4
GD32F403xx User Manual Table 7-1. NVIC exception types in Cortex-M4 Vector Exception Type Priority (a) Vector Address Description Number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management Prefetch fault, memory access BusFault Programmable 0x0000_0014...
Page 127 GD32F403xx User Manual Interrupt Vector Number Interrupt Description Vector Address Number IRQ 15 DMA0 channel4 global interrupt 0x0000_007C IRQ 16 DMA0 channel5 global interrupt 0x0000_0080 IRQ 17 DMA0 channel6 global interrupt 0x0000_0084 IRQ 18 ADC0 and ADC1 global interrupt 0x0000_0088 IRQ 19 CAN0 TX interrupts 0x0000_008C...
Page 128 GD32F403xx User Manual Interrupt Vector Number Interrupt Description Vector Address Number TIMER7 channel capture compare IRQ 46 0x0000_00F8 interrupt IRQ 47 ADC2 global interrupt 0x0000_00FC IRQ 48 EXMC global interrupt 0x0000_0100 IRQ 49 SDIO global interrupt 0x0000_0104 IRQ50 reserved 0x0000_0108 IRQ51 SPI2 global interrupt 0x0000_010C...
Page 129: External Interrupt And Event (Exti) Block Diagram
GD32F403xx User Manual External interrupt and event (EXTI) block diagram 7.4. Figure 7-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~18 Edge detector To NVIC Interrupt Mask Control To Wakeup Unit Event Event Mask Generate Control External Interrupt and Event function overview 7.5.
Page 130: Table 7-3. Exti Source
GD32F403xx User Manual Table 7-3. EXTI source EXTI Line Source Number PA0/PB0/PC0/PD0/PE0/PF0/PG0 PA1/PB1/PC1/PD1/PE1/PF1/PG1 PA2/PB2/PC2/PD2/PE2/PF2/PG2 PA3/PB3/PC3/PD3/PE3/PF3/PG3 PA4/PB4/PC4/PD4/PE4/PF4/PG4 PA5/PB5/PC5/PD5/PE5/PF5/PG5 PA6/PB6/PC6/PD6/PE6/PF6/PG6 PA7/PB7/PC7/PD7/PE7/PF7/PG7 PA8/PB8/PC8/PD8/PE8/PF8/PG8 PA9/PB9/PC9/PD9/PE9/PF9/PG9 PA10/PB10/PC10/PD10/PE10/PF10/PG10 PA11/PB11/PC11/PD11/PE11/PF11/PG11 PA12/PB12/PC12/PD12/PE12/PF12/PG12 PA13/PB13/PC13/PD13/PE13/PF13/PG13 PA14/PB14/PC14/PD14/PE14/PF14/PG14 PA15/PB15/PC15/PD15/PE15/PF15/PG15 RTC Alarm USB Wakeup...
Page 131: Exti Register
GD32F403xx User Manual EXTI Register 7.6. EXTI base address: 0x4001 0400 Interrupt enable register (EXTI_INTEN) 7.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10 INTEN9 INTEN8 INTEN7 INTEN6...
Page 132: Rising Edge Trigger Enable Register (Exti_Rten)
GD32F403xx User Manual Rising edge trigger enable register (EXTI_RTEN) 7.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7 RTEN6 RTEN5 RTEN4 RTEN3 RTEN2...
Page 133: Pending Register (Exti_Pd)
GD32F403xx User Manual This register has to be accessed by word(32-bit) Reserved SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:19 Reserved Must be kept at reset value 18: 0 SWIEVx Interrupt/Event software trigger...
Page 134: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32F403xx User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) Overview 8.1. There are up to 112 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15 and PG0 ~ PG15 for the device to implement logic input/output functions.
Page 135: Gpio Pin Configuration
GD32F403xx User Manual Table 8-1. GPIO configuration table Configuration mode CTL[1:0] SPDy: MD[1:0] OCTL don’t care Analog don’t care Input floating Input x 00 Input pull-down Input pull-up x 00: Reserved Push-pull 0 or 1 General purpose x 01: Speed up to 10MHz Output (GPIO) Open-drain 0 or 1...
Page 136: External Interrupt/Event Lines
GD32F403xx User Manual PA13: JTMS / SWDIO in PU mode. PB4: NJTRST in PU mode. PB3: JTDO in Floating mode. The GPIO pins can be configured as inputs or outputs. When the GPIO pins are configured as input pins, all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen.
Page 137: Output Configuration
GD32F403xx User Manual Figure 8-2. Input configuration Output configuration 8.3.5. When GPIO pin is configured as output: ◼ The schmitt trigger input is enabled. ◼ The weak pull-up and pull-down resistors are disabled. ◼ The output buffer is enabled. ◼ Open Drain Mode, the pad outputs low level when setting “0”...
Page 138: Analog Configuration
GD32F403xx User Manual Analog configuration 8.3.6. When GPIO pin is used as analog configuration: ◼ The weak pull-up and pull-down resistors are disabled. ◼ The output buffer is disabled. ◼ The schmitt trigger input is disabled. ◼ The port input status register of this I/O port bit is “0”. Figure 8-4.
Page 139: Gpio Locking Function
GD32F403xx User Manual Figure 8-5. Alternate function configuration Output driver Alternate Function Output Output Control protection I/O pin Alternate Function Input Schmitt trigger Input driver GPIO locking function 8.3.8. The locking mechanism allows the IO configuration to be protected. The protected registers are GPIOx_CTL0, GPIOx_CTL1. It allows the I/O configuration to be frozen by the 32-bit locking register (GPIOx_LOCK).
Page 140: Main Features
GD32F403xx User Manual line source by setting the relevant EXTI source selection register (AFIO_EXTISSx) to trigger an interrupt or event. Main features 8.4.2. ◼ EXTI source selection. ◼ Each pin has up to four alternative functions for configuration. JTAG/SWD alternate function remapping 8.4.3.
Page 141: Adc Af Remapping
GD32F403xx User Manual ADC AF remapping 8.4.4. Refer to AFIO Port Configuration Register 0 (AFIO_ PCF0). Table 8-4. ADC0/ADC1 external trigger rountine conversion AF remapping Register ADC0 ADC1 ADC0 external signal trigger ADC0_ETRGRER_REMA normal conversion is connected P = 0 to EXTI11 ADC0 external signal trigger ADC0_ETRGRER_REMA...
Page 142: Table 8-6. Timer4 Alternate Function Remapping
GD32F403xx User Manual TIMERx_REMAP [1:0](x = 0，1，2) Alternate TIMERx_REMAP(x = 8，9，10，12， function “0”/“00” (no “1”/“01” (partial “10” (partial “11” (full remap) remap) remap) remap) TIMER1_CH0/T PA15 PA15 IMER1_ETI TIMER1_CH1 TIMER1_CH2 PB10 TIMER1_CH3 PB11 TIMER2_CH0 TIMER2_CH1 TIMER2_CH2 TIMER2_CH3 TIMER3_CH0 PD12 TIMER3_CH1 PD13 TIMER3_CH2 PD14...
Page 143: Usart Af Remapping
GD32F403xx User Manual USART AF remapping 8.4.6. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 8-7. USART alternate function remapping Register USART0 USART1 USART2 PA9(USART0_TX) USART0_REMAP = 0 PA10(USART0_RX) PB6(USART0_TX) USART0_REMAP = 1 PB7(USART0_RX) PA0(USART1_CTS) PA1(USART1_RTS) USART1_REMAP = 0 PA2(USART1_TX) PA3(USART1_RX) PA4(USART1_CK)
Page 144: Spi/I2S Af Remapping
GD32F403xx User Manual Table 8-8. I2C0 alternate function remapping Register I2C0_SCL I2C0_SDA I2C0_REMAP = 0 I2C0_REMAP = 1 SPI/I2S AF remapping 8.4.8. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 8-9. SPI/I2S alternate function remapping Register SPI0 SPI2/I2S PA4(SPI0_NSS) PA5(SPI0_SCK) PA6(SPI0_MISO) SPI0_REMAP = 1...
Page 145: Ethernet Af Remapping
GD32F403xx User Manual Register CAN0 CAN1 PB12(CAN1_RX) CAN1_REMAP = “0” PB13(CAN1_TX) PB5(CAN1_RX) CAN1_REMAP = “1” PB6(CAN1_TX) CAN0_RX and CAN0_TX in connectivity line devices; CAN_RX and CAN_TX in other devices with a single CAN interface. This remapping is available only on 100-pin packages. Ethernet AF remapping 8.4.10.
Page 146: Table 8-13. Osc32 Pins Configuration
GD32F403xx User Manual 2. Refer to the note on IO usage restrictions in Section 3.3.1. Table 8-13. OSC32 pins configuration Alternate function LXTAL= ON LXTAL= OFF PC14 OSC32_IN PC14 PC15 OSC32_OUT PC15 The HXTAL oscillator pins OSC_IN/OSC_OUT can be used as general-purpose I/O PD0/PD1. Table 8-14.
Page 147: Register Definition
GD32F403xx User Manual Register definition 8.5. GPIOA base address: 0x4001 0800 GPIOB base address: 0x4001 0C00 GPIOC base address: 0x4001 1000 GPIOD base address: 0x4001 1400 GPIOE base address: 0x4001 1800 GPIOF base address: 0x4001 1C00 GPIOG base address: 0x4001 2000 AFIO base address: 0x4001 0000 Port control register 0 (GPIOx_CTL0, x=A..G) 8.5.1.
Page 148 GD32F403xx User Manual 21:20 MD5[1:0] Pin 5 mode bits These bits are set and cleared by software refer to MD0[1:0]description 19:18 CTL4[1:0] Pin 4 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 17:16 MD4[1:0] Pin 4 mode bits These bits are set and cleared by software refer to MD0[1:0]description 15:14...
Page 149: Port Control Register 1 (Gpiox_Ctl1, X=A
GD32F403xx User Manual MD0[1:0] Pin 0 mode bits These bits are set and cleared by software 00: Input mode (reset state) 01: Output mode ,max speed 10MHz 10: Output mode ,max speed 2 MHz 11: Output mode ,max speed 50MHz Port control register 1 (GPIOx_CTL1, x=A..G) 8.5.2.
Page 150: Port Input Status Register (Gpiox_Istat, X=A
GD32F403xx User Manual These bits are set and cleared by software refer to CTL0[1:0]description 17:16 MD12[1:0] Pin 12 mode bits These bits are set and cleared by software refer to MD0[1:0]description 15:14 CTL11[1:0] Pin 11 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 13:12 MD11[1:0]...
Page 151: Port Output Control Register (Gpiox_Octl, X=A
GD32F403xx User Manual ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT 9 ISTAT 8 ISTAT 7 ISTAT 6 ISTAT 5 ISTAT 4 ISTAT 3 ISTAT 2 ISTAT 1 ISTAT 0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 ISTATy Pin input status(y=0..15)
Page 152: Port Bit Clear Register (Gpiox_Bc, X=A
GD32F403xx User Manual Bits Fields Descriptions 31:16 Pin Clear bit y(y=0..15) These bits are set and cleared by software 0: No action on the corresponding OCTLy bit 1: Clear the corresponding OCTLy bit to 0 15:0 BOPy Pin Set bit y(y=0..15) These bits are set and cleared by software 0: No action on the corresponding OCTLy bit 1: Set the corresponding OCTLy bit to 1...
Page 153: Port Bit Speed Register (Gpiox_ Spd, X=A
GD32F403xx User Manual LK15 LK14 LK13 LK12 LK11 LK10 Bits Fields Descriptions Must be kept at reset value. 31:17 Reserved Lock sequence key It can only be setted using the lock key writing sequence. And it is always readable. 0: GPIO_LOCK register is not locked and the port configuration is not locked. 1: GPIO_LOCK register is locked until an MCU reset..
Page 154: Event Control Register (Afio_Ec)
GD32F403xx User Manual Event control register (AFIO_EC) 8.5.9. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved PORT[2:0] PIN[3:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. Event output enable Set and cleared by software.
Page 155 GD32F403xx User Manual ADC1_ ADC0_ SPI2_ CAN1_ Reserved Reserved SWJ_ CFG[2:0] Reserved Reserved ETRGRER Reserved ETRGRER Reserved REMAP REMAP _REMAP _REMAP PD01_ TIMER3_ USART1_ USART0_ I2C0_ SPI0_ CAN0_REMAP [1:0] TIMER2_REMAP [1:0] Reserved TIMER0_REMAP [1:0] USART2_ REMAP[1:0] REMAP REMAP REMAP REMAP REMAP REMAP Bits...
Page 156 GD32F403xx User Manual Reserved Must be kept at reset value. ADC0_ETRGREG_R ADC 0 external trigger rountine conversion remapping EMAP Set and cleared by software. 17:16 Reserved Must be kept at reset value. PD01_REMAP Port D0/Port D1 mapping on OSC_IN/OSC_OUT This bit is set and cleared by software. 0: Not remap 1: PD0 remapped on OSC_IN, PD1 remapped on OSC_OUT 14:13...
Page 157: Exti Sources Selection Register 0 (Afio_Extiss0)
GD32F403xx User Manual TIMER0_CH2/PE13, TIMER0_CH3/PE14, TIMER0_BKIN/PE15, TIMER0_CH0_ON/PE8, TIMER0_CH1_ON/PE10, TIMER0_CH2_ON/PE12) USART2_REMAP USART2 remapping [1:0] These bits are set and cleared by software. 00: No remap (USART2_TX/PB10, USART2_RX /PB11, USART2_CK/PB12, USART2_CTS/PB13, USART2_RTS/PB14) 01: Partial remap (USART2_TX/PC10, USART2_RX /PC11, USART2_CK/PC12, USART2_CTS/PB13, USART2_RTS/PB14) 10: Not used 11: Full remap (USART2_TX/PD8, USART2_RX /PD9, USART2_CK/PD10, USART2_CTS/PD11, USART2_RTS/PD12) USART1_REMAP...
Page 158 GD32F403xx User Manual EXTI3_SS [3:0] EXTI2_SS [3:0] EXTI1_SS [3:0] EXTI0_SS [3:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI3_SS [3:0] EXTI 3 sources selection 0000: PA3 pin 0001: PB3 pin 0010: PC3 pin 0011: PD3 pin 0100: PE3 pin 0101: PF3 pin 0110: PG3 pin...
Page 159: Exti Sources Selection Register 1 (Afio_Extiss1)
GD32F403xx User Manual Other configurations are reserved. EXTI sources selection register 1 (AFIO_EXTISS1) 8.5.12. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI7_SS [3:0] EXTI6_SS [3:0] EXTI5_SS [3:0] EXTI4_SS [3:0] Bits Fields Descriptions 31:16...
Page 160: Exti Sources Selection Register 2 (Afio_Extiss2)
GD32F403xx User Manual 0110: PG5 pin Other configurations are reserved. EXTI4_SS [3:0] EXTI 4 sources selection 0000: PA4 pin 0001: PB4 pin 0010: PC4 pin 0011: PD4 pin 0100: PE4 pin 0101: PF4 pin 0110: PG4 pin Other configurations are reserved. EXTI sources selection register 2 (AFIO_EXTISS2) 8.5.13.
Page 161: Exti Sources Selection Register 3 (Afio_Extiss3)
GD32F403xx User Manual 0101: PF10 pin 0110: PG10 pin Other configurations are reserved. EXTI9_SS [3:0] EXTI 9 sources selection 0000: PA9 pin 0001: PB9 pin 0010: PC9 pin 0011: PD9 pin 0100: PE9 pin 0101: PF9 pin 0110: PG9 pin Other configurations are reserved.
Page 162: Afio Port Configuration Register 1 (Afio_Pcf1)
GD32F403xx User Manual 0011: PD15 pin 0100: PE15 pin 0101: PF15 pin 0110: PG15 pin Other configurations are reserved. 11:8 EXTI14_SS [3:0] EXTI 14 sources selection 0000: PA14 pin 0001: PB14 pin 0010: PC14 pin 0011: PD14 pin 0100: PE14 pin 0101: PF14 pin 0110: PG14 pin Other configurations are reserved.
Page 163 GD32F403xx User Manual EXMC_NA TIMER13_R TIMER12_ TIMER10_ TIMER9_R TIMER8_R Reserved CTC_REMAP [1:0] Reserved EMAP REMAP REMAP EMAP EMAP Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:11 CTC_REMAP [1:0] CTC remapping These bits are set and cleared by software, they control the mapping of the CTC_SYNC alternate function onto the GPIO ports .
Page 164: Io Compensation Control Register (Afio_Cpsctl)
GD32F403xx User Manual TIMER8_REMAP TIMER8 remapping This bit is set and cleared by software, it controls the mapping of the TIMER8_CH0 and TIMER8_CH1 alternate function onto the GPIO ports 0: No remap (TIMER8_CH0 on PA2 and TIMER8_CH1 on PA3) 1: Remap (PF6) (TIMER8_CH0 on PE5 and TIMER8_CH1 on PE6) Reserved Must be kept at reset value.
Page 165: Cyclic Redundancy Checks Management Unit (Crc)
GD32F403xx User Manual Cyclic redundancy checks management unit (CRC) 9.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 32 bit CRC code with fixed polynomial. 9.2.
Page 166: Function Overview
GD32F403xx User Manual Figure 9-1. Block diagram of CRC calculation unit Data Input Input Data Register (32 bit) CRC Management Unit Fixed polynomial 0x4C11DB7 Interface Data Output Output Data Register (32 bit) Data Access Free Purpose Register (8 bit) 9.3. Function overview ◼...
Page 167: Register Definition
GD32F403xx User Manual 9.4. Register definition CRC base address: 0x4002 3000 Data register (CRC_DATA) 9.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA [31:16] DATA [15:0] Bits Fields Descriptions 31:0 DATA [31:0] CRC calculation result bits Software writes and reads.
Page 168: Control Register (Crc_Ctl)
GD32F403xx User Manual These bits are unrelated with CRC calculation. This byte can be used for any goal by any other peripheral. The CRC_CTL register will take no effect to the byte. Control register (CRC_CTL) 9.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 169: Direct Memory Access Controller (Dma)
GD32F403xx User Manual Direct memory access controller (DMA) Overview 10.1. The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention f rom the CPU, thereby f reeing up bandwidth f or other system f unctions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions.
Page 170: Block Diagram
GD32F403xx User Manual Block diagram 10.3. Figure 10-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management Peripheral control Arbiter state &...
Page 171: Table 10-1. Dma Transfer Operation
GD32F403xx User Manual Table 10-1. DMA transfer operation Transfer size Transfer operations Source Destination Source Destination 1: Read B3B2B1B0[31:0] @0x0 1: Write B3B2B1B0[31:0] @0x0 2: Read B7B6B5B4[31:0] @0x4 2: Write B7B6B5B4[31:0] @0x4 32 bits 32 bits 3: Read BBBAB9B8[31:0] @0x8 3: Write BBBAB9B8[31:0] @0x8 4: Read BFBEBDBC[31:0] @0xC 4: Write BFBEBDBC[31:0] @0xC...
Page 172: Peripheral Handshake
GD32F403xx User Manual Peripheral handshake 10.4.2. To ensure a well-organized and efficient data transfer, a handshake mechanism is introduced between the DMA and peripherals, including a request signal and a acknowledge signal: ◼ Request signal asserted by peripheral to DMA controller, indicating that the peripheral is ready to transmit or receive data ◼...
Page 173: Circular Mode
GD32F403xx User Manual base address registers (DMA_CHxPADDR, DMA_CHxMADDR). In the increasing mode, the next address is equal to the current address plus 1 or 2 or 4, depending on the transfer data width. Circular mode 10.4.5. Circular mode is implemented to handle continue peripheral requests (for example, ADC scan mode).
Page 174: Dma Request Mapping
GD32F403xx User Manual including full transfer f inish, half transfer finish, and transfer error. Each interrupt event has a dedicated flag bit in the DMA_INTF register, a dedicated clear bit in the DMA_INTC register, and a dedicated enable bit in the DMA_CHxCTL register. The relationship is described in the following Table 10-2.
Page 175: Figure 10-4. Dma0 Request Mapping
GD32F403xx User Manual Figure 10-4. DMA0 request mapping Hardware priority ADC0 high TIMER3_CH0 Channel 0 SPI0_RX USART2_TX TIMER0_CH0 Channel 1 TIMER2_CH2 SPI0_TX USART2_RX TIMER0_CH1 Channel 2 TIMER2_CH3 TIMER2_UP SPI1/I2S1_RX USART0_TX I2C1_TX TIMER0_CH3 Channel 3 TIMER0_TG TIMER0_CMT TIMER3_CH1 SPI1/I2S1_TX USART0_RX I2C1_RX Channel 4 TIMER0_UP TIMER3_CH2...
Page 176: Figure 10-5. Dma1 Request Mapping
GD32F403xx User Manual Periphera Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 ● USART USART2_TX USART2_RX USART0_TX USART0_RX USART1_RX USART1_TX ● ● ● I2C1_TX I2C1_RX I2C0_TX I2C0_RX Table 10-3. DMA0 requests for each channel Figure 10-5.
Page 177 GD32F403xx User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 ● ● ● ● SDIO SDIO...
Page 178: Register Definition
GD32F403xx User Manual Register definition 10.5. DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Note: For DMA1 having 5 channels, all bits related to channel 5 and channel 6 in the f ollowing registers are not suitable for DMA1. Interrupt flag register (DMA_INTF) 10.5.1.
Page 179: Interrupt Flag Clear Register (Dma_Intc)
GD32F403xx User Manual Interrupt flag clear register (DMA_INTC) 10.5.2. Address offset: 0x04 Reset value: 0x0000 0000 Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0 GIFC0...
Page 180 GD32F403xx User Manual Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. Memory to Memory Mode Software set and cleared 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level...
Page 181: Channel X Counter Register (Dma_Chxcnt)
GD32F403xx User Manual Circular mode enable CMEN Software set and cleared 0: Disable circular mode 1: Enable circular mode This bit can not be written when CHEN is ‘1’. Transfer direction Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’.
Page 182: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32F403xx User Manual 31:16 Reserved Must be kept at reset value. 15:0 CNT[15:0] Transfer counter These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. This register indicates how many transfers remain. Once the channel is enabled, it is read-only, and decreases after each DMA transfer.
Page 183 GD32F403xx User Manual Bits Fields Descriptions 31:0 MADDR[31:0] Memory base address These bits can not be written when CHEN in the DMA_CHxCTL register is ‘1’. When MWIDTH in the DMA_CHxCTL register is 01 (16-bit), the LSB of these bits is ignored.
Page 184: Debug (Dbg)
GD32F403xx User Manual Debug (DBG) Introduction 11.1. The GD32F403xx series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the Arm CoreSightTM module together with a ® daisy chained standard TAP controller. Debug and trace functions are integrated into the Arm ®...
Page 185: Jtag Daisy Chained Structure
GD32F403xx User Manual PA15 : JTDI PA14 : JTCK/SWCLK PA13 : JTMS/SWDIO : NJTRST : JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB4 can be used to other GPIO functions. (NJTRST tied to 1 by hardware).
Page 186: Debug Support For Timer, I2C, Wwdgt, Fwdgt And Can
GD32F403xx User Manual When SLP_HOLD bit in DBG control register 0 (DBG_CTL0) is set and entering the sleep mode, the clock of AHB bus for CPU is not closed, and the debugger can debug in sleep mode. Debug support for TIMER, I2C, WWDGT, FWDGT and CAN 11.3.2.
Page 187: Dbg Registers
GD32F403xx User Manual 11.4. DBG registers DEBUG base address: 0xE0042000U ID code register (DBG_ID) 11.4.1. Address: 0xE004 2000 Read only This register has to be accessed by word(32-bit) ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software, These bits are unchanged constant Control register 0 (DBG_CTL0) 11.4.2.
Page 188 GD32F403xx User Manual TIMER9_HOLD TIMER 9 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER 9 counter for debug when core halted TIMER8_HOLD TIMER 8 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER 8 counter for debug when core halted TIMER13_HOLD...
Page 189 GD32F403xx User Manual I2C1_HOLD I2C1 hold bit This bit is set and reset by software 0: no effect 1: hold the I2C1 SMBUS timeout for debug when core halted I2C0_HOLD I2C0 hold bit This bit is set and reset by software 0: no effect 1: hold the I2C0 SMBUS timeout for debug when core halted CAN0_HOLD...
Page 190 GD32F403xx User Manual Reserved Must be kept at reset value STB_HOLD Standby mode hold register This bit is set and reset by software 0: no effect 1: At the standby mode, the clock of AHB bus and system clock are provided by CK_IRC8M, a system reset generated when exit standby mode DSLP_HOLD Deep-sleep mode hold register...
Page 191: Analog-To-Digital Converter (Adc)
GD32F403xx User Manual Analog-to-digital converter (ADC) Overview 12.1. A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals f rom 16 external channels and 2 internal channels. The 18 ADC sampling channels all support a variety of operation modes. After sampling and conversion, the conversion results can be stored in the corresponding data registers according to the least significant bit alignment or the most significant bit alignment.
Page 192: Pins And Internal Signals
GD32F403xx User Manual ◼ Module supply requirements: 2.6V to 3.6V, and typical power supply voltage is 3.3V. ◼ ≤V ≤V Channel input voltage range: V REFN REFP 12.3. Pins and internal signals Figure 12-1. ADC module block diagram shows the ADC block diagram. Table 12-1.
Page 193: Functional Overview
GD32F403xx User Manual 12.4. Functional overview Figure 12-1. ADC module block diagram DMA request Trig select routine sequence Interrupt Interrupt Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO ADC_IN15 routine data registers SAR ADC Over sampler 6~12bit （16 bits） SENSE REFINT TOVS...
Page 194: Adc Clock
GD32F403xx User Manual Set CLB=1. Wait until CLB=0. ADC clock 12.4.2. The CK_ADC clock is synchronous with the AHB and APB2 clock and provided by the clock controller. ADC clock can be divided and configured by RCU controller. 12.4.3. ADC enable The ADCON bit on the ADC_CTL1 register is the enable switch of the ADC module.
Page 195: Figure 12-3. Continuous Operation Mode
GD32F403xx User Manual Software procedure for single operation mode of a routine channel: Make sure the DISRC, SM in the ADC_CTL0 register and CTN bit in the ADC_CTL1 register are reset. Conf igure RSQ0 with the analog channel number. Conf igure ADC_SAMPTx register. Conf igure ETERC and ETSRC bits in the ADC_CTL1 register if in need .
Page 196: Figure 12-4. Scan Operation Mode, Continuous Disable
GD32F403xx User Manual Scan operation mode The scan operation mode will be enabled when SM bit in the ADC_CTL0 register is set. In this mode, the ADC performs conversion on all channels with a specific routine sequence specified in the ADC_RSQ0~ADC_RSQ2 registers. When the ADCON has been set high, the ADC samples and converts specified channels one by one in the routine sequence till the end of the sequence , once the corresponding software trigger or external trigger is active.
Page 197: Conversion Result Threshold Monitor Function
GD32F403xx User Manual the next n channels configured in the ADC_RSQ0~ADC_RSQ2 registers until all the channels of routine sequence are done. The EOC will be set after every circle of the routine sequence. An interrupt will be generated if the EOCIE bit is set. Figure 12-6.
Page 198: Sample Time Configuration
GD32F403xx User Manual Figure 12-7. 12-bit Data storage mode 6-bit resolution data alignment is different from 12-bit/10-bit/8-bit resolution data alignment, shown as Figure 12-8. 6-bit Data storage mode. Figure 12-8. 6-bit Data storage mode 12.4.8. Sample time configuration The number of CK_ADC cycles which is used to sample the input voltage can be specified by the SPTn[2:0] bits in the ADC_SAMPT0 and ADC_SAMPT1 registers.
Page 199: Dma Request
GD32F403xx User Manual ETSRC[2:0] Trigger Source Trigger Type TIMER2_TRGO TIMER3_CH3 EXTI11/ TIMER7_TRGO Software trigger SWRCST Table 12-4. External trigger source for ADC2 ETSRC[2:0] Trigger Source Trigger Type TIMER2_CH0 reserved TIMER0_CH2 Hardware rigger TIMER7_CH0 TIMER7_TRGO reserved reserved Software trigger SWRCST DMA request 12.4.10.
Page 200: Programmable Resolution (Dres)
GD32F403xx User Manual for the channel. Enable the temperature sensor by setting the TSVREN bit in the ADC control register 1 (ADC_CTL1). Start the ADC conversion by setting the ADCON bit or by the triggers. Read the internal temperature sensor output voltage(V ), and get the temperature temperature with the following equation:...
Page 201: Figure 12-9. 20-Bit To 16-Bit Result Truncation
GD32F403xx User Manual Summation units can produce up to 20 bits (256 x 12-bit), which is first shifted right. The upper bits of the result are then truncated, keeping only the 16 least significant bits rounded to the nearest value using the least significant bits left apart by the shifting, before being finally transferred into the data register.
Page 202: Adc Sync Mode
GD32F403xx User Manual mpling OVSS= shift shift shift shift shift shift shift shift ratio data 0000 OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= OVSS= 0001 0010 0011 0100 0101 0110 0111 1000 0x1FFE 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0x003F 0x001F 0x3FFC 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0x003F 0x7FF8 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF 0x007F 0xFFF0 0xFFF0 0x7FF8 0x3FFC 0x1FFE 0x0FFF 0x07FF 0x03FF 0x01FF 0x00FF...
Page 203: Free Mode
GD32F403xx User Manual Figure 12-11. ADC sync block diagram Routine Routine data registers （16 bits） channels ADC1 (slave) ADC_IN0 ADC_IN1 GPIO Routine Routine data registers （16 bits） channels ADC_IN15 SENSE REFINT Syncl mode control ADC0 EXTI11 (master) Routine trigger mux Free mode 12.5.1.
Page 204: Routine Follow-Up Fast Mode
GD32F403xx User Manual 2. Two channels sampled by two ADCs at the same time should be configured with the same sampling time. Figure 12-12. Routine parallel mode on 10 channels Routine follow-up fast mode 12.5.3. The routine f ollow-up fast mode is applicable to sample the same channel of two ADCs. The source of external trigger comes from the ADC0 routine channel (selected by the ETSRC[2:0] bits in the ADC_CTL1 register).
Page 205: Adc Interrupts
GD32F403xx User Manual Continuous mode can’t be used in this mode, because it continuously converts the routine channel. The behavior of follow-up slow mode shows in the Figure 12-14. Routine follow- up slow mode. After an EOC interrupt is generated by ADC0 (if EOCIE bit is set), we can use a 32-bit DMA, which transfers to SRAM the ADC_RDATA register containing the ADC1 converted data in the [31: 16] bits field and the ADC0 converted data in the [15: 0] bits field.
Page 206: Adc Registers
GD32F403xx User Manual 12.7. ADC registers ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 ADC2 base address: 0x4001 3C00 Status register (ADC_STAT) 12.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved STRC...
Page 207: Control Register 0 (Adc_Ctl0)
GD32F403xx User Manual Control register 0 (ADC_CTL0) 12.7.2. Address offset: 0x04 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RWDEN Reserved SYNCM[3:0] DISNUM[2:0] Reserved DISRC Reserved WDSC Reserved WDEIE EOCIE WDCHSEL[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value.
Page 208: Control Register 1 (Adc_Ctl1)
GD32F403xx User Manual 1: A single channel has analog watchdog function Scan mode 0: Scan operation mode disable 1: Scan operation mode enable Reserved Must be kept at reset value. WDEIE Interrupt enable for WDE 0: Interrupt disable 1: Interrupt enable EOCIE Interrupt enable for EOC 0: Interrupt disable...
Page 209 GD32F403xx User Manual This register has to be accessed by word(32-bit) Reserved TSVREN SWRCST Reserved ETERC ETSRC[2:0] Reserved Reserved Reserved. Reserved RSTCLB ADCON Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. TSVREN Channel 16 and 17 enable of ADC0. 0: Channel 16 and 17 of ADC0 disable 1: Channel 16 and 17 of ADC0 enable SWRCST...
Page 210: Sample Time Register 0 (Adc_Sampt0)
GD32F403xx User Manual 16:12 Reserved Must be kept at reset value Data alignment 0: LSB alignment 1: MSB alignment 10:9 Reserved Must be kept at reset value. DMA request enable. 0: DMA request disable 1: DMA request enable Reserved Must be kept at reset value. RSTCLB Reset calibration This bit is set by software and cleared by hardware after the calibration registers...
Page 211: Sample Time Register 1 (Adc_Sampt1)
GD32F403xx User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value 23:21 SPT17[2:0] refer to SPT10[2:0] description 20:18 SPT16[2:0] refer to SPT10[2:0] description 17:15 SPT15[2:0] refer to SPT10[2:0] description 14:12 SPT14[2:0] refer to SPT10[2:0] description 11:9 SPT13[2:0] refer to SPT10[2:0] description SPT12[2:0] refer to SPT10[2:0] description...
Page 212: Watchdog High Threshold Register (Adc_Wdht)
GD32F403xx User Manual 20:18 SPT6[2:0] refer to SPT0[2:0] description 17:15 SPT5[2:0] refer to SPT0[2:0] description 14:12 SPT4[2:0] refer to SPT0[2:0] description 11:9 SPT3[2:0] refer to SPT0[2:0] description SPT2[2:0] refer to SPT0[2:0] description SPT1[2:0] refer to SPT0[2:0] description SPT0[2:0] Channel sample time 000: channel sampling time is 1.5 cycles 001: channel sampling time is 7.5 cycles 010: channel sampling time is 13.5 cycles...
Page 213: Routine Sequence Register 0 (Adc_Rsq0)
GD32F403xx User Manual Reserved Reserved WDLT[11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 WDLT[11:0] Low threshold for analog watchdog These bits define the low threshold for the analog watchdog. Routine sequence register 0 (ADC_RSQ0) 12.7.8. Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
Page 214: Routine Sequence Register 2 (Adc_Rsq2)
GD32F403xx User Manual Reserved RSQ11[4:0] RSQ10[4:0] RSQ9[4:1] RSQ9[0] RSQ8[4:0] RSQ7[4:0] RSQ6[4:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:25 RSQ11[4:0] refer to RSQ0[4:0] description 24:20 RSQ10[4:0] refer to RSQ0[4:0] description 19:15 RSQ9[4:0] refer to RSQ0[4:0] description 14:10 RSQ8[4:0] refer to RSQ0[4:0] description...
Page 215: Routine Data Register (Adc_Rdata)
GD32F403xx User Manual conversion in the routine sequence. Routine data register (ADC_RDATA) 12.7.11. Address offset: 0x4C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) ADC1RDTR[15:0] RDATA[15:0] Bits Fields Descriptions 31:16 ADC1RDTR[15:0] ADC1 routine channel data In sync mode, these bits contain the routine data of ADC1. These bits are only used in ADC0.
Page 216 GD32F403xx User Manual 11:10 Reserved Must be kept at reset value. TOVS Triggered Oversampling This bit is set and cleared by software. 0: All oversampled conversions for a channel are done consecutively after a trigger 1: Each conversion needs a trigger for a oversampled channel and the number of triggers is determined by the oversampling ratio(OVSR[2:0]).
Page 217 GD32F403xx User Manual ensures that no conversion is in progress).
Page 218: Digital-To-Analog Converter (Dac)
GD32F403xx User Manual Digital-to-analog converter (DAC) Introduction 13.1. The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability.
Page 219: Function Description
GD32F403xx User Manual Figure 13-1. DAC block diagram DAC control register DTSELx[2:0] DBOFFx TIMER5_TRGO TIMER2_TRGO TIMER6_TRGO TIMER3_TRGO EXTI9 Buff SWTRx DAC_OUTx Control logic 12-bit 12-bit 12-bit Table 13-1. DAC I/O description Name Description Signal type Analog power supply Power Ground for analog power supply Power reference voltage Analog Input...
Page 220: Dac Data Configuration
GD32F403xx User Manual in the DAC_CTL register. DAC data configuration 13.3.3. The 12-bit DAC holding data (DACx_DH) can be configured by writing any one of these registers (DACx_R12DH, DACx_L12DH or DACx_R8DH). When the data is loaded into DACx_R8DH register, only the MSB 8 bits are configurable, the LS B 4 bits are fored to 4’b0000.
Page 221: Dac Output Calculate
GD32F403xx User Manual LFSR noise wave mode: there is a Linear Feedback Shift Register (LFSR) in the DAC control logic, it controls the LFSR noise signal which is added to the DACx_DH value. When the configured DAC noise wave bit width is less than 12, the noise signal equals to the LSB DWBWx bits of the LFSR register, while the MSB bits are masked.
Page 222: Dac Concurrent Conversion
GD32F403xx User Manual bits of the DAC_CTL register. When an external hardware trigger (not a software trigger) occurs ,A DMA request will be generated by DAC. DAC concurrent conversion 13.3.9. In order to maximize the utilization of the bus bandwidth, we can make the two DACs work at the same time using concurrent mode.
Page 223: Dac Registers
GD32F403xx User Manual DAC registers 13.4. DAC base address: 0x4000 7400 Control register (DAC_CTL) 13.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DDMAEN1 DWBW1[3:0] DWM1[1:0] DTSEL1[2:0] DTEN1 DBOFF1 DEN1 Reserved DDMAEN0 DWBW0[3:0] DWM0[1:0] DTSEL0[2:0]...
Page 224 GD32F403xx User Manual 00: wave disabled 01: LFSR noise mode 1x: Triangle noise mode 21:19 DTSEL1[2:0] DAC1 trigger selection These bits select the external trigger of DAC1 when DTEN1=1. 000: TIMER5 TRGO 001: TIMER2 TRGO 010: TIMER6 TRGO 011: Reserved 100: Reserved 101: TIMER3 TRGO 110: EXTI line 9...
Page 225: Software Trigger Register (Dac_Swt)
GD32F403xx User Manual 1001: The bit width of the wave signal is 10 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12 DWM0[1:0] DAC0 noise wave mode These bits specify the mode selection of the noise wave signal of DAC0 when external trigger of DAC0 is enabled (DTEN0=1).
Page 226: Dac0 12-Bit Right-Aligned Data Holding Register (Dac0_R12Dh)
GD32F403xx User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SWTR1 DAC1 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled SWTR0 DAC0 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled DAC0 12-bit right-aligned data holding register (DAC0_R12DH) 13.4.3.
Page 227: Dac0 8-Bit Right-Aligned Data Holding Register (Dac0_R8Dh)
GD32F403xx User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value DAC0 8-bit right-aligned data holding register (DAC0_R8DH) 13.4.5.
Page 228: Dac1 12-Bit Left-Aligned Data Holding Register (Dac1_L12Dh)
GD32F403xx User Manual These bits specify the data that is to be converted by DAC1. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) 13.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DH[11:0] Reserved Bits Fields...
Page 229: Dac Concurrent Mode 12-Bit Right-Aligned Data Holding Register (Dacc_R12Dh)
GD32F403xx User Manual DAC concurrent mode 12-bit right-aligned data holding register 13.4.9. (DACC_R12DH) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DH[11:0] Reserved DAC0_DH[11:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:16 DAC1_DH[11:0] DAC1 12-bit right-aligned data...
Page 230: Dac Concurrent Mode 8-Bit Right-Aligned Data Holding Register (Dacc_R8Dh)
GD32F403xx User Manual 19:16 Reserved Must be kept at reset value. 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value. DAC concurrent mode 8-bit right-aligned data holding register 13.4.11.
Page 231: Dac1 Data Output Register (Dac1_Do)
GD32F403xx User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DAC0_DO [11:0] DAC0 data output These bits, which are read only, reflect the data that is being converted by DAC0. DAC1 data output register (DAC1_DO) 13.4.13.
Page 232: Watchdog Timer (Wdgt)
GD32F403xx User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system f ailures due to software malfunctions. There are two watchdog timer peripherals in the chip: f ree watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy.
Page 233: Figure 14-1. Free Watchdog Block Diagram
GD32F403xx User Manual Figure 14-1. Free watchdog block diagram The f ree watchdog is enabled by writing the value (0xCCCC) to the control register (FWDGT_CTL), then the counter starts counting down. When the counter reaches the value (0x000), there will be a reset. The counter can be reloaded by writing the value (0xAAAA) to the FWDGT_CTL register at anytime.
Page 234 GD32F403xx User Manual Min timeout (ms) Max timeout (ms) Prescaler divider PSC[2:0] bits RLD[11:0]=0x000 RLD[11:0]=0xFFF 1 / 256 110 or 111 0.025 26208.025 The FWDGT timeout can be more accurate by calibrating the IRC40K. Note: When after the execution of watchdog reload operation, if the MCU needs enter the deepsleep / standby mode immediately, more than 3 IRC40K clock intervals must be inserted in the middle of reload and deepsleep / standby mode commands by software setting.
Page 235: Register Definition
GD32F403xx User Manual Register definition 14.1.4. FWDGT base address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access. Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
Page 236 GD32F403xx User Manual 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit is reset before changing the prescaler value.
Page 237 GD32F403xx User Manual Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free watchdog timer counter reload value update. During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid. This bit is reset by hardware after the update operation of FWDGT_RLD register.
Page 238: Window Watchdog Timer (Wwdgt)
GD32F403xx User Manual 14.2. Window watchdog timer (WWDGT) Overview 14.2.1. The window watchdog timer (WWDGT) is used to detect system f ailures due to software malf unctions. After the window watchdog timer starts, the value of down counter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit has been cleared).
Page 239: Figure 14-3. Window Watchdog Timing Diagram
GD32F403xx User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. When window watchdog timer is enabled, the counter counts down all the time, the conf igured value of the counter should be greater than 0x3F (it implies that the CNT[6] bit should be set).
Page 240: Table 14-2. Min/Max Timeout Value At 84 Mhz
GD32F403xx User Manual Table 14-2. Min/max timeout value at 84 MHz (f PCLK1 Min timeout value Max timeout value Prescaler divider PSC[1:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 48.76 μs 1 / 1 3.12 ms 97.52 μs 1 / 2 6.24 ms 195.04 μs 1 / 4 12.48 ms 390.08 μs...
Page 241: Register Definition
GD32F403xx User Manual Register definition 14.2.4. WWDGT base address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value.
Page 242 GD32F403xx User Manual PSC[1:0] Prescaler. The time base of the watchdog timer counter 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4 11: (PCLK1 / 4096) / 8 WIN[6:0] The Window value. A reset occurs if the watchdog counter (CNT bits in WWDGT_CTL) is written when the value of the watchdog counter is greater than the Window value.
Page 243: Real-Time Clock(Rtc)
GD32F403xx User Manual Real-time Clock(RTC) Overview 15.1. The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains. The ones in the Backup Domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register. That means the RTC settings and time are kept when the device resets or wakes up from Standby mode.
Page 244: Rtc Reset
GD32F403xx User Manual the RTC will generate an alarm interrupt when the system time equals to the alarm time (stored in the RTC_ALRMH/L register). Figure 15-1. Block diagram of RTC APB1 BUS PCLK1 APB interface RTC_Second SCIF HXTAL/128 SCIE RTC Interrupt RTCCLK RTC_Overflow SC_CLK...
Page 245: Rtc Flag Assertion
GD32F403xx User Manual bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation executes when the peripheral exit configuration mode, and it takes at least three RTCCLK cycles to complete. The value of the LWOFF bit in the RTC_CTL register sets to ‘1’, if the write operation finished.
Page 246 GD32F403xx User Manual RTC second and overflow waveform example (RTC_PSC= 3) Figure 15-3.
Page 247: Rtc Register
GD32F403xx User Manual RTC Register 15.4. RTC base address: 0x4000 2800 RTC interrupt enable register(RTC_INTEN) 15.4.1. Address offset : 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved OVIE ALRMIE SCIE Bits Fields Descriptions Must be kept at reset...
Page 248: Rtc Prescaler High Register (Rtc_Psch)
GD32F403xx User Manual Must be kept at reset value. 31:6 Reserved LWOFF Last write operation finished flag 0: Last write operation on RTC registers did not finished. 1: Last write operation on RTC registers finished. Configuration mode flag 0: Exit configuration mode. 1: Enter configuration mode.
Page 249: Rtc Prescaler Low Register(Rtc_Pscl)
GD32F403xx User Manual RTC prescaler value high PSC[19:16] RTC prescaler low register(RTC_PSCL) 15.4.4. Address offset: 0x0C Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved PSC[15:0] Bits Fields Descriptions Must be kept at reset value. 31:16 Reserved RTC prescaler value low...
Page 250: Rtc Counter High Register(Rtc_Cnth)
GD32F403xx User Manual Reserved DIV[15:0] Bits Fields Descriptions Must be kept at reset value. 31:16 Reserved 15:0 DIV[15:0] RTC divider value low The RTC divider register is reloaded by hardware when the RTC prescaler or RTC counter register updated. RTC counter high register(RTC_CNTH) 15.4.7.
Page 251: Rtc Alarm High Register(Rtc_Alrmh)
GD32F403xx User Manual RTC counter value low 15:0 CNT[15:0] RTC alarm high register(RTC_ALRMH) 15.4.9. Address offset: 0x20 Reset value: 0xFFFF This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ALRM[31:16] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. RTC alarm value high 15:0 ALRM[31:16]...
Page 252: Timers(Timerx)
GD32F403xx User Manual Timers(TIMERx) Table 16-1. Timers (TIMERx) are divided into five sorts TIMER TIMER0/7 TIMER2~3 TIMER8/11 TIMER9/10/12/13 TIMER5/6 TYPE Advanced General-L0 General-L1 General-L2 Basic Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit Counter 16-bit 16-bit 16-bit 16-bit 16-bit UP,DOWN, UP,DOWN, Count mode UP ONLY UP ONLY UP ONLY...
Page 253: Advanced Timer (Timerx, X=0, 7)
GD32F403xx User Manual 16.1. Advanced timer (TIMERx, x=0, 7) Overview 16.1.1. The advanced timer module (Timer0&Timer7) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 254: Block Diagram
GD32F403xx User Manual Block diagram 16.1.3. Figure 16-1. Advanced timer block diagram provides details of the internal configuration of the advanced timer. Figure 16-1. Advanced timer block diagram...
Page 255: Function Overview
GD32F403xx User Manual Function overview 16.1.4. Clock source configuration The advanced timer has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]). ◼ SMC [2:0] == 3’b000. Internal clock CK_TIMER is selected as timer clock source which is f rom module RCU.
Page 256: Figure 16-3. Timing Chart Of Psc Value Change From 0 To 2
GD32F403xx User Manual 0x1, 0x2 or 0x3. ◼ SMC1== 1’b1 (external clock mode 1). External input is selected as timer clock source (ETI) The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin ETI. This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1.
Page 257: Figure 16-4. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F403xx User Manual times of overflow events. The counting direction bit DIR in the TIMERx_CTL0 register should be set to 0 for the up counting mode. Whenever, if the update event software trigger is enabled by setting the UPG bit in the TIMERx_SWEVG register, the counter value will be initialized to 0 and generates an update event.
Page 258: Figure 16-5. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F403xx User Manual Figure 16-5. Timing chart of up counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 259 GD32F403xx User Manual counter behavior in different clock frequencies when TIMERx_CAR=0x99. Figure 16-6. Timing chart of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF)
Page 260: Figure 16-7. Timing Chart Of Down Counting Mode, Change Timerx_Car On The Go
GD32F403xx User Manual Figure 16-7. Timing chart of down counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) Update interrupt flag (UPIF)
Page 261 GD32F403xx User Manual behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 16-8. Timing chart of center-aligned counting TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Update event (from overflow/underflow) rate configuration...
Page 262: Figure 16-9. Repetition Timechart For Center-Aligned Counter
GD32F403xx User Manual generated (on overflow or underflow) depending on when the written CREP value takes effect. If an update event is generated by software after writing an odd number to CREP, the update events will be generated on the underflow. If the next update event occurs on overflow after writing an odd number to CREP, then the subsequent update events will be generated on the overf low.
Page 263: Figure 16-11. Repetition Timechart For Down-Counter
GD32F403xx User Manual Figure 16-11. Repetition timechart for down-counter TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 264: Figure 16-12. Channel Input Capture Principle
GD32F403xx User Manual Figure 16-12. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 265 GD32F403xx User Manual Result: when you wanted input signal is got, TIMERx_CHxCV will be set by counter’s value. And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by sof tware directly.
Page 266: Figure 16-13. Output-Compare Under Three Modes
GD32F403xx User Manual Figure 16-13. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 267 GD32F403xx User Manual Figure 16-14. EAPWM timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Figure 16-15. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal...
Page 268 GD32F403xx User Manual CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 269: Table 16-2. Complementary Outputs Controlled By Parameters
GD32F403xx User Manual Table 16-2. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable: CHx_O = ISOx CHx_ON = ISOxN CHx_O = CHxP CHx_ON = CHxNP...
Page 270: Figure 16-16. Complementary Output With Dead-Time Insertion
GD32F403xx User Manual Insertion dead time for complementary PWM The dead time insertion is enabled when both CHxEN and CHxNEN are 1’b1, and set POEN is also necessary. The field named DTCFG defines the dead time delay that can be used for all channels expect for channel 3.
Page 271: Figure 16-17. Output Behavior In Response To A Break(The Break High Active)
GD32F403xx User Manual and HXTAL stuck event by Clock Monitor (CKM) in RCU. The break function enabled by setting the BRKEN bit in the TIMERx_CCHP register. The break input polarity is setting by the BRKP bit in TIMERx_CCHP. When a break occurs, the POEN bit is cleared asynchronously, the output CHx_O and CHx_ON are driven with the level programmed in the ISOx bit and ISOxN in the TIMERx_CTL1 register as soon as POEN is 0.
Page 272: Figure 16-18. Example Of Counter Operation In Encoder Interface Mode
GD32F403xx User Manual selection. This means that the counter counts continuously in the interval between 0 and the counter-reload value. Therefore, users must configure the TIMERx_CAR register before the counter starts to count. Table 16-3. Counting direction versus encoder signals CI0FE0 CI1FE1 Counting mode...
Page 273: Figure 16-20. Hall Sensor Is Used To Bldc Motor
GD32F403xx User Manual Hall sensor function Hall sensor is generally used to control BLDC Motor; advanced timer can support this function. Figure 16-20. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers. First TIMER_in（Advanced/General L0 TIMER） should accept three Rotor Position signals from Motor.
Page 274: Figure 16-21. Hall Sensor Timing Between Two Timers
GD32F403xx User Manual Figure 16-20. Hall sensor is used to BLDC motor TIMER_in Input capture GPIO Core TIMER_out Output compare PWM output Figure 16-21. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_IN CH1_IN CH2_IN CI0(OXR) Counter CH0VAL...
Page 275: Figure 16-22. Restart Mode
GD32F403xx User Manual Master-slave management The TIMERx can be synchronized with a trigger in several modes including the restart mode, the pause mode and the event mode which is selected by the SMC [2:0] in the TIMERx_SMCFG register. The trigger input of these modes can be selected by the TRGS [2:0] in the TIMERx_SMCFG register.
Page 276: Figure 16-23. Pause Mode
GD32F403xx User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection Exam2 Pause mode TI0S=0.（Non-xor） Filter is bypass in this TRGS[2:0]=3’b10 [CH0NP==0, CH0P==0] example. The counter can no inverted. Capture will be be paused when CI0FE0 sensitive to the rising edge the trigger input is selection.
Page 277: Figure 16-25. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32F403xx User Manual Once the timer is set to operate in the single pulse mode, it is not necessary to set the timer enable bit CEN in the TIMERx_CTL0 register to 1 to enable the counter. The trigger to generate a pulse can be sourced from the trigger signals edge or by setting the CEN bit to 1 using software.
Page 278 GD32F403xx User Manual Figure 16-26. Timer0 master/slave mode timer example TIMER0 TRGS TIMER 2 Master ITI2 TRG O Pre scaler Counter mode control Trigger selection TIMER 3 Master TRG O ITI3 Pre scaler Counter mode control CI0F_ED CI0FE0 CI1FE1 ETIFP Other interconnection examples: ◼...
Page 279: Figure 16-27. Triggering Timer0 With Enable Signal Of Timer2
GD32F403xx User Manual divided internal clock after trigger by timer2 enable output. When Timer0 receives the trigger signal its CEN bit is set and the counter counts until we disable timer0. Both counter clock frequencies are divided by 3 by the prescaler compared to TIMER_CK (f CNT_CLK = f TIMER_CK /3).
Page 280: Figure 16-28. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32F403xx User Manual Figure 16-28. Triggering TIMER0 and TIMER2 with TIMER2’s CI0 input TIMER2 TIMER_CK TRGIF CNT_REG TIMER0 TRGIF CNT_CK CNT_REG Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB. Of course, you have to enable a DMA request which will be asserted by some internal event.
Page 281: Timerx Registers(X=0, 7)
GD32F403xx User Manual TIMERx registers(x=0, 7) 16.1.5. TIMER0 base address: 0x4001 2C00 TIMER7 base address: 0x4001 3400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS...
Page 282 GD32F403xx User Manual Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode. 0: Single pulse mode disable. The counter continues after update event. 1: Single pulse mode enable. The counter counts until the next update event occurs.
Page 283 GD32F403xx User Manual Bits Fields Descriptions Reserved Must be kept at reset value. ISO3 Idle state of channel 3 output Refer to ISO0 bit ISO2N Idle state of channel 2 complementary output Refer to ISO0N bit ISO2 Idle state of channel 2 output Refer to ISO0 bit ISO1N Idle state of channel 1 complementary output...
Page 284 GD32F403xx User Manual 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit. 011: When a capture or compare pulse event occurs in chann el0, a TRGO trigger signal is output.
Page 285 GD32F403xx User Manual Bits Fields Descriptions External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at high level or rising edge. 1: ETI is active at low level or falling edge. SMC1 Part of SMC for enable External clock mode1. In external clock mode 1, the counter is clocked by any active edge on the ETIF signal.
Page 286 GD32F403xx User Manual 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected together.
Page 287 GD32F403xx User Manual DMA and interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved TRGDEN CMTDEN CH3DEN CH2DEN CH1DEN CH0DEN UPDEN BRKIE TRGIE CMTIE CH3IE CH2IE CH1IE CH0IE UPIE Bits...
Page 288 GD32F403xx User Manual CMTIE commutation interrupt enable 0: disabled 1: enabled CH3IE Channel 3 capture/compare interrupt enable 0: disabled 1: enabled CH2IE Channel 2 capture/compare interrupt enable 0: disabled 1: enabled CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE Channel 0 capture/compare interrupt enable 0: disabled...
Page 289 GD32F403xx User Manual capture event occurs while CH0IF flag has already been set. This flag is cleared by software. 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved Must be kept at reset value. BRKIF Break interrupt flag When the break input is inactive, the bit is set by hardware.
Page 290 GD32F403xx User Manual Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved BRKG TRGG CMTG CH3G CH2G CH1G CH0G Bits Fields Descriptions 15:8 Reserved Must be kept at reset value. BRKG Break event generation This bit is set by software and cleared by hardware automatically.
Page 291 GD32F403xx User Manual flag is set, the corresponding interrupt or DMA request is sent if enabled. In addition, if channel 1 is configured in input mode, the current value of the counter is captured in TIMERx_CH0CV register, and the CH0OF flag is set if the CH0IF flag was already high.
Page 292 GD32F403xx User Manual 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS. Note: When CH1MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 293 GD32F403xx User Manual 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
Page 294 GD32F403xx User Manual 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 295 GD32F403xx User Manual CH3COMFEN Channel 3 output compare fast enable Refer to CH0COMFEN description CH3MS[1:0] Channel 3 mode selection This bit-field specifies the direction of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH3EN bit in TIMERx_CHCTL2 register is reset).
Page 296 GD32F403xx User Manual 11 and CH2MS bit-filed is 00(COMPARE MODE). CH2COMSEN Channel 2 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH2CV register, which updates at each update event will be enabled. 0: Channel 2 output compare shadow disable 1: Channel 2 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1)
Page 297 GD32F403xx User Manual Basic principle of digital filter: continuously sample the CI2 input signal according to and record the number of times of the same level of the si gnal. After reaching SAMP the filtering capacity configured by this bit, it is considered to be an effective level. The filtering capability configuration is as follows: CH2CAPFLT [3:0] Times...
Page 298 GD32F403xx User Manual 15:14 Reserved Must be kept at reset value. CH3P Channel 3 capture/compare function polarity Refer to CH0P description CH3EN Channel 3 capture/compare function enable Refer to CH0EN description CH2NP Channel 2 complementary output polarity Refer to CH0NP description CH2NEN Channel 2 complementary output enable Refer to CH0NEN description...
Page 299 GD32F403xx User Manual polarity. 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] will select the active trigger or capture polarity for CI0FE0 or CI1FE0.
Page 300 GD32F403xx User Manual PSC[15:0] Bits Fields Descriptions 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 301 GD32F403xx User Manual are enabled. Channel 0 capture/compare value register (TIMERx_CH0CV) Address offset: 0x34 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH0VAL[15:0] Bits Fields Descriptions 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 302 GD32F403xx User Manual CH2VAL[15:0] Bits Fields Descriptions 15:0 CH2VAL[15:0] Capture or compare value of channel 2 When channel 2 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 2 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 303 GD32F403xx User Manual - If OAEN is set to 1, this bit is set to 1 at the next update event. The bit can be cleared to 0 by: - Write 0 to this bit - Valid fault input (asynchronous). When one of channels is configured in output mode, setting this bit enables the channel outputs (CHx_O and CHx_ON) if the corresponding enable bits (CHxEN, CHxNEN in TIMERx_CHCTL2 register) have been set.
Page 304 GD32F403xx User Manual This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 10 or 11. PROT[1:0] Complementary register protect control This bit-filed specifies the write protection property of registers. 00: protect disable. No write protection. 01: PROT mode 0.The ISOx/ISOxN bits in TIMERx_CTL1 register and the BRKEN/BRKP/OAEN/DTCFG bits in TIMERx_CCHP register are writing protected.
Page 305 GD32F403xx User Manual This filed defines the number(n) of the register that DMA will access(R/W), n = (DMATC [4:0] +1). DMATC [4:0] is from 5’b0_0000 to 5’b1_0001. Reserved Must be kept at reset value. DMATA [4:0] DMA transfer access start address This filed define the first address for the DMA access the TIMERx_DMATB.
Page 306 GD32F403xx User Manual 0: No effect OUTSEL The output value selection This bit-field set and reset by software 1: If POEN and IOS is 0, the output disabled 0: No effect...
Page 307: General Level0 Timer (Timerx, X= 2, 3)
GD32F403xx User Manual 16.2. General level0 timer (TIMERx, x= 2, 3) Overview 16.2.1. The general level0 timer module (Timer2, 3) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 308 GD32F403xx User Manual conf iguration of the general level0 timer. Figure 16-29. General Level 0 timer block diagram...
Page 309: Function Overview
GD32F403xx User Manual Function overview 16.2.4. Clock source configuration The general level0 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]). ◼ SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU. The default internal clock source is the CK_TIMER used to drive the counter prescaler when the SMC [2:0] == 3’b000.
Page 310: Figure 16-31. Timing Chart Of Psc Value Change From 0 To 2
GD32F403xx User Manual ◼ SMC1== 1’b1(external clock mode 1). External input pin source (ETI) The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of rising or falling edge on the external pin ETI. This mode can be selected by setting the SMC1 bit in the TIMERx_SMCFG register to 1.
Page 311: Figure 16-32. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F403xx User Manual value will be initialized to 0 and generates an update event. If the UPDIS bit in TIMERx_CTL0 register is set, the update event is disabled. When an update event occurs, all the shadow registers (counter auto reload register, prescaler register) are updated.
Page 312: Figure 16-33. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F403xx User Manual Figure 16-33. Timing chart of up counting mode, change TIMERx_CAR on the go. TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 313: Figure 16-35. Down-Counter Timechart, Change Timerx_Car On The Go
GD32F403xx User Manual Figure 16-34. Timing chart of down counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 16-35.
Page 314: Figure 16-36. Timing Chart Of Center-Aligned Counting Mode
GD32F403xx User Manual Counter center-aligned counting In this mode, the counter counts up from 0 to the counter-reload value and then counts down to 0 alternatively. The Timer module generates an overflow event when the counter counts to the counter-reload value subtract 1 in the up-counting mode and generates an underflow event when the counter counts to 1 in the down-counting mode.
Page 315 GD32F403xx User Manual Figure 16-36. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set Software clear Input capture and output compare channels The general level0 Timer has four independent channels which can be used as capture inputs or compare match outputs.
Page 316: Figure 16-37. Channel Input Capture Principle
GD32F403xx User Manual Figure 16-37. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P TIMER_CK CI0FE0 Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal ITI0 ITI1 ITI2...
Page 317 GD32F403xx User Manual And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly.
Page 318: Figure 16-38. Output-Compare Under Three Modes
GD32F403xx User Manual Figure 16-38. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM mode (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can outputs PWM waveform according to the TIMERx_CAR registers and TIMERx_CHxCV registers.
Page 319 GD32F403xx User Manual Figure 16-39. EAPWM timechart CHxVAL Cx OUT Cx OUT CHxIF CHxOF Figure 16-40. CAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only CHxIF CHxOF CAM=2'b10 up only CHxIF CHxOF CAM=2'b11 up/down CHxIF CHxOF Channel output prepare signal...
Page 320: Table 16-5. Slave Mode Example Table
GD32F403xx User Manual CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
Page 321: Figure 16-41. Restart Mode
GD32F403xx User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection TRGS[2:0]=3’b00 Exam1 Restart mode For ITI0, no polarity selector For the ITI0, no filter and The counter can be can be used. ITI0 is the prescaler can be used. clear and restart when a selection.
Page 322: Figure 16-43. Event Mode
GD32F403xx User Manual Mode Selection Source Polarity Selection Filter and Prescaler Selection TRGS[2:0]=3’b11 Exam3 Event mode ETP = 0 no polarity change. ETPSC = 1, divided by 2. The counter will start to ETFC = 0 , no filter count when a rising ETIF trigger input.
Page 323: Figure 16-44. Single Pulse Mode Timerx_Chxcv = 0X04 Timerx_Car=0X60
GD32F403xx User Manual Figure 16-44. Single pulse mode TIMERx_CHxCV = 0x04 TIMERx_CAR=0x60 TIMER_CK(CNT_CLK) Under SPM, counter stop …. CNT_REG O2CPRE Timers interconnection Advanced timer (TIMERx, x=0, 7). Ref er to Timer DMA mode Timer’s DMA mode is the function that configures timer’s register by DMA module. The relative registers are TIMERx_DMACFG and TIMERx_DMATB;...
Page 324: Timerx Registers(X=2, 3)
GD32F403xx User Manual TIMERx registers(x=2, 3) 16.2.5. TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CKDIV[1:0] ARSE CAM[1:0] UPDIS...
Page 325 GD32F403xx User Manual Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only. Single pulse mode. 0: Single pulse mode disable. The counter continues after update event. 1: Single pulse mode enable. The counter counts until the next update event occurs.
Page 326 GD32F403xx User Manual Bits Fields Descriptions 15:8 Reserved Must be kept at reset value. TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input. 1: The result of combinational XOR of TIMERx_CH0, CH1 and CH2 pins is selected as channel 0 trigger input.
Page 327 GD32F403xx User Manual SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at high level or rising edge. 1: ETI is active at low level or falling edge. SMC1 Part of SMC for enable External clock mode1.
Page 328 GD32F403xx User Manual 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected together.
Page 329 GD32F403xx User Manual 110: Event mode. A rising edge of the trigger input enables the counter. 111: External clock mode0. The counter counts on the rising edges of the selected trigger. DMA and interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved TRGDEN Reserved CH3DEN CH2DEN CH1DEN CH0DEN UPDEN Reserved...
Page 330 GD32F403xx User Manual 1: enabled Reserved Must be kept at reset value. CH3IE Channel 3 capture/compare interrupt enable 0: disabled 1: enabled CH2IE Channel 2 capture/compare interrupt enable 0: disabled 1: enabled CH1IE Channel 1 capture/compare interrupt enable 0: disabled 1: enabled CH0IE Channel 0 capture/compare interrupt enable...
Page 331 GD32F403xx User Manual capture event occurs while CH0IF flag has already been set. This flag is cleared by software. 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved Must be kept at reset value. TRGIF Trigger interrupt flag This flag is set on trigger event and cleared by software.
Page 332 GD32F403xx User Manual Bits Fields Descriptions 15:7 Reserved Must be kept at reset value. TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STAT register is set, related interrupt or DMA transfer can occur if enabled.
Page 333 GD32F403xx User Manual CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control Refer to CH0COMCTL description CH1COMSEN Channel 1 output compare shadow enable...
Page 334 GD32F403xx User Manual compare register TIMERx_CH0CV. 100: Force low. O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low when the counter is larger than TIMERx_CH0CV, and high otherwise.
Page 335 GD32F403xx User Manual Input capture mode: Bits Fields Descriptions 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection Same as Output compare mode CH0CAPFLT[3:0] Channel 0 input capture filter control The CI0 input signal can be filtered by digital filter and this bit-field configure the...
Page 336 GD32F403xx User Manual Same as Output compare mode Channel control register 1 (TIMERx_CHCTL1) Address offset: 0x1C Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH3COM CH3COM CH3COM CH2COM CH2COM CH2COM CH3COMCTL[2:0] CH2COMCTL[2:0] CH3MS[1:0] CH2MS[1:0] CH3CAPFLT[3:0] CH3CAPPSC[1:0] CH2CAPFLT[3:0]...
Page 337 GD32F403xx User Manual O0CPRE. In addition, the high level of O0CPRE is the active level, and CH0_O and CH0_ON channels polarity depends on CH0P and CH0NP bits. 000: Timing mode. The O2CPRE signal keeps stable, independent of the comparison between the output compare register TIMERx_CH2CV and the counter TIMERx_CNT.
Page 338 GD32F403xx User Manual This bit-field specifies the work mode of the channel and the input signal selection. This bit-field is writable only when the channel is not active. (CH2EN bit in TIMERx_CHCTL2 register is reset).). 00: Channel 2 is programmed as output mode 01: Channel 2 is programmed as input mode, IS2 is connected to CI2FE2 10: Channel 2 is programmed as input mode, IS2 is connected to CI3FE2 11: Channel 2 is programmed as input mode, IS2 is connected to ITS.
Page 339 GD32F403xx User Manual 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
Page 340 GD32F403xx User Manual CH0P Channel 0 capture/compare function polarity When channel 0 is configured in output mode, this bit specifies the output signal polarity. 0: Channel 0 high level is active level 1: Channel 0 low level is active level When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity.
Page 341 GD32F403xx User Manual Bits Fields Descriptions 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 342 GD32F403xx User Manual Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH1VAL[15:0] Bits Fields Descriptions 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 343 GD32F403xx User Manual CH3VAL[15:0] Bits Fields Descriptions 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 3 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 344 GD32F403xx User Manual Bits Fields Descriptions 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed. The transfer Timer is calculated by hardware, and ranges from 0 to DMATC. Configuration register (TIMERx_CFG ) Address offset: 0xFC Reset value: 0x0000...
Page 345: General Level1 Timer (Timerx, X=8, 11)
GD32F403xx User Manual 16.3. General level1 timer (TIMERx, x=8, 11) Overview 16.3.1. The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 346: Figure 16-45. General Level1 Timer Block Diagram
GD32F403xx User Manual Block diagram 16.3.3. Figure 16-45. General level1 timer block diagram provides details on the internal conf iguration of the general level1 timer. Figure 16-45. General level1 timer block diagram CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector ITI0 ITI1...
Page 347: Figure 16-46. Timing Chart Of Internal Clock Divided By 1
GD32F403xx User Manual Function overview 16.3.4. Clock source configuration The general level1 TIMER has the capability of being clocked by either the CK_TIMER or an alternate clock source controlled by SMC (TIMERx_SMCFG bit [2:0]). ◼ SMC [2:0] == 3’b000. Internal timer clock CK_TIMER which is from module RCU. The default internal clock source is the CK_TIMER used to drive the counter prescaler when the SMC [2:0] == 3’b000.
Page 348: Figure 16-47. Timing Chart Of Psc Value Change From 0 To 2
GD32F403xx User Manual Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale f actor can be configured f rom 1 to 65536 through the prescaler register (TIMERx_PSC). The new written prescaler value will not take effect until the next update event.
Page 349: Figure 16-48. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F403xx User Manual Figure 16-48. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 16-49.
Page 350: Figure 16-50. Channels Input Capture Principle
GD32F403xx User Manual Input capture and output compare channels The general level1 timer has two independent channels which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ◼...
Page 351 GD32F403xx User Manual Step2: Edge selection. (CHxP/CHxNP in TIMERx_CHCTL2) Rising or falling edge, choose one by CHxP/CHxNP. Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0) As soon as you select one input capture source by CHxMS, you have set the channel to input mode (CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more.
Page 352: Figure 16-51. Output-Compare Under Three Modes
GD32F403xx User Manual About the CHxVAL, you can change it on the go to meet the waveform you expected. Step5: Start the counter by CEN. The timechart below show the three compare modes toggle/set/clear. CAR=0x63, CHxVAL=0x3 Figure 16-51. Output-compare under three modes CNT_CLK ….
Page 353: Figure 16-52. Eapwm Timechart
GD32F403xx User Manual mode0 (CHxCOMCTL==3’b110). And if TIMERx_CHxCV is equal to zero, the output will be always inactive under PWM mode0 (CHxCOMCTL==3’b110). Figure 16-52. EAPWM timechart CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF CHxOF Figure 16-53. CAPWM timechart CHxVAL PWM MODE0 Cx OUT...
Page 354: Table 16-6．Slave Mode Example Table
GD32F403xx User Manual x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function. These include, keeping the original level by setting the CHxCOMCTL field to 0x00, set to 1 by setting the CHxCOMCTL field to 0x01, set to 0 by setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register.
Page 355: Figure 16-54. Restart Mode
GD32F403xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 16-54. Restart mode TIMER_CK CNT_REG UPIF ITI0 Internal sync delay TRGIF Exam2 Pause mode CH0P==0, Filter is bypass in this TRGS[2:0]=3’b101 no inverted. Capture will be example. The counter can be CI0FE0 sensitive to the rising edge...
Page 356: Figure 16-56. Event Mode
GD32F403xx User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 16-56. Event mode Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event.
Page 357 GD32F403xx User Manual Figure 16-57. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 Timers interconnection Advanced timer (TIMERx, x=0, Ref er to Timer debug mode ® When the Cortex -M4 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1, the TIMERx counter stops.
Page 358 GD32F403xx User Manual TIMERx registers(x=8, 11) 16.3.5. TIMER8 base address: 0x4001 4C00 TIMER11 base address: 0x4000 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CKDIV[1:0] ARSE Reserved UPDIS...
Page 359 GD32F403xx User Manual UPDIS Update disable. This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values . These events generate update event: The UPG bit is set The counter generates an overflow or underflow event...
Page 360 GD32F403xx User Manual 100: CI0F_ED 101: CI0FE0 110: CI1FE1 111: Reserved. These bits must not be changed when slave mode is enabled. Reserved Must be kept at reset value. SMC[2:0] Slave mode control 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high.
Page 361 GD32F403xx User Manual 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CH1OF CH0OF Reserved TRGIF Reserved CH1IF...
Page 362 GD32F403xx User Manual mode, this flag is set when a compare event occurs. If Channel0 is set to input mode, this bit will be reset by reading TIMERx_CH0CV. 0: No Channel 0interrupt occurred 1: Channel 0 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software.
Page 363 GD32F403xx User Manual bit is set, the counter is cleared. The prescaler counter is cleared at the same time. 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH1COM CH1COM...
Page 364 GD32F403xx User Manual 000: Timing mode. The O0CPRE signal keeps stable, independent of the comparison between the register TIMERx_CH0CV and the counter TIMERx_CNT. 001: Set the channel output. O0CPRE signal is forced high when the counter is equals to the output compare register TIMERx_CH0CV. 010: Clear the channel output.
Page 365 GD32F403xx User Manual 00: Channel 0 is programmed as output mode 01: Channel 0 is programmed as input mode, IS0 is connected to CI0FE0 10: Channel 0 is programmed as input mode, IS0 is connected to CI1FE0 11: Channel 0 is programmed as input mode, IS0 is connected to ITS Note: When CH0MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
Page 366 GD32F403xx User Manual is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges CH0MS[1:0] Channel 0 mode selection...
Page 367 GD32F403xx User Manual When channel 0 is configured in input mode, this bit specifies the CI0 signal polarity. [CH0NP, CH0P] will select the active trigger or capture polarity for CI0FE0 or CI1FE0. [CH0NP==0, CH0P==0]: CIxFE0’s rising edge is the active signal for capture or trigger operation in slave mode.
Page 368 GD32F403xx User Manual Bits Fields Descriptions 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
Page 369 GD32F403xx User Manual Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH1VAL[15:0] Bits Fields Descriptions 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event.
Page 370: Figure 16-58. General Level2 Timer Block Diagram
GD32F403xx User Manual 16.4. General level2 timer (TIMERx, x=9, 10, 12, 13) Overview 16.4.1. The general level2 timer module (Timer9, 10, 12, 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
Page 371 GD32F403xx User Manual conf iguration of the general level2 timer. Figure 16-58. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMERx_TRGO TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update Update...
Page 372: Figure 16-59. Timing Chart Of Internal Clock Divided By 1
GD32F403xx User Manual Function overview 16.4.4. Clock source configuration The general level2 TIMER can only being clocked by the CK_TIMER. ◼ Internal timer clock CK_TIMER which is from module RCU The general level2 TIMER has only one clock source which is the internal CK_TIMER, used to drive the counter prescaler.
Page 373: Figure 16-60. Timing Chart Of Psc Value Change From 0 To 2
GD32F403xx User Manual Figure 16-60. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is def ined in the TIMERx_CAR register, in a count-up direction.
Page 374: Figure 16-61. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F403xx User Manual Figure 16-61. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Hardware set Update interrupt flag (UPIF) Figure 16-62.
Page 375: Figure 16-63. Channels Input Capture Principle
GD32F403xx User Manual Input capture and output compare channels The general level2 timer has one independent channel which can be used as capture inputs or compare match outputs. Each channel is built around a channel capture compare register including an input stage, channel controller and an output stage. ◼...
Page 376 GD32F403xx User Manual Step2: Edge selection. (CHxP/CHxNP in TIMERx_CHCTL2) Rising or falling edge, choose one by CHxP/CHxNP. Step3: Capture source selection. (CHxMS in TIMERx_CHCTL0) As soon as you select one input capture source by CHxMS, you have set the channel to input mode ( CHxMS!=0x0) and TIMERx_CHxCV cannot be written any more.
Page 377: Figure 16-64. Output-Compare Under Three Modes
GD32F403xx User Manual The timechart below show the three compare modes toggle/set/clear. CAR=0x63, CHxVAL=0x3 Figure 16-64. Output-compare under three modes CNT_CLK …. …. …. CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed.
Page 378 GD32F403xx User Manual Timers interconnection Advanced timer (TIMERx, x=0, Ref er to Timer debug mode ® When the Cortex -M4 halted, and the TIMERx_HOLD configuration bit in DBG_CTL0 register set to 1, the TIMERx counter stops.
Page 379 GD32F403xx User Manual TIMERx registers(x=9, 10, 12, 13) 16.4.5. TIMER9 base address: 0x4001 5000 TIMER10 base address: 0x4001 5400 TIMER12 base address: 0x4000 1C00 TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved CKDIV[1:0] ARSE...
Page 380 GD32F403xx User Manual This bit is used to enable or disable the update event generation. 0: Update event enable. When an update event occurs, the corresponding shadow registers are loaded with their preloaded values . These events generate update event: The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event.
Page 381 GD32F403xx User Manual 011: When a capture or compare pulse event occurs in chann el0, a TRGO trigger signal is output. 100: When a compare event occurs, a TRGO trigger signal is output. The compare source is from O0CPRE 101: Reserved 110: Reserved 111: Reserved Reserved...
Page 382 GD32F403xx User Manual When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set. This flag is cleared by software. 0: No over capture interrupt occurred 1: Over capture interrupt occurred Reserved Must be kept at reset value.
Page 383 GD32F403xx User Manual time. 0: No generate an update event 1: Generate an update event Channel control register 0 (TIMERx_CHCTL0) Address offset: 0x18 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) CH0COM CH0COM Reserved CH0COMCTL[2:0] Reserved.
Page 384 GD32F403xx User Manual 11 and CH0MS bit-filed is 00(COMPARE MODE). CH0COMSEN Channel 0 compare output shadow enable When this bit is set, the shadow register of TIMERx_CH0CV register, which updates at each update event, will be enabled. 0: Channel 0 output co mpare shadow disable 1: Channel 0 output compare shadow enable The PWM mode can be used without verifying the shadow register only in single pulse mode (when SPM=1)
Page 385 GD32F403xx User Manual 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges...
Page 386 GD32F403xx User Manual When channel 0 is configured in input mode, together with CH0P, this bit is used to define the polarity of CI0. This bit cannot be modified when PROT [1:0] bit-filed in TIMERx_CCHP register is 11 or 10. Must be kept at reset value.
Page 387 GD32F403xx User Manual the value of the counter. Prescaler register (TIMERx_PSC) Address offset: 0x28 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) PSC[15:0] Bits Fields Descriptions 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock.
Page 388 GD32F403xx User Manual Bits Fields Descriptions 15:0 CH0VAL[15:0] Capture or compare value of channel0 When channel 0 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 0 is configured in output mode, this bit-filed contains value to be compared to the counter.
Page 389: Figure 16-65. Basic Timer Block Diagram
GD32F403xx User Manual 16.5. Basic timer (TIMERx, x=5, 6) Overview 16.5.1. The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC.
Page 390: Figure 16-66. Timing Chart Of Internal Clock Divided By 1
GD32F403xx User Manual Figure 16-66. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale f actor can be configured f rom 1 to 65536 through the prescaler register (TIMERx_PSC).
Page 391: Figure 16-68. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F403xx User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is def ined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up f rom 0 again. The update event is generated at each counter overflow.
Page 392: Figure 16-69. Timing Chart Of Up Counting Mode, Change Timerx_Car On The Go
GD32F403xx User Manual Figure 16-69. Timing chart of up counting mode, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120 Update event (UPE) Update interrupt flag (UPIF)
Page 393 GD32F403xx User Manual TIMERx registers(x=5, 6) 16.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ARSE Reserved UPDIS Bits...
Page 394 GD32F403xx User Manual 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized. Counter enable 0: Counter disable 1: Counter enable The CEN bit must be set by software when timer work s in external clock, pause mode and encoder mode.
Page 395 GD32F403xx User Manual Reserved UPDEN Reserved UPIE Bits Fields Descriptions 15:9 Reserved Must be kept at reset value. UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value. UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10...
Page 396 GD32F403xx User Manual Bits Fields Descriptions 15:1 Reserved Must be kept at reset value. This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared. The prescaler counter is cleared at the same time.
Page 397 GD32F403xx User Manual This register can be accessed by half-word (16-bit) or word (32-bit) CARL[15:0] Bits Fields Descriptions 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
Page 398 GD32F403xx User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 17.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a f lexible serial data exchange interface. Data f rames can be transferred in f ull duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK(PCLK1 or PCLK2) to produce a dedicated baud rate clock for the USART transmitter and receiver.
Page 399: Table 16-1. Description Of Usart Important Pins
GD32F403xx User Manual – Block mode (T=1) – Direct and inverse convention ◼ Multiprocessor communication – Enter into mute mode if address match does not occur. – Wake up from mute mode by idle frame or address match detection. ◼ Various status flags: –...
Page 400: Figure 16-1. Usart Module Block Diagram
GD32F403xx User Manual Figure 17-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controller Flow nCTS Controller USART Control Registers USART Address Transmitter Transimit clock...
Page 401 GD32F403xx User Manual STB[1:0] stop bit length (bit) usage description normal USART and single-wire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
Page 402: Figure 16-3. Usart Transmit Procedure
GD32F403xx User Manual the TBE bit in the USART_STAT0 register is asserted. The TBE bit is cleared by writing to the USART_DATA register and it is set by hardware after the data is put into the transmit shift register. If a data is written to the USART_DATA register while a transmission is ongoing, it will be firstly stored in the transmit buffer, and transferred to the transmit shift register after the current transmission is done.
Page 403: Figure 16-4. Receiving A Frame Bit By Oversampling Method
GD32F403xx User Manual Set the STB[1:0] bits in USART_CTL1. Enable DMA (DENR bit) in USART_CTL2 if multibuffer communication is selected. Set the baud rate in USART_BAUD. Set the REN bit in USART_CTL0. After being enabled, the receiver receives a bit stream after a valid start pulse has been detected.
Page 404: Figure 16-5. Configuration Step When Using Dma For Usart Transmission
GD32F403xx User Manual USART_CTL2 register is set, or if the RBNEIE is set. If a noise error (NERR), parity error (PERR), frame error (FERR) or overrun error (ORERR) is generated during a receiving process, then NERR, PERR, FERR or ORERR will be set at same time with RBNE.
Page 405: Figure 16-6. Configuration Steps When Using Dma For Usart Reception
GD32F403xx User Manual After all of the data frames are transmitted, the TC bit in USART_STAT0 is set. An interrupt occurs if the TCIE bit in USART_CTL0 is set. When DMA is used for USART reception, DMA transfers data from the receive data buffer of the USART to the internal SRAM.
Page 406: Figure 16-7. Hardware Flow Control Between Two Usarts
GD32F403xx User Manual Figure 17-7. Hardware flow control between two USARTs RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame.
Page 407 GD32F403xx User Manual big burden for a device to monitor all of the messages on the RX pin. To reduce the burden of a device, software can put an USART module into a mute mode by setting the RWU bit in USART_CTL0 register.
Page 408: Figure 16-9. Break Frame Occurs During Idle State
GD32F403xx User Manual Figure 17-9. Break frame occurs during idle state frame0 frame1 frame2 RX pin 1 frame time FERR USART_DATA data0 data1 00000000 data2 LBDF As shown in Figure 17-10. Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame.
Page 409: Figure 16-12. 8-Bit Format Usart Synchronous Waveform (Clen=1)
GD32F403xx User Manual Figure 17-12. 8-bit format USART synchronous waveform (CLEN=1) IrDA SIR ENDEC mode 17.3.10. The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be cleared in IrDA mode.
Page 410: Figure 16-14. Irda Data Modulation
GD32F403xx User Manual width is less than 1 PSC clock. While it can detect a pulse by chance if the pulse width is greater than 1 but smaller than 2 times PSC clock. Because the IrDA is a half-duplex protocol, the transmission and the reception should not be carried out at the same time in the IrDA SIR ENDEC block.
Page 411: Figure 16-15. Iso7816-3 Frame Format
GD32F403xx User Manual bit may be configured for a receiver. Figure 17-15. ISO7816-3 frame format Character (T=0) mode Comparing to the timing in normal operation, the transmission time from transmit shift register to the TX pin is delayed by half baud clock, and the TC flag assertion time is delayed by a guard time that is configured by the GUAT[7:0] bits in USART_GP.
Page 412 GD32F403xx User Manual timeout period is expressed in baud time units. The RTF bit in USART_STAT1 will be asserted, if no answer is received from the card before the expiration of this period. An interrupt is generated if the RTIE bit in USART_CTL3 is set. The USART generates a RBNE interrupt if the first character is received before the expiration of the RT[23:0] period.
Page 413: Figure 16-16. Usart Interrupt Mapping Diagram
GD32F403xx User Manual Table 17-3. USART interrupt requests Enable Interrupt event Event flag Control register Control bit Transmit data buffer empty USART_CTL0 TBEIE CTS toggled flag CTSF USART_CTL2 CTSIE Transmission complete USART_CTL0 TCIE Received buff not empty RBNE USART_CTL0 RBNEIE Overrun error ORERR Idle frame...
Page 414 GD32F403xx User Manual 17.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 Status register 0 (USART_STAT0) 17.4.1. Address offset: 0x00 Reset value: 0x0000 00C0 This register has to be accessed by word (32-bit).
Page 415 GD32F403xx User Manual 1: Transmit data buffer is empty. Transmission complete. This bit is set after power on. If the TBE bit has been set, this bit is set when the transmission of current data is complete. An interrupt occurs if the TCIE bit in USART_CTL0 is set.
Page 416 GD32F403xx User Manual registers one by one. 0: The USART does not detect a framing error. 1: The USART has detected a framing error. PERR Parity error flag This bit is set when the parity bit of a receive frame does not match the expected parity value.
Page 417 GD32F403xx User Manual INTDIV [11:0] FRADIV[3:0] Bits Fields Descriptions 31:16 Reserved Must be kept the reset value. 15:4 INTDIV[11:0] Integer part of baud -rate divider. FRADIV[3:0] Fraction part of baud -rate divider. Control register 0 (USART_CTL0) 17.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit).
Page 418 GD32F403xx User Manual If this bit is set, an interrupt occurs when the PERR bit in USART_STAT0 is set. 0: Parity error interrupt is disabled . 1: Parity error interrupt is enabled . TBEIE Transmitter buffer empty interrupt enable. If this bit is set, an interrupt occurs when the TBE bit in USART_STAT0 is set. 0: Transmitter buffer empty interrupt is disabled .
Page 419 GD32F403xx User Manual 1: Transmit a break frame. Control register 1 (USART_CTL1) 17.4.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved LMEN STB[1:0] CKEN CLEN Reserved. LBDIE LBLEN Reserved ADDR[3:0] Bits Fields Descriptions...
Page 420 GD32F403xx User Manual This bit specifies the length of the CK signal in synchronous mode. 0: There are 7 CK pulses for an 8 bit frame and 8 CK pulses for a 9 bit frame. 1: There are 8 CK pulses for an 8 bit frame and 9 CK pulses for a 9 bit frame. This bit is reserved for UART3/4.
Page 421 GD32F403xx User Manual This bit enables the CTS hardware flow control function. 0: CTS hardware flow control disabled. 1: CTS hardware flow control enabled . This bit is reserved for UART3/4. RTSEN RTS enable This bit enables the RTS hardware flow control function. 0: RTS hardware flow control disabled.
Page 422 GD32F403xx User Manual When DMA request for reception is enabled (DENR=1), if this bit is set, an interrupt occurs when any one of the FERR, ORERR and NERR bits in USART_STAT0 is set. 0: Error interrupt disabled . 1: Error interrupt enabled . Guard time and prescaler register (USART_GP) 17.4.7.
Page 423 GD32F403xx User Manual Control register 3 (USART_CTL3) 17.4.8. Address offset: 0x80 Reset value: 0x0000 0000 This register is not available for UART3/4. This register has to be accessed by word (32-bit). Reserved Reserved MSBF DINV TINV RINV Reserved EBIE RTIE SCRTNUM[2:0] RTEN Bits...
Page 424 GD32F403xx User Manual RTIE Interrupt enable bit of receive timeout event. If this bit is set, an interrupt occurs when the RTF bit in USART_STAT1 is set. 0: Receive timeout interrupt is enabled. 1: Receive timeout interrupt is disabled. SCRTNUM[2:0] Smartcard auto-retry number.
Page 425 GD32F403xx User Manual USART_STAT1 is written to 0, the Block length counter is reset. 23:0 RT[23:0] Receiver timeout threshold. These bits are used to specify receiver timeout value in terms of number of baud clocks. If Smartcard mode is not enabled, the RTF bit of USART_STAT1 is set if no new start bit is detected longer than RT bits time after the last received character.
Page 426 GD32F403xx User Manual Receiver timeout flag. This bit is set when the RX pin is in idle state for longer than RT bits time. An interrupt occurs if the RTIE bit in USART_CTL3 is set. Software can clear this bit by writing 0 to it. 0: Receiver timeout event does not occur.
Page 427: Figure 18-1. I2C Module Block Diagram
GD32F403xx User Manual Inter-integrated circuit interface (I2C) Overview 18.1. The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. The I2C interface implements standard I2C protocol with standard-mode, fast-mode and fast- mode-plus as well as CRC calculation and checking, SMBus (system management bus) and PMBus (power management bus).
Page 428: Table 18-1. Definition Of I2C-Bus Terminology (Refer To The I2C Specification Of Philips Semiconductors)
GD32F403xx User Manual Figure 18-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register Control Registers Timing and SMBA Control Logic Status Flags DMA/ Interrupts Table 18-1. Definition of I2C-bus terminology (refer to the I2C specification of Philips semiconductors) Term Description...
Page 429: Figure 18-2. Data Validation
GD32F403xx User Manual devices connected to the bus must have an open-drain or open-collect to perform the wired- AND function. Data on the I2C-bus can be transferred at rates of up to 100 Kbit/s in the standard-mode, up to 400 Kbit/s in the fast-mode and up to 1Mbit/s in the fast-mode-plus if the FMPEN bit in I2C_FMPCFG is set.
Page 430: Figure 18-4. Clock Synchronization
GD32F403xx User Manual This is done by clock synchronization and bus arbitration. In a single master system, clock synchronization and bus arbitration are unnecessary. Clock synchronization is performed using the wired-AND connection of I2C interfaces to the SCL line. This means that a HIGH to LOW transition on the SCL line causes the masters concerned to start counting their LOW period and, once a master clock has gone LOW, it holds the SCL line in that state until the clock HIGH state is reached (see Figure 18-4.
Page 431: Figure 18-6. I2C Communication Flow With 7-Bit Address
GD32F403xx User Manual I2C communication flow 18.3.6. Each I2C device is recognized by a unique address (whether it is a microcontroller, LCD driver, memory or keyboard interface) and can be operated as either a transmitter or receiver, depending on the function of the device. An I2C slave will continue to detect addresses after a START signal on I2C bus and compare the detected address with its slave address which is programmed by software.
Page 432 GD32F403xx User Manual ◼ Master Transmitter. ◼ Master Receiver. ◼ Slave Transmitter. ◼ Slave Receiver. I2C block supports all of the four I2C modes. After system reset, it works in slave mode. After sending a START signal on I2C bus, it changes into master mode. The I2C changes back to slave mode after sending a STOP signal on I2C bus.
Page 433: Figure 18-9. Programming Model For Slave Transmitting Mode (10-Bit Address Mode)
GD32F403xx User Manual clears AERR bit by writing 0 to it. Figure 18-9. Programming model for slave transmitting mode (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge...
Page 434: Figure 18-11. Programming Model For Master Transmitting Mode (10-Bit Address Mode)
GD32F403xx User Manual soon as ADDSEND bit is cleared. As soon as the first byte is received, RBNE is set by hardware. Software can now read the first byte from I2C_DATA and RBNE is cleared as well. Any time RBNE is set, software can read a byte from I2C_DATA. After the last byte is received, RBNE is set.
Page 435 GD32F403xx User Manual After sending a START signal, the I2C hardware sets the SBSEND bit in I2C_STAT0 register and enters master mode. Now software should clear the SBSEND bit by reading I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address to I2C_DATA. I2C begins to send address or header to I2C bus as soon as SBSEND bit is cleared.
Page 436 GD32F403xx User Manual Figure 18-11. Programming model for master transmitting mode (10-bit address mode) I2C Line State Software Flow Hardware Action 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends ACK Set ADD10SEND...
Page 437: Figure 18-12. Programming Model For Master Receiving Using Solution A (10-Bit Address Mode)
GD32F403xx User Manual register and enters master mode. Now software should clear the SBSEND bit by reading I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address to I2C_DATA. I2C begins to send address or header to I2C bus as soon as SBSEND bit is cleared. If the address which has been sent is header of a 10-bit address, the hardware sets ADD10SEND bit after sending header and software should clear the ADD10SEND bit by reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA.
Page 438 GD32F403xx User Manual address mode) Hardware I2C Line State Software Flow Action 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address Slave sends Acknowledge...
Page 439: Figure 18-13. Programming Model For Master Receiving Mode Using Solution B
GD32F403xx User Manual ADD10SEND bit after sending header and software should clear the ADD10SEND bit by reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA. After the 7-bit or 10-bit address has been sent, the I2C hardware sets the ADDSEND bit and software should clear the ADDSEND bit by reading I2C_STAT0 and then I2C_STAT1.
Page 440 GD32F403xx User Manual address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND Master sends Header Slave sends Acknowledge Set ADD10SEND SCL stretched by master 4) Clear ADD10SEND Master sends Address...
Page 441 GD32F403xx User Manual register is filled with the next data to be transmitted. When the RBNE and BTC bits are set in receiving mode, the receiver stretches the SCL line low until the data in the transfer buffer is read out. When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register.
Page 442 GD32F403xx User Manual SMBus support 18.3.11. The System Management Bus (abbreviated to SMBus or SMB) is a single-ended simple two- wire bus for the purpose of lightweight communication. Most commonly it is found in computer motherboards for communication with power source for ON/OFF instructions.It is derived from I2C for communication with low-bandwidth devices on a motherboard, especially power related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data).
Page 443: Table18-2. Event Status Flags
GD32F403xx User Manual the address and read/write bit. The polynomial used is x8+x2+x+1 (the CRC-8-ATM HEC algorithm, initialized to zero). SMBus alert The SMBus has an extra optional shared interrupt signal called SMBALERT# which can be used by slaves to tell the host to ask its slaves about events of interest. SMBus also defines a less common "Host Notify Protocol", providing similar notifications which is based on the I2C multi-master mode but it can pass more data.
Page 444 GD32F403xx User Manual Error Name Description AERR No acknowledge received CRC value doesn’t match PECERR SMBTO Bus timeout in SMBus mode SMBALT SMBus Alert...
Page 445 GD32F403xx User Manual Register definition 18.4. I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 Control register 0 (I2C_CTL0) 18.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved PECTRA SRESET Reserved SALT...
Page 446 GD32F403xx User Manual byte 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte ACKEN ACK enable This bit is set and cleared by software and cleared by hardware when I2CEN=0 0: ACK will not be sent 1: ACK will be sent...
Page 447 GD32F403xx User Manual 1: SMBus mode I2CEN I2C peripheral enable 0: I2C is disabled 1: I2C is enabled Control register 1 (I2C_CTL1) 18.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word(16-bit) or word (32-bit) Reserved Reserved DMALST DMAON...
Page 448 GD32F403xx User Manual Reserved Must be kept at reset value. I2CCLK[6:0] I2C peripheral clock frequency I2CCLK[6:0]should be the frequency of input APB1 clock in MHz which is at least 0d – 1d: Not allowed 2d – 60d: 2 MHz~60MHz 61d – 127d: Not allowed due to the limitation of APB1 clock Note: In I2C standard mode, the frequencies of APB1 must be equal or greater than 2MHz.
Page 449 GD32F403xx User Manual This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual -Address mode DUADEN Dual-Address mode enable 0: Dual-Address mode is disabled...
Page 450 GD32F403xx User Manual LOSTAR ADD10S ADDSEN SMBALT SMBTO Reserved PECERR OUERR AERR BERR RBNE Reserved STPDET SBSEND rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0. 0: SMBA pin not pulled down (device mode) or no Alert detected (host mode) 1: SMBA pin pulled down and Alert address received (device mode) or Alert detected (host mode)
Page 451 GD32F403xx User Manual 0: No bus error 1: A bus error detected I2C_DATA is empty during transmitting This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA. If both the shift register and I2C_DATA are empty, writing I2C_DATA won’t clear TBE (refer to Programming Model for detail).
Page 452 GD32F403xx User Manual 0: In slave mode, no address is received or the received address does not match witih its own address. In master mode, no address is sent or address has been sent but not received the ACK from slave. 1: In slave mode, address is received and matches witih its own address.
Page 453 GD32F403xx User Manual This bit is cleared by hardware after a STOP or a START signal or I2CEN=0. 0: No general call address (0x00) received 1: General call address (0x00) received Reserved Must be kept at reset value. Transmitter or receiver This bit indicates whether the I2C is a transmitter or a receiver.
Page 454 GD32F403xx User Manual 13:12 Reserved Must be kept the reset value 11:0 CLKC[11:0] I2C clock control in master mode In standard speed mode: T =CLKC* T high PCLK1 In fast speed mode or fast mode plus, if DTCY=0: =CLKC* T =2*CLKC*T high PCLK1...
Page 455 GD32F403xx User Manual Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. FMPEN Fast mode plus enable The I2C device supports up to 1MHz when this bit is set. 0: Fast mode plus disabled 1: Fast mode plus enabled...
Page 456 GD32F403xx User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) Overview 19.1. The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
Page 457: Figure 19-1. Block Diagram Of Spi
GD32F403xx User Manual SPI function overview 19.3. SPI block diagram 19.3.1. Figure 19-1. Block diagram of SPI SYSCLK MOSI TXBuffer MISO RX Buffer SPI signal description 19.3.2. Normal configuration (Not Quad-SPI Mode) Table 19-1. SPI signal description Pin name Direction Description Master: SPI clock output Slave: SPI clock input...
Page 458: Figure 19-2. Spi Timing Diagram In Normal Mode
GD32F403xx User Manual Pin name Direction Description application. Slave in hardware NSS mode: NSS input, as a chip select signal for slave. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI0).
Page 459: Figure 19-3. Spi Timing Diagram In Quad-Spi Mode (Ckpl=1, Ckph=1, Lf=0)
GD32F403xx User Manual Figure 19-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) sample SCK (CKPH=0 CKPL=0) SCK (CKPH=0 CKPL=1) SCK (CKPH=1 CKPL=0) SCK (CKPH=1 CKPL=1) MOSI D[3] D[0] D[2] D[4] D[5] D[1] D[6] D[7] LF=1 FF16=0 MISO D[2] D[1] D[5] D[6]...
Page 460: Table 19-4. Nss Function In Master Mode
GD32F403xx User Manual (SWNSSEN=1). Then, once the NSS pin (in hardware NSS mode) or the SWNSS bit (in software NSS mode) goes low, the SPI automatically enters to slave mode and triggers a master fault flag CONFERR. If the application wants to use NSS line to control the SPI slave, NSS should be configured to hardware output mode (SWNSSEN=0, NSSDRV=1).
Page 461 GD32F403xx User Manual Mode Description Register Configuration Data Pin Usage MSTMOD = 1 Master Transmission with RO = 0 MOSI: Transmission unidirectional connection BDEN = 0 MISO: Not used BDOEN: Don’t care MSTMOD = 1 Master Reception with RO = 1 MOSI: Not used unidirectional connection BDEN = 0...
Page 462: Figure 19-4. A Typical Full-Duplex Connection
GD32F403xx User Manual Figure 19-4. A typical Full-duplex connection Figure 19-5. A typical simplex connection (Master: Receive, Slave: Transmit) Slave Master MISO MISO MOSI MOSI Figure 19-6. A typical simplex connection (Master: Transmit only, Slave: Receive) Figure 19-7. A typical bidirectional connection Master Slave MTB/MRB...
Page 463 GD32F403xx User Manual SPI initialization sequence Before transmiting or receiving data, application should follow the SPI initialization sequence described below: If master mode or slave TI mode is used, program the PSC [2:0] bits in SPI_CTL0 reg ister to generate SCK with desired baud rate or configure the Td time in TI mode, otherwise, ignore this step.
Page 464: Figure 19-8. Timing Diagram Of Ti Master Mode With Discontinuous Transfer
GD32F403xx User Manual frame, while in full-duplex master mode (MFD), hardware only receives the next data frame when the transmit buffer is not empty. SPI operation sequence in different modes (Not Quad -SPI, TI mode or NSSP mode) In full-duplex mode, either MFD or SFD, application should monitor the RBNE and TBE flags and follow the sequences described above.
Page 465: Figure 19-9. Timing Diagram Of Ti Master Mode With Continuous Transfer
GD32F403xx User Manual Figure 19-9. Timing diagram of TI master mode with continuous transfer In master TI mode, SPI can perform continuous or non-continuous transfer. If the master writes SPI_DATA register fast enough, the transfer is continuous, otherwise non-continuous. In non-continuous transfer there is an extra header clock cycle before each byte. While in continuous transfer, the extra header clock cycle only exists before the first byte and the following bytes’...
Page 466: Figure 19-11. Timing Diagram Of Nss Pulse With Continuous Transmit
GD32F403xx User Manual mode, and frame format should follow the normal SPI protocol, and set the data capture edge to first clock transition. In summary: NSSP = 1; MSTMOD = 1; CKPH = 0; When active, a pluse duration of least 1 SCK clock priod is inserted between successive data frames depending on internal data transmit buffer status, multiple SCK clock cycle interval is possible if the transfer buffer stays empty.
Page 467: Figure 19-12. Timing Diagram Of Quad Write Operation In Quad-Spi Mode
GD32F403xx User Manual Figure 19-12. Timing diagram of quad write operation in Quad-SPI mode Software write SPI_DATA Hardware sets TBE again sample MOSI D0[0] D0[4] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] Quad read operation SPI works in quad read mode when QMOD and QRD are both set in SPI_QCTL register.
Page 468: Figure 19-13. Timing Diagram Of Quad Read Operation In Quad-Spi Mode
GD32F403xx User Manual Figure 19-13. Timing diagram of quad read operation in Quad-SPI mode Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7]...
Page 469 GD32F403xx User Manual Quad-SPI mode Before leaving quad wire mode or disabling SPI, software should first check that, TBE bit is set and TRANS bit is cleared, then the QMOD bit in SPI_QCTL register and SPIEN bit in SPI_CTL0 register are cleared. DMA function 19.3.6.
Page 470: Table 19-6. Spi Interrupt Requests
GD32F403xx User Manual This bit is set when receive buffer is not empty, which means that one data is received and stored in the receive buffer, and software can read the data by reading the SPI_DATA register. ◼ SPI Transmitting On-Going flag (TRANS) TRANS is a status flag to indicate whether the transfer is on-going or not.
Page 471: Figure 19-14. Block Diagram Of I2S
GD32F403xx User Manual Interrupt Flag Description Clear Method Enable bit CRCERR CRC error Write 0 to CRCERR bit FERR TI Mode Format Error Write 0 to FERR bit I2S function overview 19.4. I2S block diagram 19.4.1. Figure 19-14. Block diagram of I2S SYSCLK I2S_MCK SPI_SCK /...
Page 472: Figure 19-15. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F403xx User Manual I2S audio standards 19.4.3. The I2S audio standard is selected by the I2SSTD bits in the SPI_I2SCTL register. Four audio standards are supported, including I2S Phillips standard, MSB justified standard, LSB justified standard, and PCM standard. All standards except PCM handle audio data time-multiplexed on two channels (the left channel and the right channel).
Page 473: Figure 19-17. I2S Phillips Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32F403xx User Manual Figure 19-17. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) Figure 19-18. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) When the packet type is 32-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete a frame.
Page 474: Figure 19-21. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32F403xx User Manual Figure 19-21. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 19-22. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) When the packet type is 16-bit data packed in 32-bit frame, only one write or read operation to or from the SPI_DATA register is needed to complete a frame.
Page 475: Figure 19-26. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32F403xx User Manual Figure 19-26. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 19-27. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 19-28. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) 24-bit data 8-bit 0 Figure 19-29.
Page 476: Figure 19-31. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32F403xx User Manual Figure 19-31. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) Figure 19-32. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) When the packet type is 24-bit data packed in 32-bit frame, two write or read operations to or from the SPI_DATA register are needed to complete a frame.
Page 477: Figure 19-35. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F403xx User Manual synchronization mode and the long frame synchronization mode are available and configurable using the PCMSMOD bit in the SPI_I2SCTL register. The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard. The timing diagrams for each configuration of the short frame synchronization mode are shown below.
Page 478: Figure 19-43. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F403xx User Manual Figure19-40. PCM standard short frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=1) Figure 19-41. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 19-42. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 frame 2 16-bit data...
Page 479: Figure 19-46. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32F403xx User Manual (DTLEN=10, CHLEN=1, CKPL=0) Figure 19-46. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 19-47. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 frame 2 13 bits 24-bit data 8-bit 0 Figure 19-48.
Page 480: Figure 19-51. Block Diagram Of I2S Clock Generator
GD32F403xx User Manual (DTLEN=00, CHLEN=1, CKPL=1) I2S clock 19.4.4. Figure 19-51. Block diagram of I2S clock generator The block diagram of I2S clock generator is shown as Figure 19-51. Block diagram of I2S clock generator. The I2S interf ace clocks are configured by the DIV bits, the OF bit, the MCKOEN bit in the SPI_I2SPSC register and the CHLEN bit in the SPI_I2SCTL register.
Page 481: Figure 19-52. I2S Initialization Sequence
GD32F403xx User Manual Table 19-8. Audio sampling frequency calculation formulas MCKOEN CHLEN Formula I2SCLK / (32 * (DIV * 2 + OF)) I2SCLK / (64 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) I2SCLK / (256 * (DIV * 2 + OF)) Operation 19.4.5.
Page 482 GD32F403xx User Manual Figure 19-52. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the bit is 1 bit, and the MCKOEN bit to define MSTMOD the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity of idle state Configure the I2SSEL bit to select I2S mode Configure the I2SSTD [1:0] bits and the PCMSMOD...
Page 483 GD32F403xx User Manual and no transmission sequence is processing in the shift register. When a half word is written to the SPI_DATA register (TBE goes low), the data is transferred from the transmit buffer to the shift register (TBE goes high) immediately. At the moment, the transmission sequence begins.
Page 484: Figure 19-53. I2S Master Reception Disabling Sequence
GD32F403xx User Manual Figure 19-53. I2S master reception disabling sequence Start If DTLEN == 2b'00&&CHLEN == 2b'1 && I2SSTDSEL ==2b'10 ? If DTLEN == 2b'00&&CHLEN == Wait for the second last RBNE 2b'1 && I2SSTDSEL !=2b'10 ? Wait for the last RBNE Wait for the second last RBNE Wait 17 I2S CK clock (clock on Wait one I2S clock cycle...
Page 485 GD32F403xx User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The difference between them is described below. In slave mode, the slave has to be enabled before the external master starts the communication.
Page 486: Table 19-10. I2S Interrupt
GD32F403xx User Manual In the slave transmit mode, when the valid SCK signal starts transmitting, if the transmit buffer is empty, TXURERR will be set. ◼ Reception Overrun Error Flag (RXORERR) This condition occurs when the receive buffer is full and a newly incoming data has been completely received.
Page 487 GD32F403xx User Manual Register definition 19.5. SPI0 base address: 0x4001 3000 SPI1/I2S1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 Control register 0 (SPI_CTL0) 19.5.1. Address offset: 0x00 Reset value: 0x0000 This register has to be accessed by word (32-bit) This register has no meaning in I2S mode.
Page 488 GD32F403xx User Manual In full-duplex or transmit-only mode, set this bit after the last data is written to SPI_DATA register. In receive only mode, set this bit after the sec ond last data is received. FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only When BDEN is cleared, this bit determines the direction of transfer.
Page 489 GD32F403xx User Manual CKPH Clock phase selection 0: Capture the first data at the first clock transition 1: Capture the first data at the second clock transition Control register 1 (SPI_CTL1) 19.5.2. Address offset: 0x04 Reset value: 0x0000 This register has to be accessed by word (32-bit) Reserved Reserved TBEIE...
Page 490 GD32F403xx User Manual If the NSS pin is configured as input, the NSS pin should be pulled high in master mode, and this bit has no effect. DMATEN Transmit buffer DMA enable 0: Transmit buffer DMA is disabled 1: Transmit buffer DMA is enabled . When the TBE bit in SPI_STAT is set, it will generate a DMA request at corresponding DMA channel.
Page 491 GD32F403xx User Manual 1: Reception overrun error occurs. This bit is set by hardware and cleared by a read operation on the SPI_DATA register followed by a read access to the SPI_STAT register. CONFERR SPI configuration error bit 0: No configuration fault occurs 1: Configuration fault occurred.
Page 492 GD32F403xx User Manual Reserved SPI_DATA[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 SPI_DATA[15:0] Data transfer register The hardware has two buffers, including transmit buffer and receive buffer. Write data to SPI_DATA will save the data to transmit buffer and read data from SPI_DATA will get the data from receive buffer.
Page 493 GD32F403xx User Manual Reset value: 0x0000 This register has to be accessed by word(32-bit). Reserved RCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RCRC[15:0] RX CRC register When the CRCERRN bit of SPI_CTL0 is set, the hardware computes the CRC value of the received bytes and saves them in RCR register.
Page 494 GD32F403xx User Manual value in TCRC [7:0]. When the Data frame format is set to 16-bit data, CRC calculation is based on CRC16 standard, and saves the value in TCRC [15:0]. The hardware computes the CRC value after each transmitted bit, when the TRANS is set, a read to this register could return an intermediate value.
Page 495 GD32F403xx User Manual This bit has a meaning only when PCM standard is used. This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode. Reserved Must be kept at reset value. I2SSTD[1:0] I2S standard selection 00: I2S Phillips standard 01: MSB justified standard...
Page 496 GD32F403xx User Manual Reserved MCKOEN DIV[7:0] Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. MCKOEN I2S_MCK output enable 0: I2S_MCK output is disabled 1: I2S_MCK output is enabled This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode.
Page 497 GD32F403xx User Manual Quad-SPI mode read select. 0: SPI is in quad wire write mode 1: SPI is in quad wire read mode This bit should be only be configured when SPI is not busy (TRANS bit cleared) This bit is only available in SPI0. Quad-SPI mode enable QMOD 0: SPI is in single wire mode...
Page 498 GD32F403xx User Manual Secure digital input/output interface (SDIO) 20.1. Introduction The secure digital input/output interface (SDIO) defines the SD, SD I/O, MMC and CE-ATA card host interface, which provides command/data transfer between the AHB system bus and SD memory cards, SD I/O cards, Multimedia Card (MMC) and CE-ATA devices. The supported SD memory card and SD I/O card system specifications are defined in the SD card Association website at www.sdcard.org.
Page 499: Figure 20-1. Sdio "No Response" And "No Data" Operations
GD32F403xx User Manual Response: a response is a token which is sent from the card to the host as an answer to a previously received command. A response is transferred serially on the CMD line. Data: data can be transferred from the card to the host or vice versa. Data is transferred via the data lines.
Page 500: Figure 20-2. Sdio Multiple Blocks Read Operation
GD32F403xx User Manual has an optional busy before it is ready to receive the data. Figure 20-2. SDIO multiple blocks read operation Figure 20-3. SDIO multiple blocks write operation Data transfers to/from SD memory cards, SD I/O cards (both IO only card and combo card) and CE-ATA device are done in data blocks.
Page 501: Figure 20-5. Sdio Sequential Write Operation
GD32F403xx User Manual Figure 20-5. SDIO sequential write operation 20.4. SDIO functional description The following figure shows the SDIO structure. There have two main parts: ◼ The SDIO adapter block consists of control unit which manage clock, command unit which manage command transfer, data unit which manage data transfer. ◼...
Page 502: Table 20-1. Sdio I/O Definitions
GD32F403xx User Manual a one bit transfer on the command line (SDIO_CMD) and on all the data lines (SDIO_DAT). The SDIO_CLK frequency can vary between 0 MHz and 20 MHz for a Multimedia Card V3.31, between 0 and 48 MHz for a Multimedia Card V4.2, or between 0 and 25 MHz for an SD/SD I/O card.
Page 503 GD32F403xx User Manual avoid the corresponded error. Only state machines are frozen, the AHB interface is still alive. So, the FIFO can access by AHB bus. Command unit The command unit implements command transfer to the card. The data transfer flow is controlled by Command State Machine (CSM).
Page 504 GD32F403xx User Manual CS_Receive Receive the response and check the CRC. → 1.Response Received in CE-ATA mode and CS_Waitcompl interrupt disabled and wait for CE-ATA Command Completion signal enabled → 2.Response Received in CE-ATA mode and CS_Pend interrupt disabled and wait for CE-ATA Command Completion signal disabled →...
Page 505 GD32F403xx User Manual DS_Send Transmit data to the card. → 1.Data block transmitted DS_Busy → 2.DSM disabled DS_Idle → 3.Data FIFO underrun error occurs DS_Idle → 4. Internal CRC error DS_Idle DS_Busy Waits for the CRC status flag. → 1.Receive a positive CRC status DS_WaitS →...
Page 506 GD32F403xx User Manual and memory. The following example describes how to implement this method: 1. Complete the card identification process 2. Increase the SDIO_CLK frequency 3. Send CMD7 to select the card and configure the bus width 4. Configure the DMA1 as follows: Enable DMA1 controller and clear any pending interrupts.
Page 507 GD32F403xx User Manual 20.5. Card functional description Card registers 20.5.1. Within the card interface registers are defined: OCR, CID, CSD, EXT_CSD, RCA, DSR and SCR. These can be accessed only by corresponding commands. The OCR, CID, CSD and SCR registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters.
Page 508: Figure 20-7. Command Token Format
GD32F403xx User Manual length, transfer rate or number of cards). The CSD register carries the information about the DSR register usage. The default value of the DSR register is 0x404. The host can use CMD4 to get the content of this register. SCR register: Just SD/SD I/O (if has memory port) have this register.
Page 509: Table 20-3. Card Command Classes (Cccs)
GD32F403xx User Manual a CRC7. Every command code word is terminated by the end bit (always 1). Command classes The command set of the Card system is divided into several classes (See Table 20-3. Card command classes (CCCs)). Each class supports a set of card functionalities. Table 20-3.
Page 510 GD32F403xx User Manual CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD32 CMD33 CMD34 CMD35 CMD36 CMD37 CMD38 CMD39 CMD40 CMD42 CMD50 CMD52 CMD53 CMD55 CMD56 CMD57...
Page 511: Table 20-4. Basic Commands (Class 0)
GD32F403xx User Manual ACMD6 ACMD13 ACMD22 ACMD23 ACMD41 ACMD42 ACMD51 Note: 1.CMD1, CMD11, CMD14, CMD19, CMD20, CMD23, CMD26, CMD39 and CMD40 are only available for MMC.CMD5, CMD32-34, CMD50, CMD52, CMD53, CMD57 and ACMDx are only available for SD card. CMD60, CMD61 are only available for CE-ATA device. 2.
Page 512 GD32F403xx User Manual [31:26] Set to 0 [25:24] Access Only for MMC. Switches the [23:16] Index mode of operation of the selected CMD6 SWITCH [15:8] Value card or modifies the EXT_CSD [7:3] Set to 0 registers. [2:0] Cmd Set Command toggles card between...
Page 513: Table 20-5. Block-Oriented Read Commands (Class 2)
GD32F403xx User Manual Table 20-5. Block-Oriented read commands (class 2) Response type argument Abbreviation Description index format In the case of a Standard Capacity SD and MMC, this command sets the block length (in bytes) for all following block commands (read, write, lock). Default is 512 Bytes.
Page 514: Table 20-6. Stream Read Commands (Class 1) And Stream Write Commands (Class 3)
GD32F403xx User Manual Table 20-6. Stream read commands (class 1) and stream write commands (class 3) Response type argument Abbreviation Description index format Reads data stream from the card, [31:0] data READ_DAT_UNTI starting at the given address, CMD11 adtc address L_STOP until a STOP_TRANSMISSIO N follows.
Page 515: Table 20-8. Erase Commands (Class 5)
GD32F403xx User Manual Response type argument Abbreviation Description index format Programming card identification register. This command shall be issued only once. card contains CMD26 adtc [31:0] stuff bits PROGRAM_CID hardware prevent this operation after first programming. Normally this command is reserved for the manufacturer.
Page 516: Table 20-9. Block Oriented Write Protection Commands (Class 6)
GD32F403xx User Manual Table 20-9. Block oriented write protection commands (class 6) Response type argument Abbreviation Description index format If the card has write protection features, this command sets the write protection bit addressed group. The properties [31:0] data SET_WRITE_PRO of write protection are coded in CMD28 address...
Page 517: Table 20-11. Application-Specific Commands (Class 8)
GD32F403xx User Manual Table 20-11. Application-specific commands (class 8) Response type argument Abbreviation Description index format Sends host capacity support information (HCS) and asks [31]reserved bit the accessed card to send its [30]HCS operating condition [29:24]reserved SD_SEND_OP_ register(OCR) content in the ACMD41 bits COND...
Page 518: Table 20-12. I/O Mode Commands (Class 9)
GD32F403xx User Manual Table 20-12. I/O mode commands (class 9) Response type argument Abbreviation Description index format Used to write and read 8 bit (register) data fields. The command addresses a card and a register and provides the [31:16] RCA data for writing if the write flag [15] register write is set.
Page 519: Table 20-13. Switch Function Commands (Class 10)
GD32F403xx User Manual Response type argument Abbreviation Description index format Count Note: 1.CMD39, CMD40 are only for MMC. 2. CMD52, CMD53 are only for SD I/O card. Table 20-13. Switch function commands (class 10) Response type argument Abbreviation Description index format [31] Mode 0:Check function...
Page 520: Figure 20-8. Response Token Format
GD32F403xx User Manual ◼ R7 : Card interface condition. The SD Memory Card support five types of them, R1 / R1b, R2, R3, R6, R7. And the SD I/O Card and MMC supports additional response types named R4 and R5, but they are not exactly the same for SD I/O Card and MMC.
Page 521: Table 20-15. Response R2
GD32F403xx User Manual R2 (CID, CSD register) Code length is 136 bits. The contents of the CID register are sent as a response to the commands CMD2 and CMD10. The contents of the CSD register are sent as a res ponse to CMD9.
Page 522: Table 20-18. Response R4 For Sd I/O
GD32F403xx User Manual unique SD I/O response R4. Table 20-18. Response R4 for SD I/O [45:40] 39 [38:36] [34:32] 31 [30:8] [7:1] position Width ‘1111 ‘1111 ‘0’ ‘0’ ‘000’ Value 11’ 111’ Number descripti start transmiss Reser Memory Stuff Reser ion bit Present Bits...
Page 523: Figure 20-9. 1-Bit Data Bus Width
GD32F403xx User Manual ‘0’ ‘0’ ‘000011’ ‘1’ Value start transmission New published RCA card status description CMD3 CRC7 of the card bits:23,22,19,12:0 R7 (Card interface condition) For SD memory only. Code length is 48 bits. The card support voltage information is sent by the response of CMD8.
Page 524: Figure 20-10. 4-Bit Data Bus Width
GD32F403xx User Manual 4-bit data packet format Figure 20-10. 4-bit data bus width Start Byte Byte Byte Byte … … DAT3 … … DAT2 … … DAT1 … … DAT0 8-bit data packet format Figure 20-11. 8-bit data bus width Start Byte Byte...
Page 525: Table 20-23. Card Status
GD32F403xx User Manual Type •E: Error bit. Send an error condition to the host. These bits are cleared as soon as the response (reporting the error) is sent out. •S: Status bit. These bits serve as information fields only, and do not alter the execution of the command being responded to.
Page 526 GD32F403xx User Manual ’1’= error password error been detected in lock/unlock card command. ’0’= no error COM_CRC_ERROR The CRC check of the previous ’1’= error command failed. ’0’= no error ILLEGAL_COMMAND Command not legal for the card ’1’= error state. ’0’= success CARD_ECC_FAILED Card internal ECC was applied...
Page 527 GD32F403xx User Manual 1 = ready receiving the command. If the 2 = identification command execution causes a 3 = stand by state change, it will be visible to 4 = transfer the host in the response to the 5 = send data next command.
Page 528: Table 20-24. Sd Status
GD32F403xx User Manual Table 20-24. SD status Bits Identifier Type Value Description Clear Condition ’00’= 1 (default) [511: DAT_BUS_WIDTH Shows the currently defined ‘01’= reserved 510] data bus width that was defined ‘10’= 4 bit width SET_BUS_WIDT H ‘11’= reserved command ’0’= Not in the...
Page 529: Table 20-25. Performance Move Field
GD32F403xx User Manual Bits Identifier Type Value Description Clear Condition time. [399: reserved 312] [311: reserved for manufacturer SIZE_OF_PROTECTED_AREA Setting this field differs between SDSC and SDHC/SDXC. In case of SDSC Card, the capacity of protected area is calculated as follows: Protected Area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN.
Page 530: Table 20-26. Au_Size Field
GD32F403xx User Manual PERFORMANCE_MOVE Value Definition Infinity AU_SIZE This 4-bit field indicates AU Size and the value can be selected from 16 KB. Table 20-26. AU_SIZE field AU_SIZE Value Definition Not Defined 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB...
Page 531: Table 20-29. Erase Timeout Field
GD32F403xx User Manual ERASE_SIZE Value Definition 0003h 3 AU ....FFFFh 65535 AU ERASE_TIMEOUT This 6-bit field indicates the T and the value indicates erase timeout from offset when ERASE multiple AUs are erased as specified by ERASE_SIZE. The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of ERASE_SIZE and ERASE_TIMEOUT depending...
Page 532 GD32F403xx User Manual voltage range, identifies cards and asks them to publish Relative Card Address (RCA). This operation is done to each card separately on its own CMD line. All data communication in the Card Identification Mode uses the command line (CMD) only. During the card identification process, the card shall operate in the clock f requency of the identification clock rate F (400 kHz).
Page 533 GD32F403xx User Manual 1. Check if the card is connected. 2. Identify the card type; SD, MMC(CE-ATA), or SD I/O. – Send CMD5 first. If a response is received, then the card is SD I/O – If not, send ACMD41; if a response is received, then the card is SD. –...
Page 534 GD32F403xx User Manual Single block or multiple block write 20.6.3. During block write (CMD24 - 27) one or more blocks of data are transferred from the host to the card. The block consists of start bits (1 or 4 bits LOW), data block, CRC and end bits(1 or 4 bits HIGH).
Page 535 GD32F403xx User Manual task file, then use CMD61 to write the data. After writing to the CMD register, host starts executing a command, when the command is sent to the bus, the CMDRECV flag is set. 5. Write data to SDIO_FIFO. 6.
Page 536 GD32F403xx User Manual read and CMD18 for a multiple-block read. For SD I/O cards, using CMD53 for both single- block and multiple-block transfers. For CE-ATA, first using CMD60 to write the ATA task file, then using CMD 61 to read the data. After writing to the CMD register, the host starts executing the command, when the command is sent to the bus, the CMDRECV flag is set.
Page 537 GD32F403xx User Manual the card may not be able to process the data and will stop programming, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop command. As the host sends CMD12, the card will respond with the TXURE bit set and return to Transfer state Stream read There is a stream oriented data transfer controlled by READ_DAT_UNTIL_STOP (CMD11).
Page 538 GD32F403xx User Manual write blocks which are the basic writable units of the card. The size of the Erase Group is a card specific parameter and defined in the CSD. The host can erase a contiguous range of Erase Groups. Starting the erase process is a three steps sequence.
Page 539 GD32F403xx User Manual Protection management 20.6.8. In order to allow the host to protect data against erase or write, three methods for the cards are supported in the card: CSD register for card protection (optional) The entire card may be write protected by setting the permanent or temporary write protect bits in the CSD.
Page 540: Table 20-31. Lock Card Data Structure
GD32F403xx User Manual card data structure describes the structure of the command data block. Table 20-31. Lock card data structure Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved(all set to 0) ERASE LOCK_UNLOCK CLR_PWD...
Page 541 GD32F403xx User Manual Reset the password ⚫ Select a card (CMD7), if not previously selected. ⚫ Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-bit password size (in bytes), and the number of bytes of the currently used password. ⚫...
Page 542: Figure 20-12. Read Wait Control By Stopping Sdio_Clk
GD32F403xx User Manual Read Wait operation Suspend/resume operation Interrupts The SD I/O supports these operations only if the SDIO_DATACTL[11] bit is set, except for read suspend that does not need specific hardware implementation. SD I/O read wait operation The optional Read Wait (RW) operation is defined only for the SD 1-bit and 4-bit modes. The Read Wait operation allows a host to signal a card that is executing a read multiple (CMD53) operation to temporarily stall the data transfer while allowing the host to send commands to any function within the SD I/O card.
Page 543: Figure 20-14. Function2 Read Cycle Inserted During Function1 Multiple Read Cycle
GD32F403xx User Manual SDIO_DATACTL[8] = 1) and data direction is from card to SD I/O (SDIO_DATACTL[1] = 1), the DSM directly moves from Idle to Read Wait. In Read Wait the DSM drives SDIO_DAT[2] to 0 af ter 2 SDIO_CLK clock cycles. In this state, when you set the RWSTOP bit (SDIO_DATACTL[9]), the DSM remains in Wait for two more SDIO_CLK clock cycles to drive SDIO_DAT[2] to 1 f or one clock cycle.
Page 544: Figure 20-15. Read Interrupt Cycle Timing
GD32F403xx User Manual on the SD interf ace. Pin number 8, which is used as SDIO_DAT[1] when operating in the 4- bit SD mode, is used to signal the card’s interrupt to the host. The use of interrupt is optional f or each card or f unction within a card.
Page 545: Figure 20-17. Multiple Block 4-Bit Read Interrupt Cycle Timing
GD32F403xx User Manual during a 4-bit multi-block write Figure 20-17. Multiple block 4-Bit read interrupt cycle timing Figure 20-18. Multiple block 4-Bit write interrupt cycle timing CE-ATA specific operations 20.7.2. The CE-ATA device supports these specific operations: Receive command completion signal Send command completion disable signal The SDIO supports these operations only when SDIO_CMDCTL[14] is set.
Page 546: Figure 20-19. The Operation For Command Completion Disable Signal
GD32F403xx User Manual Command completion disable signal The host may cancel the ability for the device to return a command completion signal by issuing the command completion signal d isable. The host shall only issue the command completion signal disable when it has received an R1b response f or an outstanding RW_MULTIPLE_BLOCK (CMD61) command.
Page 547 GD32F403xx User Manual 20.8. SDIO registers SDIO base address: 0x4001 8000 Power control register (SDIO_PWRCTL) 20.8.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved PWRCTL[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value PWRCTL[1:0] SDIO power control bits.
Page 548 GD32F403xx User Manual Bits Fields Descriptions DIV[8] MSB of Clock division This field defines the MSB division between the input clock (SDIOCLK) and the output clock, refer to bit 7:0 of SDIO_CLKCTL 30:15 Reserved Must be kept at reset value. HWCLKEN Hardware Clock Control enable bit If this bit is set, hardware controls the SDIO_CLK on/off depending on the system...
Page 549 GD32F403xx User Manual Command argument register (SDIO_CMDAGMT) 20.8.3. Address offset: 0x08 Reset value: 0x0000 0000 This register defines 32 bit command argument, which will be used as part of the command (bit 39 to bit 8). This register has to be accessed by word(32-bit) CMDAGMT[31:16] CMDAGMT[15:0] Bits...
Page 550 GD32F403xx User Manual NINTEN No CE-ATA Interrupt (CE-ATA only) This bit defines if there is CE-ATA interrupt or not. This bit is only used when CE- ATA card. 0: CE-ATA interrupt enable 1: CE_ATA interrupt disable ENCMDC CMD completion signal enabled (CE-ATA only) This bit defines if there is command completion signal or not in CE-ATA card.
Page 551: Table 20-32. Sdio_Respx Register At Different Response Type
GD32F403xx User Manual Command index response register (SDIO_RSPCMDIDX) 20.8.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RSPCMDIDX[5:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value RSPCMDIDX[5:0] Last response command index Read-only bits field.
Page 552 GD32F403xx User Manual Register Short response Long response SDIO_RESP2 reserved Card response [63:32] SDIO_RESP3 reserved Card response [31:1],plus bit 0 Data timeout register (SDIO_DATATO) 20.8.7. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) DATATO[31:16] DATATO[15:0] Bits...
Page 553 GD32F403xx User Manual starts, the data counter loads this register and starts decrement. If block data transfer selected, the content of this register must be a multiple of the block Note: size (ref er to SDIO_DATACTL). The data timer register and the data length register must be updated before being written to the data control register when need a data transfer.
Page 554 GD32F403xx User Manual 0101: block size = 2 = 32 bytes 0110: block size = 2 = 64 bytes 0111: block size = 2 = 128 bytes 1000: block size = 2 = 256 bytes 1001: block size = 2 = 512 bytes 1010: block size = 2 = 1024 bytes...
Page 555 GD32F403xx User Manual Bits Fields Descriptions 31:25 Reserved Must be kept at reset value 24:0 DATACNT[24:0] Data count value Read-only bits field. When these bits are read, the number of remaining data bytes to be transferred is returned. Status register (SDIO_STAT) 20.8.11.
Page 556 GD32F403xx User Manual Transmit FIFO is full Receive FIFO is half full: at least 8 words can be read in the FIFO Transmit FIFO is half empty: at least 8 words can be written into the FIFO RXRUN Data reception in progress TXRUN Data transmission in progress CMDRUN...
Page 557 GD32F403xx User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value ATAENDC ATAEND flag clear bit Write 1 to this bit to clear the flag. SDIOINTC SDIOINT flag clear bit Write 1 to this bit to clear the flag. 21:11 Reserved Must be kept at reset value...
Page 558 GD32F403xx User Manual ATAENDI SDIOINTI RXDTVA TXDTVAL Reserved RFEIE TFEIE RFFIE TFFIE CMDRUN DTBLKE CMDSEN CMDREC DTTMOU CMDTMO DTCRCE CCRCER RFHIE TFHIE RXRUNIE TXRUNIE STBITEIE DTENDIE RXOREIE TXUREIE NDIE UTIE RRIE Bits Fields Descriptions 31:24 Reserved Must be kept at reset value ATAENDIE CE-ATA command completion signal received interrupt enable Write 1 to this bit to enable the interrupt.
Page 559 GD32F403xx User Manual Write 1 to this bit to enable the interrupt. STBITEIE Start bit error interrupt enable Write 1 to this bit to enable the interrupt. DTENDIE Data end interrupt enable Write 1 to this bit to enable the interrupt. CMDSENDIE Command sent interrupt enable Write 1 to this bit to enable the interrupt.
Page 560 GD32F403xx User Manual These bits define the remaining number words to be written or read from the FIFO. It loads the data length register (SDIO_DATALEN[24:2] if SDIO_DATALEN is word-aligned or SDIO_DATALEN[24:2]+1 if SDIO_DATALEN is not word -aligned) when DATAEN is set, and start count decrement when a word write to or read from the FIFO.
Page 561 GD32F403xx User Manual External memory controller (EXMC) Overview 21.1. The external memory controller EXMC, is used as a translator for MCU to access a variety of external memory. By configuring the related registers, it can automatically convert AMBA memory access protocol into a specific memory access protocol, such as SRAM, ROM, NOR Flash, NAND Flash and PC Card.
Page 562: Figure 21-1. The Exmc Block Diagram
GD32F403xx User Manual Figure 21-1. The EXMC block diagram AHB Bus Interface HCLK EXMC from clock interrupt controller to NVIC EXMC Configuration Register NAND-Flash/PC Card NOR-Flash/PSRAM Controller Controller NOR/PSR Share PSRAM NAND PC Card NOR/PSRA AM/NAND d Pins Pins Pins Pins M Pins Shared Pin...
Page 563: Figure 21-2. Exmc Memory Banks
GD32F403xx User Manual External device address mapping 21.3.3. Figure 21-2. EXMC memory banks Supported memory Address Banks type 0x6000 0000 NOR/PSRAM 0x6FFF FFFF 0x7000 0000 0x7FFF FFFF NAND 0x8000 0000 0x8FFF FFFF 0x9000 0000 PC Card 0x9FFF FFFF EXMC access space is divided into multiple banks. Each bank is 256 Mbytes. The f irst bank (Bank0) is f urther divided into f our regions, and each region is 64 Mbytes.
Page 564 GD32F403xx User Manual Figure 21-3. Four regions of bank0 address mapping Supported memory HADDR[27:26] Address Regions type 0x6000 0000 Region0 NOR/PSRAM 0x63FF FFFF 0x6400 0000 Region1 NOR/PSRAM 0x67FF FFFF 0x6800 0000 Region2 NOR/PSRAM 0x6BFF FFFF 0x6C000000 Region3 NOR/PSRAM 0x6FFF FFFF HADDR[25:0] is the byte address whereas the external memory may not be byte accessed, this will lead to address inconsistency.
Page 565: Figure 21-4. Nand/Pc Card Address Mapping
GD32F403xx User Manual Figure 21-4. NAND/PC Card address mapping EXMC Memory Memory Space Address Bank 0x7000_0000 Common Memory Space 0x73FF_FFFF Bank1 0x7800_0000 Attribute Memory Space 0x7BFF_FFFF 0x8000_0000 Common Memory Space 0x83FF_FFFF Bank2 0x8800_0000 Attribute Memory Space 0x8BFF_FFFF 0x9000_0000 Common Memory Space 0x93FF_FFFF 0x9800_0000...
Page 566: Table 21-1. Nor Flash Interface Signals Description
GD32F403xx User Manual HADDR [17:16] bits are used to select one of the three areas. – When HADDR [17:16] = 00, the data area is selected. – When HADDR [17:16] = 01, the command area is selected. – When HADDR [17:16] = 1X, the address area is selected. Application software uses these three areas to access NAND Flash, their definitions are as f ollows.
Page 567: Table 21-2. Psram Non-Muxed Signal Description
GD32F403xx User Manual EXMC Pin Direction Mode Functional description (muxed) Async/Sync Input/output Data bus (non-muxed) Chip selection, EXMC_NE[x] Output Async/Sync x=0/1/2/3 EXMC_NOE Output Async/Sync Read enable EXMC_NWE Output Async/Sync Write enable EXMC_NWAIT Input Async/Sync Wait input signal EXMC_NL(NADV) Output Async/Sync Address valid Table 21-2.
Page 568: Table 21-4. Nor / Psram Controller Timing Parameters
GD32F403xx User Manual Memory Memory Access Mode Transaction Transaction Comments Size Size Use of byte lanes Async EXMC_NBL[1:0] Async Async Split into 2 EXMC Async accesses Split into 2 EXMC Async accesses Sync Sync Use of byte lanes Sync EXMC_NBL[1:0] Sync Sync Async...
Page 569: Table 21-5. Exmc_Timing Models
GD32F403xx User Manual Parameter Function Access mode Unit DSET Data setup time Async HCLK AHLD Address hold time Async(muxed) HCLK ASET Address setup time Async HCLK Table 21-5. EXMC_timing models Timing Extend Write timing Read timing Mode description model mode parameter parameter DSET...
Page 570: Figure 21-6. Mode 1 Read Access
GD32F403xx User Manual Figure 21-6. Mode 1 read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 2 HCLK (ASET+1 HCLK) (DSET+1 HCLK) Figure 21-7.
Page 571: Figure 21-8. Mode A Read Access
GD32F403xx User Manual Bit Position Bit Name Reference Setting Value NREN No effect Depends on memory NRTP Depends on memory, except 2(Nor Flash) NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 0x0000 29-28 ASYNCMOD No effect 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to 19-16 BUSLAT...
Page 572: Figure 21-9. Mode A Write Access
GD32F403xx User Manual Figure 21-9. Mode A write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The different between mode A and mode 1 write timing is that read/write timing is specified by the same set of timing configuration, while mode A write timing configuration is independent of its read configuration.
Page 573: Figure 21-10. Mode 2/B Read Access
GD32F403xx User Manual Bit Position Bit Name Reference Setting Value Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD No effect ASET Depends on memory and user EXMC_SNWTCFGx(Write) 31-30 Reserved...
Page 574: Figure 21-11. Mode 2 Write Access
GD32F403xx User Manual Figure 21-11. Mode 2 write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (ASET+1 HCLK) (DSET HCLK) Figure 21-12. Mode B write access Address (EXMC_A[25:0]) Chip Enable...
Page 575: Figure 21-13. Mode C Read Access
GD32F403xx User Manual Bit Position Bit Name Reference Setting Value NREN Depends on memory NRTP 0x2，NOR Flash NRMUX NRBKEN EXMC_SNTCFGx(Read and write in mode 2,read in mode B) 31-30 Reserved 0x0000 29-28 ASYNCMOD Mode B:0x1 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to...
Page 576: Figure 21-14. Mode C Write Access
GD32F403xx User Manual Figure 21-14. Mode C write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WDSET HCLK) The different between mode C and mode 1 write timing is that read/write timing is specified by the same set of timing conf iguration, while mode C write timing conf iguration is independent of its read configuration.
Page 577: Figure 21-15. Mode D Read Access
GD32F403xx User Manual Bit Position Bit Name Reference Setting Value Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge Depends on memory and user (DSET+3 HCLK for 15-8 DSET read) AHLD ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved 29-28...
Page 578: Figure 21-16. Mode D Write Access
GD32F403xx User Manual Figure 21-16. Mode D write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time 1 HCLK (WASET+1 HCLK) (WAHLD+1 HCLK) (WDSET HCLK) Table 21-10.
Page 579: Figure 21-17. Multiplex Mode Read Access
GD32F403xx User Manual Bit Position Bit Name Reference Setting Value AHLD Depends on memory and user ASET Depends on memory and user EXMC_SNWTCFGx 31-30 Reserved 29-28 WASYNCMOD Mode D:0x3 27-20 Reserved 0x00 Time between EXMC_NE[x] rising edge to 19-16 WBUSLAT EXMC_NE[x] falling edge Depends on memory and user (WDSET+1HCLK 15-8...
Page 580: Table 21-11. Multiplex Mode Related Registers Configuration
GD32F403xx User Manual Table 21-11. Multiplex mode related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31-20 Reserved 0x000 SYNCWR 18-16 ASYNCWTEN Depends on memory EXMODEN NRWTEN Depends on memory NRWTCFG No effect WRAPEN NRWTPOL Meaningful only when the bit 15 is set to 1 SBRSTEN Reserved NREN...
Page 581: Figure 21-19. Read Access Timing Diagram Under Async-Wait Signal Assertion
GD32F403xx User Manual maxT ≥ T (21-2) WAIT_ASSERTION ADDRES_PHASE HOLD_PHASE ≥(maxT )+4HCLK (21-3) DATA_SETUP WAIT_ASSERTION ADDRES_PHASE HOLD_PHASE Otherwise ≥ 4HCLK (21-4) DATA_SETUP Figure 21-19. Read access timing diagram under async-wait signal assertion Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Wait (EXMC_NWAIT) NRWTPOL = 0 Wait (EXMC_NWAIT) NRWTPOL = 1...
Page 582 GD32F403xx User Manual in the EXMC_SNTCFGx register. 1. Data latency and NOR Flash latency Data latency is the number of EXMC_CLK cycles to wait bef ore sampling the data. The relationship between data latency and NOR Flash specification’s latency parameter is as f ollows: For NOR Flash’s specification excluding the EXMC_NADV cycle, their relationship should be: NOR Flash latency=DLAT+2...
Page 583: Figure 21-21. Read Timing Of Synchronous Multiplexed Burst Mode
GD32F403xx User Manual a burst transmission whose length is 1. If the needed data of AHB is 32-bit, EXMC will make the transmission divided into two 16-bit transmissions, that is, EXMC perf orms a burst transmission whose length is 2. For other configurations please ref ers to Table 21-3.
Page 584: Figure 21-22. Write Timing Of Synchronous Multiplexed Burst Mode
GD32F403xx User Manual Bit Position Bit Name Reference Setting Value EXMC_SNCTLx NRTP Depends on memory，0x1/0x2 NRMUX 0x1, Depends on memory and users NRBKEN EXMC_SNTCFGx(Read) 31-30 Reserved 29-28 ASYNCMOD 27-24 DLAT Data latency 23-20 CKDIV The figure above：0x1,EXMC_CLK=2HCLK Time between EXMC_NE[x] rising edge to 19-16 BUSLAT EXMC_NE[x] falling edge...
Page 585: Table 21-14. 8-Bit Or 16-Bit Nand Interface Signal
GD32F403xx User Manual Bit Position Bit Name Reference Setting Value EXMC_SNCTLx AYSNCWAIT EXMODEN NRWTEN Depends on memory WREN NRWTCFG 0x0(Here must be zero) WRAPEN NTWTPOL Depends on memory SBRSTEN No effect Reserved NREN Depends on memory NRTP NRMUX 0x1, Depends on users NRBKEN EXMC_SNTCFGx(Write) 31-30...
Page 586: Table 21-15. 16-Bit Pc Card Interface Signal
GD32F403xx User Manual EXMC Pin Direction Functional description EXMC_NOE(NR Output Output enable EXMC_NWE Output Write enable EXMC_NWAIT/ Input NAND Flash ready/busy input signal to the EXMC, x=1, 2 EXMC_INT[x] Table 21-15. 16-bit PC Card interface signal EXMC Pin Direction Functional description EXMC_A[10:0] Output Address bus of PC Card...
Page 587: Figure 21-23. Access Timing Of Common Memory Space Of Pc Card Controller
GD32F403xx User Manual devices. Each bank has a corresponding register to manage and control the external memory, such as EXMC_NPCTLx, EXMC_NPINTENx, EXMC_NPCTCFGx, EXMC_NPATCFGx, EXMC_PIOTCFG3 and EXMC_NECCx. Among these registers, EXMC_NPCTCFGx, EXMC_NPATCFGx, EXMC_PIOTCFG3 registers contain four timing parameters individually which are conf igured according to user specification and features of the external memory. Table 21-17.
Page 588: Figure 21-24. Access To None "Nce Don't Care" Nand Flash
GD32F403xx User Manual When EXMC sends command or address to NAND Flash, it needs to use the command latch signal (A [16]) or address latch signal (EXMC_A [17]), namely, the CPU needs to perform write operation in particular address. Example: NAND Flash read operation steps: Conf igure EXMC_NPCTLx and EXMC_NPCTCFGx register.
Page 589 GD32F403xx User Manual Write ADD0 into NAND Flash bank common space address area. Write ADD1 into NAND Flash bank common space address area. Write ADD2 into NAND Flash bank common space address area. Write ADD3 into NAND Flash bank common space address area. Write CMD1 into NAND Flash bank attribute space command area.
Page 590 GD32F403xx User Manual Attribute space: EXMC_NCE3_x (x = 0, 1) is the chip enable signal, it indicates whether 8- or 16-bit access operation is being performed. EXMC_NWE and EXMC_NOE dictates whether the on-going operation is a write or read operation, and EXMC_NREG is low during attribute space access.
Page 591 GD32F403xx User Manual Registers definition 21.4. NOR/PSRAM controller registers 21.4.1. SRAM/NOR Flash control registers (EXMC_SNCTLx) (x=0, 1, 2, 3) Address offset: 0x00 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0000 30DB for region0, and 0x0000 30D2 for region1, region2, and region3. This register has to be accessed by word (32-bit) SYNC CPS[2:0]...
Page 592 GD32F403xx User Manual 0: Disable NWAI signal 1: Enable NWAIT signal WREN Write enable 0: Disabled write in the bank by the EXMC, otherwise an AHB error is reported 1: Enabled write in the bank by the EXMC (default after reset) NRWTCFG NWAIT signal configuration, only work in synchronous mode 0: NWAIT signal is active one data cycle before wait state...
Page 593 GD32F403xx User Manual Address offset: 0x04 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0FFF FFFF This register has to be accessed by word(32-bit) Reserved ASYNCMOD[1:0] DLAT[3:0] CKDIV[3:0] BUSLAT[3:0] DSET[7:0] AHLD[3:0] ASET[3:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value.
Page 594 GD32F403xx User Manual 0x00: Reserved 0x01: Data setup time = 2 * HCLK period …… 0xFF: Data setup time = 256 * HCLK period AHLD[3:0] Address hold time This field is used to set the time of address hold phase, which only used in mode D and multiplexed mode.
Page 595 GD32F403xx User Manual 11: Mode D access 27:20 Reserved Must be kept at reset value. 19:16 WBUSLAT[3:0] Bus latency Bus latency added at the end of each write transaction to match with the minimum time between consecutive transactions. 0x0: Bus latency = 1 * HCLK period 0x1: Bus latency = 2 * HCLK period ……...
Page 596 GD32F403xx User Manual ATR[2:0] CTR[3:0] Reserved ECCEN NDW[1:0] NDTP NDBKEN NDWTEN Reserved Bits Fields Description 31:20 Reserved Must be kept at reset value. 19:17 ECCSZ[2:0] ECC size 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes 16:13 ATR[3:0]...
Page 597 GD32F403xx User Manual 1: Enable wait function Reserved Must be kept at reset value. NAND Flash/PC Card interrupt enable registers (EXMC_NPINTENx) (x=1, 2, 3) Address offset: 0x44 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0x0000 0042 (for bank1 and bank2), 0x0000 0043 (for bank3) This register has to be accessed by word (32-bit) In addition to interrupt controlling bits, this register also contains a FIFO empty status bit, design specifically f or ECC purpose.
Page 598 GD32F403xx User Manual 0: Not detect interrupt high -level 1: Detect interrupt high -level INTRS Interrupt rising edge status 0: Not detect interrupt rising edge 1: Detect interrupt rising edge NAND Flash/PC Card common space timing configuration registers (EXMC_NPCTCFGx) (x=1, 2, 3) Address offset: 0x48 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0xFCFC FCFC This register has to be accessed by word(32-bit)
Page 599 GD32F403xx User Manual 0x01: COMWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFE: COMWAIT = 255 * HCLK (+NWAIT active cycles) 0xFF: Reserved COMSET[7:0] Common memory setup time Define the time to build address before sending command 0x00: COMSET = 1 * HCLK ……...
Page 600 GD32F403xx User Manual 0xFF: Reserved 15:8 ATTWAIT[7:0] Attribute memory wait time Define the minimum time to maintain command 0x00: Reserved 0x01: ATTWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFE: ATTWAIT = 255 * HCLK (+NWAIT active cycles) 0xFF: ATTWAIT = Reserved ATTSET[7:0] Attribute memory setup time Define the time to build address before sending command...
Page 601 GD32F403xx User Manual 15:8 IOWAIT[7:0] IO space wait time Define the minimum time to maintain command 0x00: Reserved 0x01: IOWAIT = 2 * HCLK (+NWAIT active cycles) …… 0xFF: IOWAIT = 256 * HCLK (+NWAIT active cycles) IOSET[7:0] IO space setup time Define the time to build address before sending command 0x00: IOSET = 1 * HCLK ……...
Page 602 GD32F403xx User Manual Controller area network (CAN) 22.1. Overview CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. As CAN network interface, basic extended CAN supports the CAN protocols version 2.0A and B.
Page 603: Figure 22-1. Can Module Block Diagram
GD32F403xx User Manual Function overview 22.3. Figure 22-1. CAN module block diagram shows the CAN block diagram. Figure 22-1. CAN module block diagram Working mode 22.3.1. The CAN interface has three working modes: ◼ Sleep working mode. ◼ Initial working mode. ◼...
Page 604 GD32F403xx User Manual Initial working mode When the conf iguration of CAN bus communication is needed to be changed, the CAN must enter initial working mode. When IWMOD bit in CAN_CTL register is set, the CAN enters the initial working mode. Then the IWS bit in CAN_STAT register is set.
Page 605: Figure 22-2. Transmission Register
GD32F403xx User Manual FIFOs, the RX pin is disconnected f rom the CAN network and the TX pin can still send messages to the CAN network. Setting LCMOD bit in CAN_BT register to enter loopback communication mode, while clearing it to leave. Loopback communication mode is useful for self-test. Loopback and silent communication mode Loopback and silent communication mode means the RX and TX pins are disconnected from the CAN network while the transmitted messages are transferred into the Rx FIFOs.
Page 606: Figure 22-3. State Of Transmit Mailbox
GD32F403xx User Manual Transmit mailbox state A transmit mailbox can be used when it is free (empty state). If the mailbox is filled with data, set TEN bit in CAN_TMIx register to prepare for starting the transmission (pending state). If more than one mailbox is in the pending state, they need scheduling the transmission (scheduled state).
Page 607: Figure 22-4. Reception Register
GD32F403xx User Manual done immediately. In the transmit state, the abort of transmission does not take effect immediately until the transmission is finished. In case that the transmission is successful, the MTFNERR and MTF in CAN_TSTAT are set and state changes to be empty. In case that the transmission is failed, the state changes to be scheduled and then the abort of transmission can be done immediately.
Page 608 GD32F403xx User Manual Rx FIFO Rx FIFO has three mailboxes. The reception f rames are stored in the mailbox according to the arriving sequence. First arrived frame can be accessed by application firstly. The number of f rames in the Rx FIFO and the status can be accessed by the register CAN_RFIFO0 and CAN_RFIFO1.
Page 609: Figure 22-5. 32-Bit Filter
GD32F403xx User Manual Figure 22-5. 32-bit filter Figure 22-6. 16-bit filter. 16-bit: SFID [10:0], FT, FF and EFID[17:15] bits. As is shown in Figure 22-6. 16-bit filter FDATA[31:21] FDATA[20:16] FDATA[15:5] FDATA[4:0] SFID[10:0] FT FF EFID[17:15] SFID[10:0] FT FF EFID[17:15] Mask mode For the Identif ier of a data f rame to be filtered, the mask mode is used to specify which bits must be the same as the preset Identif ier and which bits need not be judged.
Page 610: Table 22-1. 32-Bit Filter Number
GD32F403xx User Manual Filter number Filter consists of some f ilter bank. According to the mode and the scale of each of the f ilter banks, filter has different effects. For example, there are two f ilter banks. Bank0 is configured as 32-bit mask mode. Bank1 is Table 22-1.
Page 611: Table 22-2. Filtering Index
GD32F403xx User Manual Table 22-2. Filtering index Filter Filter Filter Filter FIFO0 Active FIFO1 Active bank nunber bank nunber F0DATA0-32bits-ID F2DATA0[15:0]-16bits-ID F2DATA0[31:16]-16bits- F0DATA1-32bits-Mask Mask F1DATA0-32bits-ID F2DATA1[15:0]-16bits-ID F2DATA1[31:16]-16bits- F1DATA1-32bits-ID Mask F3DATA0[15:0]-16bits-ID F4DATA0-32bits-ID F3DATA0[31:16]-16bits- F4DATA1-32bits-Mask Mask F3DATA1[15:0]-16bits-ID F5DATA0-32bits-ID F3DATA1[31:16]-16bits- F5DATA1-32bits-ID Mask F7DATA0[15:0]-16bits-ID F6DATA0[15:0]-16bits-ID F7DATA0[31:16]-16bits- F6DATA0[31:16]-16bits- ID...
Page 612 GD32F403xx User Manual Time-triggered communication 22.3.6. The time-triggered CAN protocol is a higher layer protocol on top of the CAN data link layer. Time-triggered communication means that activities are triggered by the elapsing of time segments. In a time-triggered communication system, all time points of message transmission are pre-defined.
Page 613: Figure 22-11. The Bit Time
GD32F403xx User Manual delay segment and Phase buf fer segment 1 in the CAN standard. Its duration is programmable f rom 1 to 16 time quanta but it may be automatically leng thened to compensate f or positive phase drifts due to different f requency of the various nodes of the network.
Page 614 GD32F403xx User Manual Error flags 22.3.8. The state of CAN bus can be ref lected by Transmit Error Counter (TECNT) and Receive Error Counter (RECNT) of CAN_ERR register. The value can be increased or decreased by the hardware according to the error, and the software can judge the stability of the CAN network by these values.
Page 615 GD32F403xx User Manual Receive FIFO0 interrupt The Rx FIFO0 interrupt can be generated by the following conditions: ◼ Rx FIFO0 not empty: RFL0 bits in the CAN_RFIFO0 register are not ‘00’ and RFNEIE0 in CAN_INTEN register is set. ◼ Rx FIFO0 full: RFF0 bit in the CAN_RFIFO0 register is set and RFFIE0 in CAN_INTEN register is set.
Page 616 GD32F403xx User Manual 22.4. CAN registers CAN0 base address: 0x4000 6400 CAN1 base address: 0x4000 6800 Control register (CAN_CTL) 22.4.1. Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit) Reserved SLPWMO SWRST Reserved ABOR RFOD IWMOD Bits...
Page 617 GD32F403xx User Manual If this bit is set, the CAN leaves sleep working mode when CAN bus activity is detected, and SLPWMOD bit in CAN_CTL register will be cleared automatically. 0: The sleeping working mode is left manually by software 1: The sleeping working mode is left automatically by hardware Automatic retransmission disable 0: Enable automatic retransmission...
Page 618 GD32F403xx User Manual RX level LASTRX Last sample value of RX pin Receiving state 0: CAN is not working in the receiving state 1: CAN is working in the receiving state Transmitting state 0: CAN is not working in the transmitting state 1: CAN is working in the transmitting state Reserved Must be kept at reset value.
Page 619 GD32F403xx User Manual 1: CAN is in the state of sleep working mode Initial working state This bit is set by hardware when the CAN enters initial working mode after setting IWMOD bit in CAN_CTL register. If the CAN leaves normal working mode to initial working mode, it must wait the current frame transmission or reception to be completed.
Page 620 GD32F403xx User Manual TME1 Transmit mailbox 1 empty 0: Transmit mailbox 1 not empty 1: Transmit mailbox 1 empty TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24 NUM[1:0] These bits are the number of the Tx FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.
Page 621 GD32F403xx User Manual This bit is set by hardware when the transmit error occurs. This bit is reset by writting 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit is reset by hardware when next transmit starts. MAL1 Mailbox 1 arbitration lost This bit is set when the arbitration lost occurs.
Page 622 GD32F403xx User Manual 0: Mailbox 0 transmit is progressing 1: Mailbox 0 transmit finished Receive message FIFO0 register (CAN_RFIFO0) 22.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RFD0 RFO0 RFF0 Reserved RFL0[1:0] rc_w1...
Page 623 GD32F403xx User Manual This register has to be accessed by word(32-bit) Reserved Reserved RFD1 RFO1 RFF1 Reserved RFL1[1:0] rc_w1 rc_w1 Bits Fields Descriptions Must be kept at reset value. 31:6 Reserved Rx FIFO1 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO1. RFD1 This bit is reset by hardware when the dequeuing is done.
Page 624 GD32F403xx User Manual Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. SLPWIE Sleep working interrupt enable 0: Sleep working interrupt disabled 1: Sleep working interrupt enabled Wakeup interrupt enable 0: Wakeup interrupt disabled 1: Wakeup interrupt enabled ERRIE Error interrupt enable 0: Error interrupt disabled...
Page 625 GD32F403xx User Manual RFFIE0 Rx FIFO0 full interrupt enable 0: Rx FIFO0 full interrupt disabled 1: Rx FIFO0 full interrupt enabled RFNEIE0 Rx FIFO0 not empty interrupt enable 0: Rx FIFO0 not empty interrupt disabled 1: Rx FIFO0 not empty interrupt enabled TMEIE Transmit mailbox empty interrup t enable 0: Transmit mailbox empty interrupt disabled...
Page 626 GD32F403xx User Manual BOERR Bus-Off error Whenever the CAN enters Bus-Off state, the bit will be set by hardware. PERR Passive error Whenever the TECNT or RECNT is greater than 127, the bit will be set by hardware. WERR Warning error Whenever the TECNT or RECNT is greater than or equal to 96, the bit will be set by hardware.
Page 627 GD32F403xx User Manual BAUDPSC[9:0] Baud rate prescaler The CAN baud rate prescaler Transmit mailbox identifier register (CAN_TMIx) (x=0..2) 22.4.9. Address offset: 0x180, 0x190, 0x1A0 Reset value: 0xXXXX XXXX (bit0=0) This register has to be accessed by word(32-bit) SFID[10:0]/EFID[28:18] EFID[17:13] EFID[12:0] Bits Fields Descriptions...
Page 628 GD32F403xx User Manual Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) TS[15:0] Reserved TSEN Reserved DLENC[3:0] Bits Fields Descriptions 31:16 TS[15:0] Time stamp The time stamp of frame in transmit mailbox. 15:9 Reserved Must be kept at reset value. TSEN Time stamp enable 0: Time stamp disabled...
Page 629 GD32F403xx User Manual 23:16 DB2[7:0] Data byte 2 15:8 DB1[7:0] Data byte 1 DB0[7:0] Data byte 0 Transmit mailbox data1 register (CAN_TMDATA1x) (x=0..2) 22.4.12. Address offset: 0x18C, 0x19C, 0x1AC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) DB7[7:0] DB6[7:0] DB5[7:0]...
Page 630 GD32F403xx User Manual EFID[28:18]: Extended format frame identifier 20:16 EFID[17:13] The frame identifier EFID[17:13]: Extended format frame identifier 15:3 EFID[12:0] The frame identifier EFID[12:0]: Extended format frame identifier Frame format 0: Standard format frame 1: Extended format frame Frame type 0: Data frame 1: Remote frame Reserved...
Page 631 GD32F403xx User Manual Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) DB3[7:0] DB2[7:0] DB1[7:0] DB0[7:0] Bits Fields Descriptions 31:24 DB3[7:0] Data byte 3 23:16 DB2[7:0] Data byte 2 15:8 DB1[7:0] Data byte 1 DB0[7:0] Data byte 0 Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) 22.4.16.
Page 632 GD32F403xx User Manual This register has to be accessed by word(32-bit) Reserved Reserved HBC1F[5:0] Reserved Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:8 HBC1F[5:0] Header bank of CAN1 filter These bits are set and cleared by software to define the first bank for CAN1 filter. Bank0 ~ Bank HBC1F-1 is used for CAN0.
Page 633 GD32F403xx User Manual Filter scale configuration register (CAN_FSCFG) (Just for CAN0) 22.4.19. Address offset: 0x20C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). This register can be modified only when FLD bit in CAN_FCTL register is set. Reserved FS27 FS26...
Page 634 GD32F403xx User Manual Filter working register (CAN_FW) (Just for CAN0) 22.4.21. Address offset: 0x21C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved FW27 FW26 FW25 FW24 FW23 FW22 FW21 FW20 FW19 FW18 FW17 FW16 FW15 FW14 FW13 FW12...
Page 635 GD32F403xx User Manual Universal serial bus full-speed interface (USBFS) 23.1. Overview USB Full-Speed (USBFS) controller provides a USB-connection solution f or portable devices. USBFS supports host and device modes, as well as OTG mode with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol). USBFS contains a f ull-speed internal USB PHY and external PHY chip is not contained.
Page 636: Figure 23-1. Usbfs Block Diagram
GD32F403xx User Manual 23.3. Block diagram Figure 23-1. USBFS block diagram interrupts AHB Slave Register Device bus Host Port control Control Data FIFO Transcation UTMI USB FS PHY Scheduler Control VBUS USB Clock USB Clock Domain 48MHz 23.4. Signal description Table 23-1.
Page 637: Figure 23-2. Connection With Host Or Device Mode
GD32F403xx User Manual Figure 23-2. Connection with host or device mode 5V Power Supply GPIO (needed in host mode) VBUS VBUS When USBFS works in host mode (FHM bit is set and FDM bit is cleared), t he VBUS is 5V power, and detecting pin which is using for voltage detection is defined in USB protocol.
Page 638: Figure 23-3. Connection With Otg Mode
GD32F403xx User Manual Figure 23-3. Connection with OTG mode 5V Power GPIO Supply VBUS VBUS USB host function 23.5.2. USB Host Port State Host application may control state of the USB port via USBFS_HPCS register. After system initialization, the USB port stays at power-off state. After PP bit is set by software, the internal USB PHY is powered on, and the USB port changes into disconnected state.
Page 639 GD32F403xx User Manual PRST bit is used f or USB reset sequence. Application may set this bit to start a USB reset and clear this bit to finish the USB reset. This bit only takes effect when port is at connected or enabled state.
Page 640 GD32F403xx User Manual USB transaction request or a channel operation request. Application needs to write packet into data FIFO via AHB register interface if it wants to start an OUT transaction on USB bus. USBFS hardware will automatically generate a transaction request entry in request queue after the application wro te a whole packet.
Page 641 GD32F403xx User Manual a resume signal on USB bus. When USBFS detects the resume signal, the WKUPIF flag in USBFS_GINTF register will be set and the USBFS wake up interrupt will be triggered. In suspend mode, USBFS is also able to remotely wake up the USB bus. Software may set RWKUP bit in USBFS_DCTL register to send a remote wake-up signal, and if remote wake- up is supported in USB host, the host will begin to send resume signal on USB bus.
Page 642 GD32F403xx User Manual Micro-B plug for device) is inserted. By utilizing the Host Negotiation Protocol (HNP), an On- The-Go B-Device, which is the default device, may make a request to be a host. The process f or changing the role to be a host is described in this section. This protocol eliminates the necessity of switching the cable connection for the roles change of the connected devices.
Page 643: Figure 23-5. Host Mode Fifo Space In Sram
GD32F403xx User Manual Figure 23-5. HOST mode FIFO space in SRAM USBFS provides a special register area f or the internal data FIFO reading and writing. Figure 23-6. Host mode FIFO access register map describes the register memory area that the data FIFO can access.
Page 644: Figure 23-7. Device Mode Fifo Space In Sram
GD32F403xx User Manual Figure 23-7. Device mode FIFO space in SRAM Start: 0x00 Rx FIFO RXFD IEPTX0RSAR[15:0] Tx FIFO0 IEPTX0FD IEPTX1RSAR[15:0] IEPTX1FD Tx FIFO1 IEPTX3RSAR[15:0] IEPTX3FD Tx FIFO3 End: 0x13F USBFS provides a special register area for the internal data FIFO reading and writing. Figure 23-8.
Page 645 GD32F403xx User Manual Host mode Global register initialization sequence 1. Program USBFS_GAHBCS register according to application’s demand, such as the TxFIFO’s empty threshold, etc. GINTEN bit should be kept cleared at this time. 2. Program USBFS_GUSBCS register according to application’s demand, such as the operation mode (host, device or OTG) and some parameters of OTG and USB protocols.
Page 646 GD32F403xx User Manual Sof tware can disable the channel by setting both CEN and CDIS bits at the same time. USBFS will generate a channel disable request entry in request queue af ter the register setting operation. When the request entry reaches the top of request queue, it will be processed by USBFS immediately: For OUT channels, the specified channel will be disabled immediately.
Page 647 GD32F403xx User Manual 4. When the request entry reaches the top of the request queue, USBFS begins to process this request entry. If bus time for the transaction indicated by the request entry is enough, USBFS starts the OUT transaction on USB bus. 5.
Page 648 GD32F403xx User Manual enable bits. 3. Program USBFS_DIEPxLEN or USBFS_DOEPxLEN register. PCNT is the number of packets in a transfer and TLEN is the total byte number of all the transmitted or received packets in a transfer. For IN endpoint：If PCNT=1, the single packet’s size is equal to TLEN. If PCNT>1, the f ormer PCNT-1 packets are considered as max-packet-length packets whose size are def ined by MPL f ield in USBFS_DIEPxCTL register, and the last p acket’s size is calculated based on PCNT, TLEN and MPL.
Page 649: Table 23-2. Usbfs Global Interrupt
GD32F403xx User Manual FIFO successfully and sends ACK handshake on USB bus), PCNT in USBFS_DOEPxLEN register is decreased by 1 and the ACK flag is triggered, otherwise, the status flags report the transaction result. 4. After all the data packets in a transfer are successfully received on USB bus, USBFS pushes a TF status entry into the Rx FIFO on top of the last packet data.
Page 650 GD32F403xx User Manual Interrupt Flag Description Operation Mode OTGIF OTG interrupt flag Host or device mode MFIF Mode fault interrupt flag Host or device mode Wake-up interrupt can be triggered when USBFS is in suspend state, even if when the USBFS’s clocks are stopped.
Page 651 GD32F403xx User Manual 23.7. Register definition USBFS base address: 0x5000 0000 Global control and status registers 23.7.1. Global OTG control and status register (USBFS_GOTGCS) Address offset: 0x0000 Reset value: 0x0000 0800 This register has to be accessed by word (32-bit) Bits Fields Descriptions...
Page 652 GD32F403xx User Manual protocol. Note: Only accessible in host mode. IDPS ID pin status Voltage level of connector ID pin 0: USBFS is in A-Device mode 1: USBFS is in B-Device mode Note: Accessible in both device and host modes. 15:12 Reserved Must be kept at reset value.
Page 653 GD32F403xx User Manual Note: Only accessible in device mode. SRPS SRP success This bit is set by the core when SRP succeeds, and this bit is cleared when SRPREQ bit is set. 0: SRP fails 1: SRP succeeds Note: Only accessible in device mode. Global OTG interrupt flag register (USBFS_GOTGINTF) Address offset: 0x0004 Reset value: 0x0000 0000...
Page 654 GD32F403xx User Manual Set by the core when a HNP ends. Read the HNPS in USBFS_GOTGCS register to get the result of HNP. Note: Accessible in both device and host modes. SRPEND SRPEND Set by the core when a SRP ends. Read the SRPS in USBFS_GOTGCS register to get the result of SRP.
Page 655 GD32F403xx User Manual empty Host mode: 0: NPTXFEIF will be triggered when the non-periodic transmit FIFO is half empty 1: NPTXFEIF will be triggered when the non-periodic transmit FIFO is completely empty 6：1 Reserved Must be kept at reset value. GINTEN Global interrupt enable 0: Global interrupt is not enabled .
Page 656 GD32F403xx User Manual pin. 0: Normal mode 1: Host mode The application must wait at least 25 ms for the change taking effect after setting the force bit. Note: Accessible in both device and host modes. 28:14 Reserved Must be kept at reset value. 13:10 UTT[3:0] USB turnaround time...
Page 657 GD32F403xx User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. 10:6 TXFNUM[4:0] Tx FIFO number Indicates which Tx FIFO will be flushed when TXFF bit in the same register is set. Host Mode: 00000: Only non -periodic Tx FIFO is flushed 00001: Only periodic Tx FIFO is flushed 1XXXX: Both periodic and non-periodic Tx FIFOs are flushed Other: Non data FIFO is flushed...
Page 658 GD32F403xx User Manual Set by the application to reset AHB clock domain circuit. Hardware automatically clears this bit after the reset process completes. After setting this bit, application should wait until this bit is cleared before any other operation on USBFS. Note: Accessible in both device and host modes.
Page 659 GD32F403xx User Manual Reserved Must be kept at reset value. PTXFEIF Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the periodic transmit FIFO is either half or completely empty. The threshold is determined by the periodic Tx FIFO emp ty level bit (PTXFTH) in the USBFS_GAHBCS regis ter.
Page 660 GD32F403xx User Manual IEPIF IN endpoint interrupt flag Set by USBFS when one of the IN endpoints in device mode has raised an interrupt. Software should first read USBFS_DAEPINT register to get the device number, and then read the corresponding USBFS_DIEPxINTF register to get the flags of the endpoint that cause the interrupt.
Page 661 GD32F403xx User Manual Note: Only accessible in device mode. NPTXFEIF Non-Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the non-periodic transmit FIFO is either half or completely empty. The threshold is determined by the non-periodic Tx FIFO empty level bit (TXFTH) in the USBFS_GAHBCS register.
Page 662 GD32F403xx User Manual This register has to be accessed by word (32-bit) Bits Fields Descriptions WKUPIE Wakeup interrupt enable 0: Disable wakeup interrupt 1: Enable wakeup interrupt Note: Accessible in both host and device modes. SESIE Session interrupt enable 0: Disable session interrupt 1: Enable session interrupt Note: Accessible in both host and device modes.
Page 663 GD32F403xx User Manual HPIE Host port interrupt enable 0: Disable host port interrupt 1: Enable host port interrupt Note: Only accessible in host mode. 23:22 Reserved Must be kept at reset value. PXNCIE Periodic transfer not complete Interrupt enable 0: Disable periodic transfer not complete interrupt 1: Enable periodic transfer not complete interrupt Note: Only accessible in host mode.
Page 664 GD32F403xx User Manual RSTIE USB reset interrupt enable 0: Disable USB reset interrupt 1: Enable USB reset interrupt Note: Only accessible in device mode. SPIE USB suspend interrupt enable 0: Disable USB suspend interrupt 1: Enable USB suspend interrupt Note: Only accessible in device mode. ESPIE Early suspend interrupt enable 0: Disable early suspend interrupt...
Page 665 GD32F403xx User Manual 1: Enable mode fault interrupt Note: Accessible in both device and host modes. Reserved Must be kept at reset value. Global receive status read/receive status read and pop registers (USBFS_GRSTATR/USBFS_GRSTATP) Address offset for Read: 0x001C Address offset for Pop: 0x0020 Reset value: 0x0000 0000 A read to the receive status read register returns the entry of the top of the Rx FIFO.
Page 666 GD32F403xx User Manual 10: DATA1 Others: Reserved 14:4 BCOUNT[10:0] Byte count The byte count of the received IN data packet. CNUM[3:0] Channel number The channel number to which the current received packet belongs. Device mode: Bits Fields Descriptions 31:21 Reserved Must be kept at reset value.
Page 667 GD32F403xx User Manual Global receive FIFO length register (USBFS_GRFLEN) Address offset: 0x024 Reset value: 0x0000 0200 This register has to be accessed by word (32-bit) r/rw Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 RXFD[15:0] Rx FIFO depth In terms of 32-bit words.
Page 668 GD32F403xx User Manual Bits Fields Descriptions 31:16 HNPTXFD[15:0] Host Non-periodic Tx FIFO depth In terms of 32-bit words. 1≤HNPTXFD≤1024 15:0 HNPTXRSAR[15:0] Host Non-periodic Tx RAM start address The start address for non-periodic transmit FIFO RAM is in term of 32-bit words. Device Mode: Bits Fields...
Page 669 GD32F403xx User Manual Bits 30:27: Channel number Bits 26:25: – 00: IN/OUT token – 01: Zero-length OUT packet – 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected ch annel. 23:16 NPTXRQS[7:0] Non-periodic Tx request queue space The remaining space of the non-periodic transmit request queue.
Page 670 GD32F403xx User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. VBUSIG ignored When this bit is set, USBFS doesn’t monitor the voltage on VBUS pin and always consider V voltage as valid both in host mode and in device mode, then free the V pin for other usage.
Page 671 GD32F403xx User Manual Bits Fields Descriptions 31:0 Core ID Software can write or read this field and uses this field as a unique ID for its application Host periodic transmit FIFO length register (USBFS_HPTFLEN) Address offset: 0x0100 Reset value: 0x0200 0600 This register has to be accessed by word 32-bit) r/rw r/rw...
Page 672 GD32F403xx User Manual r/rw r/rw Bits Fields Descriptions 31:16 IEPTXFD[15:0] IN endpoint Tx FIFO depth In terms of 32-bit words. 1≤HPTXFD≤1024 15:0 IEPTXRSAR[15:0] IN endpoint FIFO Tx RAM start address The start address for IN endpoint transmit FIFOx is in term of 32-bit words. Host control and status registers 23.7.2.
Page 673 GD32F403xx User Manual 31:2 Reserved Must be kept at reset value. CLKSEL Clock select for usbclock. 01: 48MHz clock others: reserved Host frame interval register (USBFS_HFT) Address offset: 0x0404 Reset value: 0x0000 BB80 This register sets the f rame interval for the current enumerating speed when USBFS controller is enumerating.
Page 674 GD32F403xx User Manual Bits Fields Descriptions 31:16 FRT[15:0] Frame remaining time This field reports the remaining time of current frame in terms of PHY clocks . 15:0 FRNUM[15:0] Frame number This field reports the frame number of current frame and returns to 0 after it reaches 0x3FFF.
Page 675 GD32F403xx User Manual Bits 26:25: 00: IN/OUT token 01: Zero-length OUT packet 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel. 23:16 PTXREQS[7:0] Periodic Tx request queue space The remaining space of the periodic transmit request queue. 0: Request queue is Full 1: 1 entry 2 entries...
Page 676 GD32F403xx User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. HACHINT[7:0] Host all channel interrupts Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7. Host all channels interrupt enable register (USBFS_HACHINTEN) Address offset: 0x0418 Reset value: 0x0000 0000 This register can be used by sof tware to enable or disable a channel’s interrupt.
Page 677 GD32F403xx User Manual This register has to be accessed by word (32-bit) rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:19 Reserved Must be kept at reset value. 18:17 Port speed Report the enumerated speed of the device attached to this port. 01: Full speed 10: Low speed Others: Reserved...
Page 678 GD32F403xx User Manual stops sending SOF tokens. This bit can only be cleared by the following operations: – PRST bit in this register is set by application – PREM bit in this register is set – A remote wakeup signal is detected –...
Page 679 GD32F403xx User Manual EPTYPE[1:0] Bits Fields Descriptions Channel enable Set by the application and cleared by USBFS. 0: Channel disabled 1: Channel enabled Software should following the operation guide to disable or enable a channel. CDIS Channel disable Software can set this bit to disable the channel from processing transactions . Software should follow the operation guide to disable or enable a channel.
Page 680 GD32F403xx User Manual The transfer direction of the endpoint that this channel wants to communicate with. 0: OUT 1: IN 14:11 EPNUM Endpoint number The number of the endpoint that this channel wants to communicate with. 10:0 Maximum packet length The target endpoint’s maximum packet length.
Page 681 GD32F403xx User Manual maximum packet length. USBER USB Bus Error The USB error flag is set when the following conditions occurs during receiving a packet: – A received packet has a wrong CRC field – A stuff error detected on USB bus –...
Page 682 GD32F403xx User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value DTERIE Data toggle error interrupt enable 0: Disable data toggle error interrupt 1: Enable data toggle error interrupt REQOVRIE Request queue overrun interrupt enable 0: Disable request queue overrun interrupt 1: Enable request queue overrun interrupt BBERIE Babble error interrupt enable...
Page 683 GD32F403xx User Manual 1: Enable transfer finished interrupt Host channel-x transfer length register (USBFS_HCHxLEN) (x = 0..7, where x = channel number) Address offset: 0x0510 + (channel_number × 0x20) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions...
Page 684 GD32F403xx User Manual to be transmitted in an OUT transfer. Software should program this field before the channel is enabled. When software successfully writes a packet into the channel’s data TxFIFO, this field is decreased by the byte size of the packet. For IN transfer each time software or DMA reads out a pack et from the RxFIFO, this field is decreased by the byte size of the packet.
Page 685 GD32F403xx User Manual Reserved Must be kept at reset value. NZLSOH Non-zero-length status OUT handshake When a USB device receives a non -zero-length data packet during status OUT stage, this field controls that either USBFS should receive this packet or reject this packet with a STALL handshake.
Page 686 GD32F403xx User Manual USBFS_GINTF register triggered after a while. Software should clear the GONAK flag before writing this bit again. CGINAK Clear global IN NAK Software sets this bit to clear GINS bit in this register. SGINAK Set global IN NAK Software sets this bit to set GINS bit in this register.
Page 687 GD32F403xx User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. 21:8 FNRSOF[13:0] The frame number of the received SOF. USBFS always update this field after receiving a SOF token Reserved Must be kept at reset value. ES[1:0] Enumerated speed This field reports the enumerated device speed.
Page 688 GD32F403xx User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. IEPNEEN IN endpoint NAK effective interrupt enable bit 0: Disable IN endpoint NAK effective interrupt 1: Enable IN endpoint NAK effective interrupt Reserved Must be kept at reset value EPTXFUDEN Endpoint Tx FIFO underrun interrupt enable bit 0: Disable endpoint Tx FIFO underrun interrupt...
Page 689 GD32F403xx User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. BTBSTPEN Back-to-back SETUP packets (Only for control OUT endpoint) interrupt enable bit 0: Disable back-to-back SETUP packets interrupt 1: Enable back-to-back SETUP packets interrupt Reserved Must be kept at reset value. EPRXFOVREN Endpoint Rx FIFO overrun interrupt enable bit 0: Disable endpoint Rx FIFO overrun interrupt...
Page 690 GD32F403xx User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 19:16 OEPITB[3:0] Device all OUT endpoint interrupt bits Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. 15:4 Reserved Must be kept at reset value.
Page 691 GD32F403xx User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 19:16 OEPIE[3:0] Out endpoint interrupt enable 0: Disable OUT endpoint-n interrupt 1: Enable OUT endpoint-n interrupt Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3. 15:4 Reserved Must be kept at reset value.
Page 692 GD32F403xx User Manual Device VBUS pulsing time register (USBFS_DVBUSPT) Address offset: 0x082C Reset value: 0x0000 05B8 This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DVBUSPT[11:0] Device V pulsing time This field defines the pulsing time for V The true pulsing time is...
Page 693 GD32F403xx User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. IEPTXFEIE[3:0] IN endpoint Tx FIFO empty interrupt enable bits This field controls whether the TXFE bits in USBFS_DIEPxINTF registers are able to generate an endpoint interrupt bit in USBFS_DAEPINT register. Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3 0: Disable FIFO empty interrupt 1: Enable FIFO empty interrupt...
Page 694 GD32F403xx User Manual 29:28 Reserved Must be kept at reset value. SNAK Set NAK Software sets this bit to set NAKS bit in this register. CNAK Clear NAK Software sets this bit to clear NAKS bit in this register. 25:22 TXFNUM[3:0] Tx FIFO number Defines the Tx FIFO number of IN endpoint 0.
Page 695 GD32F403xx User Manual Device IN endpoint-x control register (USBFS_DIEPxCTL) (x = 1..3, where x = endpoint_number) Address offset: 0x0900 + (endpoint_number × 0x20) Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) rw/rs Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS.
Page 696 GD32F403xx User Manual Software sets this bit to clear NAKS bit in this register. 25:22 TXFNUM[3:0] Tx FIFO number Defines the Tx FIFO number of this IN endpoint. STALL STALL handshake Software can set this bit to make USBFS sends STALL handshake when receiving IN token.
Page 697 GD32F403xx User Manual 1: Data packet’s PID is DATA1 EPACT Endpoint active This bit controls whether this endpoint is active. If an endpoint is not active, it ignores all tokens and doesn’t make any response. 14:11 Reserved Must be kept at reset value. 10:0 MPL[10:0] This field defines the maximum packet length in bytes.
Page 698 GD32F403xx User Manual STALL STALL handshake Set this bit to make USBFS send STALL handshake during an OUT transaction. USBFS will clear this bit after a SETUP token is received on OUT endpoint 0. This bit has a higher priority than NAKS bit in this register, i.e. if both STALL and NAKS bits are set, the STALL bit takes effect.
Page 699 GD32F403xx User Manual This register has to be accessed by word (32-bit) rw/rs Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint.
Page 700 GD32F403xx User Manual transaction. This bit has a higher priority than NAKS bit in this register and GINAK in USBFS_DCTL register. If both STALL and NAKS bits are set, the STALL bit takes effect. For control OUT endpoint: Only USBFS can clear this bit when a SETUP token is received on the corresponding OUT endpoint.
Page 701 GD32F403xx User Manual ignores all tokens and doesn’t make any response. 14:11 Reserved Must be kept at reset value. 10:0 MPL[10:0] This field defines the maximum packet length in bytes. Device IN endpoint-x interrupt flag register (USBFS_DIEPxINTF) (x = 0..3, where x = endpoint_number) Address offset: 0x0908 + (endpoint_number ×...
Page 702 GD32F403xx User Manual incoming CITO Control IN Timeout interrupt This flag is triggered if the device waiting for a handshake is timeout in a control IN transaction. Reserved Must be kept at reset value. EPDIS Endpoint disabled This flag is triggered when an endpoint is disabled by the software’s request. Transfer finished This flag is triggered when all the IN transactions assigned to this endpoint have been finished.
Page 703 GD32F403xx User Manual This flag is triggered if the OUT endpoint’s Rx FIFO has no enough space for a packet data when an OUT token is incoming. USBFS will drop the incoming OUT data packet and sends a NAK handshake in this case. STPF SETUP phase finished (Only for control OUT endpoint) This flag is triggered when a setup phase finished, i.e.
Page 704 GD32F403xx User Manual The total data byte number of a transfer. This field is the total data bytes of all the data packets desired to be transmitted in an IN transfer. Program this field before the endpoint is enabled. When software successfully writes a packet into the endpoint’s Tx FIFO, this field is decreased by the byte size of the packet.
Page 705 GD32F403xx User Manual on bus. 18:7 Reserved Must be kept at reset value. TLEN[6:0] Transfer length The total data byte number of a transfer. This field is the total data bytes of all the data packets desired to receive in an OUT transfer.
Page 706 GD32F403xx User Manual transmission. 18:0 TLEN[18:0] Transfer length The total data byte number of a transfer. This field is the total data bytes of all the data packets desired to be transmitted in an IN transfer. Program this field before the endpoint is enabled. When software successfully writes a packet into the endpoint’s Tx FIFO, this field is decreased by the byte size of the packet.
Page 707 GD32F403xx User Manual 10: 2 packets 11: 3 packets 28:19 PCNT[9:0] Packet count The number of data packets desired to receive in a transfer . Program this field before the endpoint is enabled. After the transfer starts, this field is decreased automatically by USBFS after each successful data packet reception on bus.
Page 708 GD32F403xx User Manual … n: n words available Power and clock control register (USBFS_PWRCLKCTL) 23.7.4. Address offset: 0x0E00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SHCLK Stop HCLK Stop the HCLK to save power.
Page 709: Table 24-1. Revision History
GD32F403xx User Manual Revision history Table 24-1. Revision history Revision No. Description Date Initial Release Feb.10, 2017 Revise ADC/DAC/DMA/RCU/USART Oct. 17, 2017 Adapt To New Document Specification Dec.14, 2018 In ADC chapter 12.7.3, ADC_CTL1 register modified In PMU chapter 3.3, update block diagram of PMU, refers to Figure 3-1.
Page 710 GD32F403xx User Manual TIMER6_HOLD、TIMER5_HOLD、TIMER_7hold bits sequence, refers to Control register 0 (DBG_CTL0) In chapter 22.4.17-22.4.22, add the description of fliter register only be used by CAN0, refers to 22.4.17-22.4.22 Modify the description of SMBALT bit in I2C_STAT0 register Jun.30, 2021 In chapter 18.3.6, correct the word in Figure 18-7 and Figure 18-8 In chapter 21.3, modify the Figure 21-21, Figure 21-22...
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