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GigaDevice Semiconductor GD32F20 Series Hardware Development Manual

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GigaDevice Semiconductor Inc.
GD32F20x Hardware Development Guide
Application Note
AN107

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Summary of Contents for GigaDevice Semiconductor GD32F20 Series

  • Page 1 GigaDevice Semiconductor Inc. GD32F20x Hardware Development Guide Application Note AN107...

  • Page 2: Table Of Contents

    AN107 GD32F20x Hardware Development Guide Table of Contents Table of Contents ......................2 List of Figures ........................ 3 List of Tables ........................4 1. Introduction ......................5 2. Hardware design ...................... 6 Power supply ....................... 6 2.1. 2.1.1. Backup domain ........................6 2.1.2.

  • Page 3: List Of Figures

    AN107 GD32F20x Hardware Development Guide List of Figures Figure 2-1. GD32F20x Power supply overview ..................... 6 Figure 2-2. GD32 F20x Recommended Power Supply Design ..............8 Figure 2-3. Power-on/power-down reset waveforms ................... 9 Figure 2-4. LVD Threshold Waveform ......................10 Figure 2-5.

  • Page 4: List Of Tables

    AN107 GD32F20x Hardware Development Guide List of Tables Table 1-1. Applicable Products ........................5 Table 2-1. CKOUT0SEL[3:0] Control Bits ....................16 Table 2-2. CKOUT1SEL[3:0] Control Bits ....................16 Table 2-3. BOOT mode ..........................17 =28 MHz Relationship between sampling period and external input impedance ..19 Table 2-4.

  • Page 5: Introduction

    AN107 GD32F20x Hardware Development Guide Introduction The article is specially provided for developers of 32-bit general-purpose MCU GD32F20x series based on Arm ® Cortex ® -M3 architecture. It provides an overall introduction to the hardware development of GD32F20x series products, such as power supply, reset, clock, boot mode settings and download debugging.

  • Page 6: Hardware Design

    AN107 GD32F20x Hardware Development Guide Hardware design 2.1. Power supply The V operating voltage range of GD32F20x series products is 2.6 V ~ 3.6 V. For GD32F20x series, there are three power domains, including V domain, 1.2 V domain, and Backup domain, as is shown in Figure 2-1.

  • Page 7: Vdd /Vdda Domain

    AN107 GD32F20x Hardware Development Guide Note: If the V pin is left floating, the Power Switch will switch V to V after the MCU is powered on, and the internal V will directly supply power to the Backup domain. domain 2.1.2.

  • Page 8: Reset And Power Management

    AN107 GD32F20x Hardware Development Guide Figure 2-2. GD32 F20x Recommended Power Supply Design VBAT 100 nF N * VDD 4.7 μF + N * 100 nF VDDA VSSA 1 μF 10 nF VREFP VREFN 1 μF 10 nF GD32F20x Note: 1、...
  • Page 9 AN107 GD32F20x Hardware Development Guide Figure 2-3. Power-on/power-down reset waveforms 600mV hyst RSTTEMPO Power Reset (Active Low) The function of LVD is to detect whether the V supply voltage is lower than the low voltage detection threshold (2.2 V ~ 2.9 V), which is configured by the LVDT[2:0] bits in the power control register (PMU_CTL0).
  • Page 10 AN107 GD32F20x Hardware Development Guide Figure 2-4. LVD Threshold Waveform threshold 100mV hyst LVD output In addition, the MCU reset source can be judged by querying the register RCU_RSTSCK (0x40021024). This register can only clear the flag bit after a power-on reset. Therefore, during use, after the reset source is obtained, the reset flag can be cleared through the RSTFC control bit.

  • Page 11: Clock

    AN107 GD32F20x Hardware Development Guide Figure 2-7. Recommend External Reset Circuit External reset circuit 10 kΩ NRST 100 nF GD32F20x Note: The inside pull-up resistor R = 40kΩ, and the outside pull-up resistor is recommended to be 10kΩ, so that voltage interference will not cause the chip to work abnormally. If the influence of static electricity is considered, an ESD protection diode can be placed at the NRST pin.
  • Page 12 AN107 GD32F20x Hardware Development Guide Figure 2-8. GD32F205xx Clock Tree CK_HXTAL VCO input clock ×49,50, PLLTR prescaler TLI prescaler PLLT prescaler CK_TLI CK_PLLTR CK_VCO PLLT input clock (PLLTRPSC (TLIPSC ) …,432 (PLLTPSC ÷2,3...7 ÷2,4,8,16 ÷2,3...63 CK_IRC8M PLLTSEL PLLTMF (to FMC) CK_USBFS(=48 MHz) USBFS or CK_TRNG(<=48 MHz)

  • Page 13: External High-Speed Crystal Oscillator Clock (Hxtal)

    AN107 GD32F20x Hardware Development Guide Figure 2-9. GD32F207xx Clock Tree CK_HXTAL PLLTR prescaler TLI prescaler VCO input clock ×49,50, PLLT prescaler CK_PLLTR CK_TLI CK_VCO PLLT input clock (PLLTRPSC (TLIPSC ) …,432 (PLLTPSC ÷2,3...7 ÷2,4,8,16 ÷2,3...63 CK_IRC8M PLLTSEL PLLTMF (to FMC) CK_USBFS(=48 MHz) USBFS or CK_TRNG(<=48 MHz)
  • Page 14 AN107 GD32F20x Hardware Development Guide input is used, the signal is connected to OSC_IN, and OSC_OUT remains floating. The Bypass function of HXTAL needs to be turned on in software (enable the HXTALBPS bit in RCU_CTL). Figure 2-10. HXTAL External Crystal Circuit Figure 2-11.

  • Page 15: External Low-Speed Crystal Oscillator Clock (Lxtal)

    AN107 GD32F20x Hardware Development Guide External low-speed crystal oscillator clock (LXTAL) 2.2.2. LXTAL crystal is a 32.768KHz low-speed external crystal (passive crystal), which can provide a low-power and high-precision clock source for RTC. The RTC module of the MCU is equivalent to a counter.

  • Page 16: Clock Output Capability (Ckout)

    AN107 GD32F20x Hardware Development Guide value. If the application needs to use V to power the RTC, the RTC can still time normally, and the RTC must select LXTAL as the clock source. Clock Output Capability (CKOUT) 2.2.3. For GD32F20x series MCU, you can select two clock signal outputs by configuring the CKOUT0SEL[3:0] bits of the clock register RCU_CFG0 and CKOUT1SEL[3:0] bits of the clock register RCU_CFG2, the corresponding GPIO pin PA8/PA9 needs to be configured as a multiplexing function to output the selected signal, as shown in the following:...

  • Page 17: Startup Configuration

    AN107 GD32F20x Hardware Development Guide HXTAL failure will cause the IRC8M to be selected as the system clock source and the PLL will be automatically disabled. The clock source of the RTC needs to be reconfigured. 2.3. Startup Configuration The GD32F20x series provides three boot modes, which can be selected by the BOOT0 bit and the BOOT1 pin to determine the boot option.

  • Page 18: Typical Peripheral Modules

    AN107 GD32F20x Hardware Development Guide 2.4. Typical Peripheral Modules GPIO Circuit 2.4.1. The largest package GPIO interface includes 9 groups of general-purpose input/output ports, each group of ports provides up to 16 general-purpose input/output pins, which are PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0~PH1 and PI0 ~ PI11(unique to LQFP176 package of GD32F207), each pin can be independently configured through registers, the basic structure of GPIO port is shown in Figure 2-15.

  • Page 19: Adc Circuit

    AN107 GD32F20x Hardware Development Guide The same label PIN in multiple groups can only configure one port as an external interrupt. For example, PA0, PB0, and PC0 only support one of the three IO ports to generate external interrupts, and do not support three external interrupt modes. Non-5V tolerant IO, when the external voltage exceeds V , a sink current may be generated.

  • Page 20: Usb Circuit

    AN107 GD32F20x Hardware Development Guide (kΩ) (cycles) (us) AINmax 0.27 3.86 13.5 0.48 7.31 28.5 1.02 15.9 41.5 1.48 23.4 55.5 1.98 31.5 71.5 2.55 40.67 239.5 8.55 137.2 USB Circuit 2.4.3. GD32F20x interconnected MCU has a built-in USB interface, which is a USBFS module. The USB protocol requires a clock accuracy of not less than 500ppm, and the internal clock may not be able to achieve such accuracy, so it is recommended to use an external crystal or an active crystal oscillator as the USB module clock source when using the USB function.

  • Page 21: Standby Mode Wake-Up Circuit

    AN107 GD32F20x Hardware Development Guide Figure 2-18. Recommend USB-Host Reference Circuit 47 kΩ 470 Ω VBUS 50 Ω PA11 50 Ω PA12 Shield USB INTERFACE Recommendation: R = 1MΩ, C = 4700pF Standby mode wake-up circuit 2.4.4. The GD32F20x series supports three low-power modes, named sleep mode, deep-sleep mode and standby mode.

  • Page 22: Download And Debug Circuit

    AN107 GD32F20x Hardware Development Guide Download and debug circuit 2.5. GD32F20x series cores support JTAG debug interface and SWD debug interface. The JTAG interface standard is a 20-pin interface, including 5 signal interfaces, and the SWD interface standard is a 5-pin interface, including 2 signal interfaces. Note: After reset, the debug related ports are in input PU/PD mode, where: PA15: JTDI is in pull-up mode.

  • Page 23: Table 2-6. Swd Download Debug Interface Assignment

    AN107 GD32F20x Hardware Development Guide Figure 2-20. Recommend JTAG Wiring Reference Design 10 kΩ JTMS PA13 PA14 JTCK JTDI PA15 JTDO NJTRST RESET NRST 10 kΩ JTAG GD32F20x Table 2-6. SWD Download Debug Interface Assignment Alternate function GPIO port SWDIO PA13 SWCLK PA14...
  • Page 24 AN107 GD32F20x Hardware Development Guide Figure 2-21. Recommend SWD Wiring Reference Design 10 kΩ SWDIO PA13 PA14 SWCLK RESET NRST 10 kΩ GD32F20x There are several ways to improve the reliability of SWD download and debugging communication and enhance the anti-interference ability of download and debugging. 1.

  • Page 25: Reference Schematic Design

    AN107 GD32F20x Hardware Development Guide Reference Schematic Design 2.6. Figure 2-22. GD32F20x Recommend Reference Schematic Design +3V3 +3V3 +3V3 +3V3 +3V3 +3V3 33Ω 33Ω 33Ω 33Ω 33Ω 33Ω PF10 PF10 PF11 33Ω PF11 PF12 33Ω PF12 PF13 33Ω PF13 PA10 PF14 33Ω...
  • Page 26 AN107 GD32F20x Hardware Development Guide Peripheral +3V3 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF 50V/0.1uF JNTRST JTDI PA15 JTMS/SWDIO PA13 JTCK/SWDCLK PA14 JTDO VBAT +3V3 +3V3 Battety 10KΩ +3V3 Vbat select JNTRST JTDI JTMS/SWDIO 10KΩ...

  • Page 27: Pcb Layout Design

    AN107 GD32F20x Hardware Development Guide PCB Layout Design In order to enhance the functional stability and EMC performance of the MCU, it is not only necessary to consider the performance of the supporting peripheral components, but also the PCB Layout. In addition, when conditions permit, try to choose a PCB design solution with an independent GND layer and an independent power supply layer, which can provide better EMC performance.

  • Page 28: Reset Circuit

    AN107 GD32F20x Hardware Development Guide Figure 3-2. Recommend Clock Pin Layout Design (passive crystal) Note: The crystal should be as close to the MCU clock pin as possible, and the matching capacitor should be as close as possible to the crystal. The whole circuit should be on the same layer as the MCU, and the wiring should not go through the layer as much as possible.

  • Page 29: Usb Circuit

    AN107 GD32F20x Hardware Development Guide the NRST pin of the MCU, and the NRST trace should be kept away from devices with strong interference risk and high-speed traces as far as possible. If conditions permit, it had better to wrap the NRST traces for better shielding effect. 3.4.

  • Page 30: Package Description

    AN107 GD32F20x Hardware Development Guide Package Description GD32F20x series has a total of 4 package types, namely LQFP176, LQFP144, LQFP100 and LQFP64. Table 4-1. Package Description Ordering code Package GD32F20xRxT6 LQFP64(10x10, 0.5 pitch) GD32F20xVxT6 LQFP100(14x14, 0.5 pitch) GD32F20xZxT6 LQFP144(20x20, 0.5 pitch) GD32F207IxT6 LQFP176(24x24, 0.5 pitch) (Original dimensions are in millimeters)

  • Page 31: Revision History

    AN107 GD32F20x Hardware Development Guide Revision history Table 5-1. Revision history Revision No. Description Date Initial Release Apr.7. 2023...
  • Page 32 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.

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