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Summary of Contents for GigaDevice Semiconductor GD32F20x
- Page 1 GigaDevice Semiconductor Inc. GD32F20x ® Cortex -M3 32-bit MCU ® User Manual Revision 2.7 ( Jun 2022 )
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Page 2: Table Of Contents
GD32F20x User Manual Table of Contents Table of Contents ........................2 List of Figures ........................20 List of Tables ......................... 28 1. System and memory architecture ................32 1.1. Arm Cortex-M3 processor....................32 1.2. System architecture ......................33 1.3. Memory map ........................34 1.3.1. - Page 3 GD32F20x User Manual 2.4.5. Control register 0 (FMC_CTL0) ...................... 56 2.4.6. Address register 0 (FMC_ADDR0)....................57 2.4.7. Option byte status register (FMC_OBSTAT) ................. 58 2.4.8. Erase/Program protection register (FMC_WP) ................58 2.4.9. Unlock key register 1 (FMC_KEY1) ....................59 2.4.10.
- Page 4 GD32F20x User Manual 5.2. Clock control unit (CCTL) ..................... 81 5.2.1. Overview ............................81 5.2.2. Characteristics........................... 83 5.2.3. Function overview ..........................83 5.3. Register definition ......................89 5.3.1. Control register (RCU_CTL) ......................89 5.3.2. Configuration register 0 (RCU_CFG0) ..................91 5.3.3.
- Page 5 GD32F20x User Manual 7. General-purpose and alternate-function I/Os (GPIO and AFIO) ......135 7.1. Overview ......................... 135 7.2. Characteristics ......................... 135 7.3. Function overview ......................135 7.3.1. GPIO pin configuration ........................136 7.3.2. External interrupt/event lines ......................137 7.3.3. Alternate functions (AF) ......................... 137 7.3.4.
- Page 6 GD32F20x User Manual 7.5.15. AFIO port configuration register 2 (AFIO_PCF2) ............... 169 7.5.16. AFIO port configuration register 3 (AFIO_PCF3) ............... 172 7.5.17. AFIO port configuration register 4 (AFIO_PCF4) ............... 176 7.5.18. AFIO port configuration register 5 (AFIO_PCF5) ............... 179 8. Cyclic redundancy checks management unit (CRC) .......... 183 8.1.
- Page 7 GD32F20x User Manual 10.9.1. CAU control register (CAU_CTL) ....................207 10.9.2. CAU Status register 0 (CAU_STAT0) ..................208 10.9.3. CAU data input register (CAU_DI) ....................209 10.9.4. CAU data output register (CAU_DO) ................... 210 10.9.5. CAU DMA enable register (CAU_DMAEN) ................. 210 10.9.6.
- Page 8 GD32F20x User Manual 12.4.8. Interrupt ............................235 12.4.9. DMA request mapping ........................236 12.5. Register definition ....................240 12.5.1. Interrupt flag register (DMA_INTF) ....................240 12.5.2. Interrupt flag clear register (DMA_INTC) ..................240 12.5.3. Channel x control register (DMA_CHxCTL)................241 12.5.4.
- Page 9 GD32F20x User Manual 14.3.11. ADC internal channels ....................... 261 14.3.12. Programmable resolution (DRES) ................... 262 14.3.13. On-chip hardware oversampling ....................263 14.4. ADC sync mode ......................264 14.4.1. Free mode ............................265 14.4.2. Routine parallel mode ........................265 14.4.3. Routine Follow-up fast mode ......................266 14.4.4.
- Page 10 GD32F20x User Manual 15.4.6. DAC1 12-bit right-aligned data holding register (DAC1_R12DH) ..........290 15.4.7. DAC1 12-bit left-aligned data holding register (DAC1_L12DH) ..........291 15.4.8. DAC1 8-bit right-aligned data holding register (DAC1_R8DH) ..........291 15.4.9. DAC concurrent mode 12-bit right-aligned data holding register (DACC_R12DH) ....291 15.4.10.
- Page 11 GD32F20x User Manual 18.1.1. Overview ............................316 18.1.2. Characteristics..........................316 18.1.3. Block diagram ..........................316 18.1.4. Function overview ........................... 317 18.1.5. Register definition ........................... 345 18.2. General level0 timer (TIMERx, x=1, 2, 3, 4) ..............372 18.2.1. Overview ............................372 18.2.2.
- Page 12 GD32F20x User Manual 19.3.9. Synchronous mode ......................... 481 19.3.10. IrDA SIR ENDEC mode ......................482 19.3.11. Half-duplex communication mode .................... 484 19.3.12. Smartcard (ISO7816-3) mode ....................484 19.3.13. USART interrupts ........................486 Register definition ....................488 19.4. 19.4.1. Status register 0 (USART_STAT0) ....................488 19.4.2.
- Page 13 GD32F20x User Manual 20.4.9. Rise time register (I2C_RT)......................528 Serial peripheral interface/Inter-IC sound (SPI/I2S) ......... 529 21.1. Overview ........................529 21.2. Characteristics ......................529 21.2.1. SPI characteristics .......................... 529 21.2.2. I2S characteristics .......................... 529 21.3. SPI function overview ....................530 21.3.1.
- Page 14 GD32F20x User Manual 22.5. Function overview ......................569 22.5.1. DCI hardware synchronization mode ................... 569 22.5.2. Embedded synchronization mode ....................570 22.5.3. Capture data using snapshot or continuous capture modes ............ 570 22.5.4. Window function ..........................571 22.5.5. Pixel formats, data padding and DMA ..................571 22.6.
- Page 15 GD32F20x User Manual 23.6.8. Interrupt enable register (TLI_INTEN) ..................591 23.6.9. Interrupt flag register (TLI_INTF) ....................592 23.6.10. Interrupt flag clear register (TLI_INTC) ................... 593 23.6.11. Line mark register (TLI_LM) ...................... 594 23.6.12. Current pixel position register (TLI_CPPOS) ................. 594 23.6.13.
- Page 16 GD32F20x User Manual 24.7. Specific operations ....................... 647 24.7.1. SD I/O specific operations ......................647 24.7.2. CE-ATA specific operations ......................651 24.8. Register definition ......................653 24.8.1. Power control register (SDIO_PWRCTL) ..................653 24.8.2. Clock control register (SDIO_CLKCTL) ..................653 24.8.3.
- Page 17 GD32F20x User Manual 26.3.3. Data transmission ........................... 737 26.3.4. Data reception ..........................739 26.3.5. Filtering function ..........................740 26.3.6. Time-triggered communication ..................... 743 26.3.7. Communication parameters ......................744 26.3.8. Error flags ............................745 26.3.9. CAN interrupts ..........................746 26.4. Register definition ......................748 26.4.1.
- Page 18 GD32F20x User Manual 27.3.6. DMA controller description ......................795 27.3.7. Example for a typical configuration flow of Ethernet ..............814 27.3.8. Ethernet interrupts .......................... 816 27.4. Register definition ....................818 27.4.1. MAC configuration register (ENET_MAC_CFG) ................ 818 27.4.2. MAC frame filter register (ENET_MAC_FRMF) ................. 820 27.4.3.
- Page 19 GD32F20x User Manual 27.4.38. PTP time stamp update low register (ENET_PTP_TSUL) ........... 845 27.4.39. PTP time stamp addend register (ENET_PTP_TSADDEND) ..........846 27.4.40. PTP expected time high register (ENET_PTP_ETH) ............846 27.4.41. PTP expected time low register (ENET_PTP_ETL) .............. 847 27.4.42.
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Page 20: List Of Figures
® Figure 1-1. Cortex -M3 block diagram ......................33 Figure 1-2. GD32F20x Connectivity line series system architecture ............34 Figure 2-1. Process of page erase operation ....................47 Figure 2-2. Process of mass erase operation ..................... 48 Figure 2-3. Process of word program operation ..................49 Figure 3-1. - Page 21 GD32F20x User Manual Figure 12-5. DMA1 request mapping ......................238 Figure 14-1. ADC module block diagram ....................255 Figure 14-2. Single operation mode ......................256 Figure 14-3. Continuous operation mode ....................257 Figure 14-4. Scan operation mode, continuous disable ................. 258 Figure 14-5.
- Page 22 GD32F20x User Manual Figure 18-21. Counter behavior with CI0FE0 polarity inverted in mode 2 ........... 335 Figure 18-22. Hall sensor is used to BLDC motor ..................336 Figure 18-23. Hall sensor timing between two timers ................337 Figure 18-24. Restart mode .......................... 338 Figure 18-25.
- Page 23 GD32F20x User Manual Figure 18-65. Timing chart of internal clock divided by 1 ............... 441 Figure 18-66. Timing chart of PSC value change from 0 to 2 ..............441 Figure 18-67. Up-counter timechart, PSC=0/2 ................... 442 Figure 18-68. Up-counter timechart, change TIMERx_CAR on the go ..........443 Figure 18-69.
- Page 24 GD32F20x User Manual mode) ................................ 515 Figure 21-1. Block diagram of SPI ....................... 530 Figure 21-2. SPI timing diagram in normal mode ..................531 Figure 21-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) ........532 Figure 21-4. A typical full-duplex connection ................... 535 Figure 21-5.
- Page 25 GD32F20x User Manual CHLEN=1, CKPL=0) ..........................549 Figure 21-38. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) ..........................549 Figure 21-39. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=0) ..........................549 Figure21-40. PCM standard long frame synchronization mode timing diagram (DTLEN=00, CHLEN=0, CKPL=1) ..........................
- Page 26 GD32F20x User Manual Figure 24-17. Multiple block 4-Bit read interrupt cycle timing ............... 651 Figure 24-18. Multiple block 4-Bit write interrupt cycle timing .............. 651 Figure 24-19. The operation for command completion disable signal ..........652 Figure 25-1. The EXMC block diagram ....................... 669 Figure 25-2.
- Page 27 GD32F20x User Manual Figure 26-4. Reception register ........................739 Figure 26-5. 32-bit filter ..........................741 Figure 26-6. 16-bit filter ..........................741 Figure 26-7. 32-bit mask mode filter ......................741 Figure 26-8. 16-bit mask mode filter ......................741 Figure 26-9. 32-bit list mode filter........................ 741 Figure 26-10.
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Page 28: List Of Tables
GD32F20x User Manual List of Tables Table 1-1 Memory map of GD32F20x devices ..................... 35 Table 1-2. Each block of SRAM........................39 Table 1-3. Boot modes ............................ 40 Table 1-4. Bootloader supported peripherals ..................... 40 Table 2-1. GD32F20x_CL ..........................44 Table 2-2. - Page 29 GD32F20x User Manual Table 14-7. ADC sync mode table ....................... 265 Table 15-1. DAC I/O description ........................282 Table 15-2. External triggers of DAC......................283 Table 16-1. Min/max FWDGT timeout period at 40 kHz (IRC40K) ............296 ) ................303 Table 16-2.
- Page 30 GD32F20x User Manual Table 24-4. Basic commands (class 0) ....................... 616 Table 24-5. Block-Oriented read commands (class 2) ................618 Table 24-6. Stream read commands (class 1) and stream write commands (class 3) ....... 619 Table 24-7. Block-Oriented write commands (class 4) ................620 Table 24-8.
- Page 31 GD32F20x User Manual Table 25-16. SPI/QPI interface ........................693 Table 25-17. 8-bit or 16-bit NAND interface signal ................... 696 Table 25-18. 16-bit PC card interface signal ....................696 Table 25-19. Bank1/2/3 of EXMC support the memory and access mode ..........696 Table 25-20.
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Page 32: System And Memory Architecture
GD32F20x User Manual System and memory architecture The devices of GD32F20x series are 32-bit general-purpose microcontrollers based on the processor includes three AHB Cortex -M3 processor. Cortex ® ® ® ® buses known as I-Code, D-Code and System buses. All memory accesses of the... -
Page 33: System Architecture
System architecture is shown in the Figure 1-2. GD32F20x Connectivity line series system architecture following figure. The AHB matrix based on AMBA 3.0 AHB-LITE is a multi-layer AHB, which enables parallel access paths between multiple masters and slaves in the system. There are seven masters on the AHB matrix, including ICode, DCode, system bus of the Cortex™-M3... -
Page 34: Memory Map
GD32F20x User Manual Figure 1-2. GD32F20x Connectivity line series system architecture SW/JTAG TPIU POR/ PDR Flash Flash Ibus Memory Arm Cortex-M3 Memory Controller : 144MHz Processor Dbus Fmax:120MHz EXMC Slave SRAM0 1.2V Slave Master SRAM1 NVIC Slave SRAM2 Slave HAU TRNG... -
Page 35: Table 1-1 Memory Map Of Gd32F20X Devices
Table 1-1 Memory map of GD32F20x devices GD32F20x series of devices, including Code, SRAM, peripheral, and other pre-defined regions. Each peripheral of each series is allocated 1KB of space. This allows simplifying the address decoding for each peripheral. The APB1 peripherals are located at the address region from 0x4000 0000 to 0x4000 FFFF, while the APB2 peripherals are located from 0x4001 0000 to 0x4001 7FFF. - Page 36 GD32F20x User Manual Pre-defined Address Peripherals Regions 0x4002 3C00 - 0x4002 3FFF Reserved 0x4002 3800 - 0x4002 3BFF Reserved 0x4002 3400 - 0x4002 37FF Reserved 0x4002 3000 - 0x4002 33FF 0x4002 2C00 - 0x4002 2FFF Reserved 0x4002 2800 - 0x4002 2BFF...
- Page 37 GD32F20x User Manual Pre-defined Address Peripherals Regions 0x4001 1C00 - 0x4001 1FFF GPIOF 0x4001 1800 - 0x4001 1BFF GPIOE 0x4001 1400 - 0x4001 17FF GPIOD 0x4001 1000 - 0x4001 13FF GPIOC 0x4001 0C00 - 0x4001 0FFF GPIOB 0x4001 0800 - 0x4001 0BFF...
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Page 38: Bit-Banding
GD32F20x User Manual Pre-defined Address Peripherals Regions 0x4000 0C00 - 0x4000 0FFF TIMER4 0x4000 0800 - 0x4000 0BFF TIMER3 0x4000 0400 - 0x4000 07FF TIMER2 0x4000 0000 - 0x4000 03FF TIMER1 0x2007 0000 - 0x3FFF FFFF Reserved 0x2006 0000 - 0x2006 FFFF... -
Page 39: On-Chip Sram Memory
On-chip SRAM memory 1.3.2. The GD32F20x series of devices contain up to 384 KB of on-chip SRAM which starts at the address 0x2000 0000. It supports byte, half-word (16 bits), and word (32 bits) accesses. On- chip SRAM is divided into three blocks, including SRAM0, SRAM1, and SRAM2. Each one owns a dedicated port connected to the AHB bus matrix. -
Page 40: Device Electronic Signature
SRAM using the NVIC exception table and offset register. The embedded boot loader is located in the System memory, which is used to reprogram the Flash memory. In GD32F20x devices, the boot loader can be activated through the USART and USB interface, as shown in Table 1-4. -
Page 41: Memory Size Information
GD32F20x User Manual Memory size information 1.5.1. Base address: 0x1FFF F7E0 The value is factory programmed and can never be altered by user. This register has to be accessed by word(32-bit) SRAM_DENSITY [15:0] FLASH_DENSITY [15:0] Bits Fields Descriptions 15:0 SRAM_DENSITY[15: SRAM memory size The value indicates the SRAM memory size of the device in Kbytes. -
Page 42: System Configuration Registers
GD32F20x User Manual UNIQUE_ID[63:48] UNIQUE_ID[47:32] Bits Fields Descriptions 31:0 UNIQUE_ID[63:32] Unique device ID Address offset: 0x08 The value is factory programmed and can never be altered by user. UNIQUE_ID[95:80] UNIQUE_ID[79:64] Bits Fields Descriptions 31:0 UNIQUE_ID[95:64] Unique device ID System configuration registers 1.6. - Page 43 GD32F20x User Manual 1: Code execution efficiency enhancement Reserved Must be kept at reset value Note: Only bit[7] can be read-modify-write, other bits are not permitted.
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Page 44: Flash Memory Controller (Fmc)
GD32F20x User Manual Flash memory controller (FMC) 2.1. Overview The flash memory controller, FMC, provides all the necessary functions for the on-chip flash memory. There is no waiting time while CPU executes instructions stored in the first 384K(in case that flash size equal to 256K or 512K, all memory is no waiting time) bytes of the flash . -
Page 45: Read Operations
GD32F20x User Manual Block Name Address Range Size (bytes) Page 2 0x0800 1000 - 0x0800 17FF Page 255 0x0807 F800 - 0x0807 FFFF Page 256 0x0808 0000 - 0x0808 0FFF Page 257 0x0808 1000 - 0x0808 1FFF Page 895 0x082F F000 - 0x082F FFFF... -
Page 46: Page Erase
GD32F20x User Manual Page erase 2.3.4. The FMC provides a page erase function which is used to initialize the contents of a main flash memory page to a high state. Each page can be erased independently without affecting the contents of other pages. The following steps show the access sequence of the registers for a page erase operation. -
Page 47: Mass Erase
GD32F20x User Manual Figure 2-1. Process of page erase operation Start Unlock the Is the LK bit is 0 FMC_CTLx Is the BUSY bit is 0 Set the PER bit, Write FMC_ADDRx Send the command to FMC by setting START bit... -
Page 48: Main Flash Programming
GD32F20x User Manual Read and verify the flash memory by using a DBUS access if required. When the operation is executed successfully, the ENDF in FMC_STATx registers is set, and an interrupt will be triggered by FMC if the ENDIE bit in the FMC_CTLx registers is set. Since... -
Page 49: Figure 2-3. Process Of Word Program Operation
GD32F20x User Manual Write a 32-bit word/16-bit half word to desired absolute address (0x08XX XXXX) by DBUS. Wait until all the operations have been finished by checking the value of the BUSY bit in FMC_STATx registers. Read and verify the Flash memory by using a DBUS access if required. -
Page 50: Option Bytes Erase
GD32F20x User Manual Option bytes erase 2.3.7. The FMC provides an erase function which is used to initialize the option bytes block in flash. The following steps show the erase sequence. Unlock the FMC_CTL0 register if necessary. Check the BUSY bit in FMC_STAT0 register to confirm that no Flash memory operation is in progress (BUSY equal to 0). -
Page 51: Option Bytes Description
GD32F20x User Manual Option bytes description 2.3.9. The option bytes block is reloaded to FMC_OBSTAT and FMC_WP registers after each system reset, and the option bytes take effect. The complement option bytes are the opposite of option bytes. When option bytes reload, if the complement option byte and option byte do not match, the OBERR bit in FMC_OBSTAT register is set, and the option byte is set to 0xFF. -
Page 52: Page Erase/Program Protection
GD32F20x User Manual Address Name Description Page erase/program protection bit 31 to 24 OB_WP[30:24]: Each bit is related to 4KB flash protection, that means 2 pages for GD32F20x_CL. Bit 0 0x1fff f80e OB_WP[31:24] configures the first 4KB flash protection, and so on. - Page 53 GD32F20x User Manual Note: In the case of read protection, the first 4k of flash cannot be programmed or erased.
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Page 54: Register Definition
GD32F20x User Manual 2.4. Register definition FMC base address: 0x4002 2000 Wait state register (FMC_WS) 2.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved WSCNT[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. -
Page 55: Option Byte Unlock Key Register (Fmc_Obkey)
GD32F20x User Manual FMC_CTL0 register Option byte unlock key register (FMC_OBKEY) 2.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). OBKEY[31:16] OBKEY[15:0] Bits Fields Descriptions 31:0 OBKEY[31:0] FMC_CTL0 option bytes operation unlock key These bits are only be written by software. -
Page 56: Control Register 0 (Fmc_Ctl0)
GD32F20x User Manual Reserved Must be kept at reset value. PGERR Program error flag bit When program to the flash while it is not 0xFFFF, this bit is set by hardware. The software can clear it by writing 1. Reserved Must be kept at reset value. -
Page 57: Address Register 0 (Fmc_Addr0)
GD32F20x User Manual This bit can be set by software. START Send erase command to FMC bit This bit is set by software to send erase command to FMC. This bit is cleared by hardware when the BUSY bit is cleared. -
Page 58: Option Byte Status Register (Fmc_Obstat)
GD32F20x User Manual Bits Fields Descriptions 31:0 ADDR[31:0] Flash erase/program command address bits These bits are configured by software. ADDR bits are the address of flash erase/program command Option byte status register (FMC_OBSTAT) 2.4.7. Address offset: 0x1C Reset value: 0x0XXX XXXX This register has to be accessed by word(32-bit). -
Page 59: Unlock Key Register 1 (Fmc_Key1)
GD32F20x User Manual Bits Fields Descriptions 31:0 WP[31:0] Store OB_WP of option bytes block after system reset Unlock key register 1 (FMC_KEY1) 2.4.9. Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). KEY[31:16] KEY[15:0]... -
Page 60: Control Register 1 (Fmc_Ctl1)
GD32F20x User Manual Reserved Must be kept at reset value. PGERR Program error flag bit When program to the flash while it is not 0xFFFF, this bit is set by hardware. The software can clear it by writing 1. Reserved Must be kept at reset value. -
Page 61: Address Register 1 (Fmc_Addr1)
GD32F20x User Manual hardware when the BUSY bit is cleared. Reserved Must be kept at reset value. Main flash mass erase for bank1 command bit This bit is set or cleared by software 0: no effect 1: main flash mass erase command for bank1... -
Page 62: Product Id Register (Fmc_Pid)
GD32F20x User Manual Reserved WSEN Bits Fields Descriptions 31:1 Reserved Must be kept at reset value. WSEN FMC wait state enable This bit is set and reset by software. This bit also protected by the FMC_KEYx register. It is necessary to writing 0x45670123 and 0xCDEF89AB to the FMC_KEYx register. -
Page 63: Power Management Unit (Pmu)
The power consumption is regarded as one of the most important issues for the devices of GD32F20x series. Power management unit (PMU) provides three types of power saving modes, including Sleep, Deep-sleep and Standby mode. These modes reduce the power consumption and allow the application to achieve the best tradeoff among the conflicting demands of CPU operating time, speed and power consumption. -
Page 64: Backup Domain
GD32F20x User Manual Figure 3-1. Power supply overview Backup Domain Power Switch 3.3V LXTAL BPOR WKUP WKUPR BREG BKP PAD WKUPN NRST WKUPF SLEEPING Cortex-M3 FWDGT SLEEPDEEP HXTAL POR / PDR AHB IPs APB IPs 1.2V Domain 1.2V Domain Domain... -
Page 65: Vdd / V Dda
GD32F20x User Manual saving mode by executing the WFI / WFE instruction, the Cortex ® -M3 can setup the RTC register with an expected wakeup time and enable the wakeup function to achieve the RTC wakeup event. After entering the power saving mode for a certain amount of time, the RTC will wake up the device when the time match event occurs. -
Page 66: Figure 3-3. Waveform Of The Lvd Threshold
GD32F20x User Manual Figure 3-2. Waveform of the POR / PDR 600mV hyst RSTTEMPO Power Reset (Active Low) domain The LVD is used to detect whether the V supply voltage is lower than a programmed threshold selected by the LVDT[2:0] bits in the Power control register (PMU_CTL). The LVD... -
Page 67: Power Domain
Power saving modes 3.3.4. After a system reset or a power reset, the GD32F20x MCU operates at full function and all power domains are active. Users can achieve lower power consumption through slowing down the system clocks (HCLK, PCLK1, PCLK2) or gating the clocks of the unused peripherals. - Page 68 GD32F20x User Manual According to the SLEEPONEXIT bit in the Cortex ® -M3 System Control Register, there are two options to select the Sleep mode entry mechanism. Sleep-now: if the SLEEPONEXIT bit is cleared, the MCU enters Sleep mode as soon as WFI or WFE instruction is executed.
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Page 69: Table 3-1. Power Saving Mode Summary
GD32F20x User Manual Table 3-1. Power saving mode summary Mode Sleep Deep-sleep Standby All clocks in the 1.2V The 1.2V domain is domain are off. power off Description Only CPU clock is off Disable IRC8M, HXTAL Disable IRC8M, and PLL. -
Page 70: Register Definition
GD32F20x User Manual 3.4. Register definition PMU base address: 0x4000 7000 Control register (PMU_CTL) 3.4.1. Address offset: 0x00 Reset value: 0x0000 0000 (reset by wakeup from Standby mode) This register can be accessed by half-word (16-bit) or word (32-bit). Reserved... -
Page 71: Control And Status Register (Pmu_Cs)
GD32F20x User Manual 0: No effect 1: Reset the wakeup flag This bit is always read as 0. STBMOD Standby Mode ® 0: Enter the Deep-sleep mode when the Cortex -M3 enters SLEEPDEEP mode ® 1: Enter the Standby mode when the Cortex... - Page 72 GD32F20x User Manual 1: The device has been in the Standby mode This bit is cleared only by a POR / PDR or by setting the STBRST bit in the PMU_CTL register. Wakeup Flag 0: No wakeup event has been received...
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Page 73: Backup Registers (Bkp)
GD32F20x User Manual Backup registers (BKP) 4.1. Overview The Backup registers are located in the Backup domain that remains powered-on by V even if V power is shut down. The Backup registers have forty two 16-bit (84 bytes) registers that can be used to store and protect user application data. Wake-up action from Standby mode or system reset do not affect these registers. -
Page 74: Tamper0 Detection
GD32F20x User Manual Tamper0 detection 4.3.2. In order to protect the important user data, the MCU provides the tamper detection function, and it can be independently enabled on TAMPER0 pin (PC13) by setting corresponding TPEN0 bit in the BKP_TPCTL register. To prevent the tamper event from losing, the edge detection is logically ANDed with the TPEN0 bit, the result is used as tamper detection signal. -
Page 75: Register Definition
GD32F20x User Manual 4.4. Register definition BPK base address: 0x4000 6C00 Backup data register x (BKP_DATAx) (x= 0..41) 4.4.1. Address offset: 0x04 to 0x28, 0x40 to 0xBC Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) -
Page 76: Tamper Pin Control Register0 (Bkp_Tpctl0)
GD32F20x User Manual CCOSEL RTC clock output selection 0: RTC clock div 64 1: RTC clock 13:10 Reserved Must be kept at reset value. ROSEL RTC output selection 0: RTC alarm pulse is selected as the RTC output 1: RTC second pulse is selected as the RTC output This bit is reset only by a Backup domain reset. -
Page 77: Tamper Control And Status Register (Bkp_Tpcs)
GD32F20x User Manual 1: The TAMPER0 pin is active low TPEN0 TAMPER0 detection enable 0: The TAMPER0 pin is free for GPIO functions 1: The TAMPER0 pin is dedicated for the Backup Reset function. The active level on the TAMPER0 pin resets all data of the BKP_DATAx register. -
Page 78: Tamper Pin Control Register1 (Bkp_Tpctl1)
GD32F20x User Manual 1: Enable the tamper1 interrupt This bit is reset only by a system reset and wake-up from Standby mode. TIR1 Tamper1/waveform detect interrupt reset 0: No effect 1: Reset the TIF1 bit This bit is always read as 1. - Page 79 GD32F20x User Manual 0: No effect 1: Detect waveform of RTCCLK/64, need configure CCOSEL to 0, TPEN0, TPEN1 to 0 PC13 -> PI8 TPM2 The second Waveform detection enable 0: No effect 1: Detect waveform of RTCCLK/64, need configure CCOSEL to 0, TPEN0, TPEN1 to 0 PC14 ->...
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Page 80: Reset And Clock Unit (Rcu)
Overview 5.1.1. GD32F20x reset control includes three control modes: power reset, system reset and backup domain reset. The power reset, known as a cold reset, resets the full system except the The system reset resets the processor core and peripheral IP components backup domain. -
Page 81: Clock Control Unit (Cctl)
GD32F20x User Manual Figure 5-1. The system reset circuit NRST Filter POWER_RSTn WWDGT_RSTn min 20 us pulse System Reset FWDGT_RSTn generator SW_RSTn OB_STDBY_RSTn OB_DPSLP_RSTn Backup domain reset A backup domain reset is generated by setting the BKPRST bit in the backup domain control... -
Page 82: Figure 5-2. Clock Tree
GD32F20x User Manual Figure 5-2. Clock tree CK_HXTAL VCO input clock ×49,50, PLLTR prescaler TLI prescaler PLLT prescaler CK_TLI CK_PLLTR CK_VCO PLLT input clock (PLLTRPSC (TLIPSC ) (PLLTPSC ,432 ÷2,3...7 ÷2,4,8,16 ÷2,3...63 CK_IRC8M PLLTSEL PLLTMF (to FMC) CK_USBFS(=48 MHz) USBFS or CK_TRNG(<=48 MHz) -
Page 83: Characteristics
GD32F20x User Manual The ADCs are clocked by the clock of APB2 divided by 2, 4, 6, 8, 12 or 16, which defined by ADCPSC in RCU_CFG0. The TIMERs are clocked by the clock divided from CK_APB2 and CK_APB1. The frequency of TIMERs clock is equal to CK_APBx(APB prescaler is 1), twice the CK_APBx(APB prescaler is not 1). -
Page 84: Figure 5-3. Hxtal Clock Source
GD32F20x User Manual Figure 5-3. HXTAL clock source The HXTAL crystal oscillator can be switched on or off using the HXTALEN bit in the control register RCU_CTL. The HXTALSTB flag in control register RCU_CTL indicates if the high- speed external crystal oscillator is stable. When the HXTAL is powered up, it will not be released for use until this HXTALSTB bit is set by the hardware. - Page 85 GD32F20x User Manual frequency is still less accurate than HXTAL. The application requirements, environment and cost will determine which oscillator type is selected. If the HXTAL or PLL is the system clock source, to minimize the time required for the system to recover from the Deep-sleep Mode, the hardware forces the IRC8M clock to be the system clock when the system initially wakes-up.
- Page 86 GD32F20x User Manual drives the OSC32IN pin. Internal 40 RC oscillator (IRC40K) The internal RC oscillator has a frequency of about 40 kHz and is a low power clock source for the Real Time Clock circuit or the Free Watchdog Timer. The IRC40K offers a low cost clock source as no external components are required.
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Page 87: Table 5-1. Clock Output 0 Source Select
GD32F20x User Manual Table 5-1. Clock Output 0 source select CKOUT0SEL Clock Source 00xx No Clock 0100 CK_SYS 0101 CK_IRC8M 0110 CK_HXTAL 0111 CK_PLL/2 1000 CK_PLL1 1001 (CK_PLL2)/2 1010 EXT1 1011 CK_PLL2 The CKOUT0 frequency can be reduced by a configurable binary divider, controlled by the CKOUT0DIV[5:0] bits , in the configuration register 2, RCU_CFG2. - Page 88 GD32F20x User Manual...
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Page 89: Register Definition
GD32F20x User Manual Register definition 5.3. RCU start address: 0x4002 1000 Control register (RCU_CTL) 5.3.1. Address offset: 0x00 Reset value: 0x0000 xx83 where x is undefined. This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) HXTALB HXTALST HXTALE Reserved PLL2STB PLL2EN PLL1STB PLL1EN... - Page 90 GD32F20x User Manual 0: PLL is not stable 1: PLL is stable PLLEN PLL enable Set and reset by software. This bit cannot be reset if the PLL clock is used as the system clock. Reset by hardware when entering Deep-sleep or Standby mode.
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Page 91: Configuration Register 0 (Rcu_Cfg0)
GD32F20x User Manual Reserved Must be kept at reset value. IRC8MSTB IRC8M Internal 8MHz RC Oscillator stabilization Flag Set by hardware to indicate if the IRC8M oscillator is stable and ready for use. 0: IRC8M oscillator is not stable 1: IRC8M oscillator is stable... - Page 92 GD32F20x User Manual 1010: EXT1 selected, to provide the external clock for ENET 1011: CK_PLL2 clock selected 23:22 USBFSPSC[1:0] USBFS and TRNG clock prescaler selection Set and reset by software. The USBFS clock must be 48MHz. These bits also control the random analog generator (TRNG) clock (≤48 MHz). These bits can’t be reset if the USBFS clock is enabled.
- Page 93 GD32F20x User Manual 11101: (PLL source clock x 30) 11110: (PLL source clock x 31) 11111: (PLL source clock x 32) PREDV0_LSB The LSB of PREDV0 division factor This bit is the same bit as PREDV0 division factor bit [0] from RCU_CFG1. Changing the PREDV0 division factor bit [0] from RCU_CFG1, this bit is also changed.
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Page 94: Interrupt Register (Rcu_Int)
GD32F20x User Manual 1000: (CK_SYS / 2) selected 1001: (CK_SYS / 4) selected 1010: (CK_SYS / 8) selected 1011: (CK_SYS / 16) selected 1100: (CK_SYS / 64) selected 1101: (CK_SYS / 128) selected 1110: (CK_SYS / 256) selected 1111: (CK_SYS / 512) selected... - Page 95 GD32F20x User Manual CKMIC HXTAL Clock Stuck Interrupt Clear Write 1 by software to reset the CKMIF flag. 0: Not reset CKMIF flag 1: Reset CKMIF flag PLL2STBIC PLL2 stabilization Interrupt Clear Write 1 by software to reset the PLL2STBIF flag.
- Page 96 GD32F20x User Manual 0: Disable the PLL1 stabilization interrupt 1: Enable the PLL1 stabilization interrupt PLLSTBIE PLL stabilization Interrupt Enable Set and reset by software to enable/disable the PLL stabilization interrupt. 0: Disable the PLL stabilization interrupt 1: Enable the PLL stabilization interrupt...
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Page 97: Apb2 Reset Register (Rcu_Apb2Rst)
GD32F20x User Manual Reset when setting the PLLSTBIC bit by software. 0: No PLL stabilization interrupt generated 1: PLL stabilization interrupt generated HXTALSTBIF HXTAL stabilization interrupt flag Set by hardware when the High speed 4 ~ 32 MHz crystal oscillator clock is stable and the HXTALSTBIE bit is set. - Page 98 GD32F20x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. TIMER10RST Timer 10 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER10 TIMER9RST Timer 9 reset This bit is set and reset by software.
- Page 99 GD32F20x User Manual 1: Reset the ADC1 ADC0RST ADC0 reset This bit is set and reset by software. 0: No reset 1: Reset the ADC0 PGRST GPIO port G reset This bit is set and reset by software. 0: No reset...
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Page 100: Apb1 Reset Register (Rcu_Apb1Rst)
GD32F20x User Manual APB1 reset register (RCU_APB1RST) 5.3.5. Address offset: 0x10 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) CAN1 CAN0 UART4 UART3 USART2 USART1 Reserved DACRST PMURST BKPIRST Reserved I2C1RST I2C0RST Reserved WWDGT TIMER13... - Page 101 GD32F20x User Manual 0: No reset 1: Reset the I2C1 I2C0RST I2C0 reset This bit is set and reset by software. 0: No reset 1: Reset the I2C0 UART4RST UART4 reset This bit is set and reset by software. 0: No reset...
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Page 102: Ahb1 Enable Register (Rcu_Ahb1En)
GD32F20x User Manual This bit is set and reset by software. 0: No reset 1: Reset the TIMER13 TIMER12RST TIMER12 reset This bit is set and reset by software. 0: No reset 1: Reset the TIMER12 TIMER11RST TIMER11 reset This bit is set and reset by software. - Page 103 GD32F20x User Manual This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) ENET Reserved RXEN ENET USBFS SRAM ENETEN Reserved Reserved SDIOEN Reserved EXMCEN Reserved CRCEN Reserved Reserved DMA1EN DMA0EN TXEN SPEN SPEN Bits Fields Descriptions 31:17 Reserved Must be kept at reset value.
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Page 104: Apb2 Enable Register (Rcu_Apb2En)
GD32F20x User Manual 1: Enabled EXMC clock Reserved Must be kept at reset value. CRCEN CRC clock enable This bit is set and reset by software. 0: Disabled CRC clock 1: Enabled CRC clock Reserved Must be kept at reset value. - Page 105 GD32F20x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. TIMER10EN TIMER10 clock enable This bit is set and reset by software. 0: Disabled TIMER10 clock 1: Enabled TIMER10 clock TIMER9EN TIMER9 clock enable This bit is set and reset by software.
- Page 106 GD32F20x User Manual 0: Disabled ADC1 clock 1: Enabled ADC1 clock ADC0EN ADC0 clock enable This bit is set and reset by software. 0: Disabled ADC0 clock 1: Enabled ADC0 clock PGEN GPIO port G clock enable This bit is set and reset by software.
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Page 107: Apb1 Enable Register (Rcu_Apb1En)
GD32F20x User Manual 1: Enabled Alternate Function IO clock APB1 enable register (RCU_APB1EN) 5.3.8. Address offset: 0x1C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) UART4 UART3 USART2 USART1 Reserved DACEN PMUEN BKPIEN CAN1EN CAN0EN... - Page 108 GD32F20x User Manual I2C1EN I2C1 clock enable This bit is set and reset by software. 0: Disabled I2C1 clock 1: Enabled I2C1 clock I2C0EN I2C0 clock enable This bit is set and reset by software. 0: Disabled I2C0 clock 1: Enabled I2C0 clock...
- Page 109 GD32F20x User Manual 10:9 Reserved Must be kept at reset value. TIMER13EN TIMER13 clock enable This bit is set and reset by software. 0: Disabled TIMER13 clock 1: Enabled TIMER13 clock TIMER12EN TIMER12 clock enable This bit is set and reset by software.
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Page 110: Backup Domain Control Register (Rcu_Bdctl)
GD32F20x User Manual Backup domain control register (RCU_BDCTL) 5.3.9. Address offset: 0x20 Reset value: 0x0000 0018, reset by backup domain reset. This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) Note: The LXTALEN, LXTALBPS, LXTALDRI, RTCSRC and RTCEN bits of the Backup domain control register (RCU_BDCTL) are only reset after a backup domain reset. -
Page 111: Reset Source/Clock Register (Rcu_Rstsck)
GD32F20x User Manual 00: Lower driving capability 01: Medium low driving capability 10: Medium high driving capability 11: Higher driving capability (reset value) Note: The LXTALDRI is not in bypass mode. LXTALBPS LXTAL bypass mode enable Set and reset by software. - Page 112 GD32F20x User Manual Set by hardware when a window watchdog timer reset generated. Reset by writing 1 to the RSTFC bit. 0: No window watchdog reset generated 1: Window watchdog reset generated FWDGTRSTF Free watchdog timer reset flag Set by hardware when a free watchdog timer reset generated.
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Page 113: Ahb1 Reset Register (Rcu_Ahb1Rst)
GD32F20x User Manual AHB1 reset register (RCU_AHB1RST) 5.3.11. Address offset: 0x28 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) Reserved ENET USBFS Reserved Reserved Reserved Bits Fields Descriptions 31:15 Reserved Must be kept at reset value. - Page 114 GD32F20x User Manual 31:19 Reserved Must be kept at reset value. I2S2SEL I2S2 clock source selection Set and reset by software to control the I2S2 clock source. 0: System clock selected as I2S2 source clock 1: (CK_PLL2 x 2) selected as I2S2 source clock...
- Page 115 GD32F20x User Manual PREDV1[3:0] PREDV1 division factor This bit is set and reset by software. These bits can be written when PLL1 and PLL2 are disable. 0000: PREDV1 input source clock not divided 0001: PREDV1 input source clock divided by 2...
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Page 116: Deep-Sleep Mode Voltage Register (Rcu_Dsv)
GD32F20x User Manual Deep-sleep mode voltage register (RCU_DSV) 5.3.13. Address offset: 0x34 Reset value: 0x0000 0000. This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) Reserved Reserved DSLPVS[2:0] Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. DSLPVS[2:0]... -
Page 117: Apb2 Additional Enable Register (Rcu_Addapb2En)
GD32F20x User Manual This bit is set and reset by software. 0: Disabled HAU clock 1: Enabled HAU clock CAUEN CAU clock enable This bit is set and reset by software. 0: Disabled CAU clock 1: Enabled CAU clock Reserved Must be kept at reset value. -
Page 118: Apb1 Additional Enable Register (Rcu_Addapb1En)
GD32F20x User Manual 1: Enabled TLI clock Reserved Must be kept at reset value. USART5EN USART5 clock enable This bit is set and reset by software. 0: Disabled USART5 clock 1: Enabled USART5 clock 23:0 Reserved Must be kept at reset value. -
Page 119: Ahb2 Reset Register (Rcu_Ahb2Rst)
GD32F20x User Manual AHB2 reset register (RCU_AHB2RST) 5.3.17. Address offset: 0x70 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit) Reserved TRNGRS Reserved HAURST CAURST Reserved DCIRST Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. -
Page 120: Apb1 Additional Reset Register (Rcu_Addapb1Rst)
GD32F20x User Manual USART5 PIRST PHRST Reserved TLIRST Reserved Reserved Reserved Bits Fields Descriptions PIRST GPIO port I reset This bit is set and reset by software. 0: No reset 1: Reset the GPIO port I PHRST GPIO port H reset This bit is set and reset by software. -
Page 121: Configuration Register 2 (Rcu_ Cfg2)
GD32F20x User Manual Bits Fields Descriptions UART7RST UART7 reset This bit is set and reset by software. 0: No reset 1: Reset the UART7 UART6RST UART6 reset This bit is set and reset by software. 0: No reset 1: Reset the UART6... -
Page 122: Pllt Control Register (Rcu_Plltctl)
GD32F20x User Manual 1010: EXT1 selected 1011: CK_PLL2 clock selected 15:14 Reserved Must be kept at reset value. 13:8 CKOUT1DIV[5:0] The CK_OUT1 divider which the CK_OUT1 frequency can be reduced Set and reset by software. 000000: The CK_OUT1 is divided by 1... -
Page 123: Pllt Interrupt Register (Rcu_Plltint)
GD32F20x User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. PLLTSTB PLLT Clock Stabilization Flag Set by hardware to indicate if the PLLT output clock is stable and ready for use. 0: PLLT is not stable... -
Page 124: Pllt Configuration Register (Rcu_Plltcfg)
GD32F20x User Manual Set by hardware when the PLLT is stable and the PLLTSTBIE bit is set. Reset by software when setting the PLLTSTBIC bit. 0: No PLLT stabilization interrupt generated 1: PLLT stabilization interrupt generated Reserved Must be kept at reset value. - Page 125 GD32F20x User Manual 11: TLIPSC = 16 Reserved Must be kept at reset value. 14:6 PLLTMF[8:0] PLLT multiply factor for VCO Set and reset by software to control the multiplication factor of the VCO. These bits should be written when the PLLT is disabled.
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Page 126: Interrupt/Event Controller(Exti)
GD32F20x User Manual Interrupt/event controller(EXTI) 6.1. Overview Cortex-M3 integrates the Nested Vectored Interrupt Controller (NVIC) for efficient exception and interrupts processing. NVIC facilitates low-latency exception and interrupt handling and controls power management. It’s tightly coupled to the processer core. You can read the... -
Page 127: Table 6-1. Nvic Exception Types In Cortex ® -M3
GD32F20x User Manual Cortex ® Table 6-1. NVIC exception types in Vector Exception Type Priority (a) Vector Address Description Number 0x0000_0000 Reserved Reset 0x0000_0004 Reset 0x0000_0008 Non maskable interrupt. HardFault 0x0000_000C All class of fault MemManage Programmable 0x0000_0010 Memory management... - Page 128 GD32F20x User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number DMA0 Channel3 global interrupt 0x0000_0078 IRQ 14 IRQ 15 DMA0 Channel4 global interrupt 0x0000_007C IRQ 16 DMA0 Channel5 global interrupt 0x0000_0080 IRQ 17 DMA0 Channel6 global interrupt 0x0000_0084...
- Page 129 GD32F20x User Manual Interrupt Vector Peripheral Interrupt Description Vector Address Number Number ADC2 global interrupt 0x0000_00FC IRQ 47 IRQ 48 EXMC global interrupt 0x0000_0100 IRQ 49 SDIO global interrupt 0x0000_0104 IRQ 50 TIMER4 global interrupt 0x0000_0108 SPI2 global interrupt 0x0000_010C...
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Page 130: External Interrupt And Event (Exti) Block Diagram
GD32F20x User Manual Note: The IRQ61 and IRQ62 are available only in the GD32F207xx device. 6.4. External interrupt and event (EXTI) block diagram Figure 6-1. Block diagram of EXTI Polarity Software Control Trigger EXTI Line0~19 Edge detector To NVIC Interrupt Mask... -
Page 131: Table 6-3. Exti Source
GD32F20x User Manual Table 6-3. EXTI source EXTI Line Number Source PA0/PB0/PC0/PD0/PE0/PF0/PG0/PH0/PI0 PA1/PB1/PC1/PD1/PE1/PF1/PG1/PH1/PI1 PA2/PB2/PC2/PD2/PE2/PF2/PG2/PH2/PI2 PA3/PB3/PC3/PD3/PE3/PF3/PG3/PH3/PI3 PA4/PB4/PC4/PD4/PE4/PF4/PG4/PH4/PI4 PA5/PB5/PC5/PD5/PE5/PF5/PG5/PH5/PI5 PA6/PB6/PC6/PD6/PE6/PF6/PG6/PH6/PI6 PA7/PB7/PC7/PD7/PE7/PF7/PG7/PH7/PI7 PA8/PB8/PC8/PD8/PE8/PF8/PG8/PH8/PI8 PA9/PB9/PC90/PD9/PE9/PF9/PG9/PH9/PI9 PA10/PB10/PC10/PD10/PE10/PF10/PG10/PH10/PI10 PA11/PB11/PC11/PD11/PE11/PF11/PG11/PH11/PI11 PA12/PB12/PC12/PD12/PE12/PF12/PG12/PH12 PA13/PB13/PC13/PD13/PE13/PF13/PG13/PH13 PA14/PB14/PC14/PD14/PE14/PF14/PG14/PH14 PA15/PB15/PC15/PD15/PE15/PF15/PG15/PH15 RTC Alarm USBFS Wake-up Ethernet Wake-up Note: The EXTI line19 is available only in the GD32F207xx device. -
Page 132: Register Definition
GD32F20x User Manual 6.6. Register definition EXTI start address: 0x4001 0400 Interrupt enable register (EXTI_INTEN) 6.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved INTEN19 INTEN18 INTEN17 INTEN16 INTEN15 INTEN14 INTEN13 INTEN12 INTEN11 INTEN10... -
Page 133: Rising Edge Trigger Enable Register (Exti_Rten)
GD32F20x User Manual Rising edge trigger enable register (EXTI_RTEN) 6.6.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved RTEN19 RTEN18 RTEN17 RTEN16 RTEN15 RTEN14 RTEN13 RTEN12 RTEN11 RTEN10 RTEN9 RTEN8 RTEN7 RTEN6... -
Page 134: Pending Register (Exti_Pd)
GD32F20x User Manual This register has to be accessed by word(32-bit) Reserved SWIEV19 SWIEV18 SWIEV17 SWIEV16 SWIEV15 SWIEV14 SWIEV13 SWIEV12 SWIEV11 SWIEV10 SWIEV9 SWIEV8 SWIEV7 SWIEV6 SWIEV5 SWIEV4 SWIEV3 SWIEV2 SWIEV1 SWIEV0 Bits Fields Descriptions 31:20 Reserved Must be kept at reset value... -
Page 135: General-Purpose And Alternate-Function I/Os (Gpio And Afio)
GD32F20x User Manual General-purpose and alternate-function I/Os (GPIO and AFIO) 7.1. Overview There are up to 140 general purpose I/O pins (GPIO), named PA0 ~ PA15, PB0 ~ PB15, PC0 ~ PC15, PD0 ~ PD15, PE0 ~ PE15, PF0 ~ PF15, PG0 ~ PG15, PH0 ~ PH15 and PI0 ~ PI11 for the device to implement logic input/output functions. -
Page 136: Gpio Pin Configuration
GD32F20x User Manual Table 7-1. GPIO configuration table Configuration mode CTL[1:0] MD[1:0] OCTL don’t care Analog don’t care Input floating Input Input pull-down Input pull-up Push-pull 0 or 1 General purpose 00: Not used Output (GPIO) Open-drain 0 or 1... -
Page 137: External Interrupt/Event Lines
GD32F20x User Manual The GPIO pins can be configured as inputs or outputs. When the GPIO pins are configured as input pins, all GPIO pins have an internal weak pull-up and weak pull-down which can be chosen. And the data on the external pins can be captured at every APB2 clock cycle to the port input status register (GPIOx_ISTAT). -
Page 138: Output Configuration
GD32F20x User Manual Output configuration 7.3.5. When GPIO pin is configured as output: The schmitt trigger input is enabled. The weak pull-up and pull-down resistors are disabled. The output buffer is enabled. Open Drain Mode: The pad output low level when a “0” in the output control register. -
Page 139: Alternate Function (Af) Configuration
GD32F20x User Manual Alternate function (AF) configuration 7.3.7. To suit for different device packages, the GPIO supports some alternate functions mapped to some other pins by software. When be configured as alternate function: The output buffer is enabled in Open-Drain or Push-Pull configuration. -
Page 140: Gpio Locking Function
GD32F20x User Manual GPIOx_CTL0/GPIOx_CTL1 registers. And set output function by configuring MDy bits to 0b01, 0b10, or 0b11 and configuring CTLy bits of corresponding port in GPIOx_CTL0/GPIOx_CTL1 register to 0b10 (for AF push-pull output) or 0b11 (for AF open-drain output). -
Page 141: Adc Af Remapping
GD32F20x User Manual Pin Name Function description PA13 JTMS / SWDIO PA14 JTCK / SWCLK PA15 JTDI JTDO / TRACESWO NJTRST To reduce the number of GPIOs used to debug, user can configure SWJ_CFG [2:0] bits in the AFIO_PCF0 to different value. Refer to Table 7-3. -
Page 142: Timer Af Remapping
GD32F20x User Manual Register ADC0 ADC1 ADC1 external signal trigger ADC1_ETRGINS_REMAP routine conversion is connected to EXTI15 ADC1 external signal trigger ADC1_ETRGINS_REMAP routine conversion is connected to TIMER7_CH3 ADC1 external signal trigger ADC1_ETRGRER_REMA routine conversion is connected P = 0... -
Page 143: Usart Af Remapping
GD32F20x User Manual TIMERx_REMAP [1:0](x = 0，1，2) Alternate TIMERx_REMAP(x = 8，9，10，12，13) function “0”/“00” (no “1”/“01” (partial “10” (partial “11” (full remap) remap) remap) remap) TIMER1_CH3 PB11 TIMER2_CH0 PA15 TIMER2_CH1 TIMER2_CH2 TIMER2_CH3 TIMER3_CH0 PD12 TIMER3_CH1 PD13 TIMER3_CH2 PD14 TIMER3_CH3 PD15 TIMER8_CH0... -
Page 144: I2C Af Remapping
GD32F20x User Manual Table 7-7. USART0/1/2 alternate function remapping Register USART0 USART1 USART2 PA9(USART0_TX) USART0_REMAP = 0 PA10(USART0_RX) PB6(USART0_TX) USART0_REMAP = 1 PB7(USART0_RX) PA0(USART1_CTS) PA1(USART1_RTS) USART1_REMAP = 0 PA2(USART1_TX) PA3(USART1_RX) PA4(USART1_CK) PD3(USART1_CTS) PD4(USART1_RTS) USART1_REMAP = 1 PD5(USART1_TX) PD6(USART1_RX) PD7(USART1_CK) PB10(USART2_TX) -
Page 145: Spi Af Remapping
GD32F20x User Manual I2C1_REMAP[1:0] = 00/01 PB10 PB11 PB12 I2C1_REMAP[1:0] = 10 I2C1_REMAP[1:0] = 11 I2C2_REMAP1 = 1 I2C2_REMAP2 = 1 SPI AF remapping 7.4.8. Refer to AFIO port configuration register 0 (AFIO_PCF0). Table 7-8. SPI0/SPI1/I2S1/SP2/I2S2 alternate function remapping Register... -
Page 146: Can0/1 Af Remapping
GD32F20x User Manual SPI1/I2S1 Register SPI0 SPI2/I2S2 PA15(SPI2_NSS/ I2S2_WS) PB3(SPI2_SCK/ I2S2_CK) SPI2_REMAP = 0 PB4(SPI2_MISO) PB5(SPI2_MOSI/I2S2_SD) PA4(SPI2_NSS/ I2S2_WS) PC10(SPI2_SCK/ I2S2_CK) SPI2_REMAP = 1 PC11(SPI2_MISO) PC12(SPI2_MOSI/I2S2_SD) SPI2_MOSI_REMA PD6(SPI2_MOSI/I2S2_SD) P = 1 CAN0/1 AF remapping 7.4.9. The CAN0/1 signals can be mapped on Port A, Port B or Port D as shown in table below. For port D, remapping is not possible in devices delivered in 64-pin packages. -
Page 147: Ethernet Af Remapping
GD32F20x User Manual Ethernet AF remapping 7.4.10. Table 7-10. ENET alternate function remapping Register ENET PA7(RX_DV-CRS_DV) PC4(RXD0) ENET_REMAP = “0” PC5(RXD1) PB0(RXD2) PB1(RXD3) PD8(RX_DV-CRS_DV) PD9(RXD0) ENET_REMAP = “1” PD10(RXD1) PD11(RXD2) PD12(RXD3) PA0(MII_CRS) PA3(MII_COL) refer to ENET_REMAP(MII_RXD2) ENET_RX_HI_REMAP/ refer to ENET_REMAP(MII_RXD3) -
Page 148: Dci Af Remapping
GD32F20x User Manual DCI AF remapping 7.4.11. Table 7-11. DCI alternate function remapping DCI_Dx_ DCI_Dx_ DCI_Dx_ DCI_Dx_ Alternate function REMAP = “00” REMAP = “01” REMAP = “10” REMAP = “11” DCI_D0 DCI_D1 PA10 PH10 DCI_D2 PG10 PH11 DCI_D3 PG11... -
Page 149: Clk Pins Af Remapping
GD32F20x User Manual AFIO_PCF3 AFIO_PCF4 Alternate function TLI_xx_Pn_ REMAP = 1 TLI_xx_Pn_ REMAP = 1 TLI_G5 PB11 TLI_G6 TLI_G7 TLI_B0 TLI_B1 PG12 TLI_B2 PD6 / PG10 TLI_B3 PD10 / PG11 TLI_B4 PE12 PI4 / PG12 TLI_B5 TLI_B6 TLI_B7 TLI_DE PE13 / PF10... -
Page 150: Table 7-15. Osc Pins Configuration 2
GD32F20x User Manual Table 7-15. OSC pins configuration 2 Alternate function PH01_REMAP = 0 PH01_REMAP = 1 OSC_IN OSC_OUT Only for 176 pin packages, PH0/PH1 default to OSC_IN, OSC_OUT, when PH01_REMAP =1, PH0/PH1 is general-purpose IO port. -
Page 151: Register Definition
GD32F20x User Manual 7.5. Register definition GPIOA base address: 0x4001 0800 GPIOB base address: 0x4001 0C00 GPIOC base address: 0x4001 1000 GPIOD base address: 0x4001 1400 GPIOE base address: 0x4001 1800 GPIOF base address: 0x4001 1C00 GPIOG base address: 0x4001 2000... - Page 152 GD32F20x User Manual These bits are set and cleared by software refer to MD0[1:0]description 23:22 CTL5[1:0] Port 5 configuration bits These bits are set and cleared by software refer to CTL0[1:0]description 21:20 MD5[1:0] Port 5 mode bits These bits are set and cleared by software...
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Page 153: Port Control Register 1 (Gpiox_Ctl1, X=A
GD32F20x User Manual 11: Reserved Output mode ( MD[1:0] >00) 00: GPIO output with push-pull 01: GPIO output with open-drain 10: AFIO output with push-pull 11: AFIO output with open-drain MD0[1:0] Port 0 mode bits These bits are set and cleared by software... - Page 154 GD32F20x User Manual refer to CTL0[1:0]description. 21:20 MD13[1:0] Port 13 mode bits These bits are set and cleared by software. refer to MD0[1:0]description. 19:18 CTL12[1:0] Port 12 configuration bits These bits are set and cleared by software. refer to CTL0[1:0]description.
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Page 155: Port Input Status Register (Gpiox_Istat, X=A
GD32F20x User Manual Port input status register (GPIOx_ISTAT, x=A..I) 7.5.3. Address offset: 0x08 Reset value: 0x0000 XXXX This register has to be accessed by word (32-bit). Reserved ISTAT15 ISTAT14 ISTAT13 ISTAT12 ISTAT11 ISTAT10 ISTAT9 ISTAT8 ISTAT7 ISTAT6 ISTAT5 ISTAT4 ISTAT3... -
Page 156: Port Bit Operate Register (Gpiox_Bop, X=A
GD32F20x User Manual Port bit operate register (GPIOx_BOP, x=A..I) 7.5.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). CR15 CR14 CR13 CR12 CR11 CR10 BOP15 BOP14 BOP13 BOP12 BOP11 BOP10 BOP9 BOP8 BOP7... -
Page 157: Port Configuration Lock Register (Gpiox_Lock, X=A
GD32F20x User Manual 1: Clear the corresponding OCTLy bit to 0 Port configuration lock register (GPIOx_LOCK, x=A..I) 7.5.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved LK15 LK14 LK13 LK12 LK11 LK10... -
Page 158: Afio Port Configuration Register 0 (Afio_Pcf0)
GD32F20x User Manual Bits Fields Descriptions 31:8 Reserved Must be kept at reset value Event output enable Set and cleared by software.When set the EVENTOUT Cortex output is connected to the I/O selected by the PORT[2:0] and PIN[3:0] bits PORT[2:0] Event output port selection Set and cleared by software.Select the port used to output the Cortex EVENTOUT... - Page 159 GD32F20x User Manual PTP_PPS_REMAP Ethernet PTP PPS remapping This bit is set and cleared by software. It enables the Ethernet MAC_PPS to be output on the PB5 pin. 0: PPT_PPS not output PB5 pin 1: PPT_PPS is output on PB5 pin...
- Page 160 GD32F20x User Manual connections with PHY 0: No remap (RX_DV-CRS_DV/PA7,RXD0/PC4,RXD1/PC5,RXD2/PB0, RXD3/PB1) 1: Remap (RX_DV-CRS_DV/PD8,RXD0/PD9,RXD1/PD10,RXD2/PD11, RXD3/PD12) ADC1_ETRGREG_REMAP ADC 1 external trigger routine conversion remapping Set and cleared by software. The bit control the trigger input connected to ADC1 external trigger routine conversion. When this bit is reset, the ADC1 external trigger routine conversion to EXTI11.When this bit is set, the ADC1...
- Page 161 GD32F20x User Manual TIMER3_REMAP TIMER3 remapping This bit is set and cleared by software. 0: No remap (TIMER3_CH0/PB6,TIMER3_CH1/PB7,TIMER3_CH2/PB8, TIMER3_CH3/PB9) 1: Full remap (TIMER3_CH0/PD12,TIMER3_CH1/PD13, TIMER3_CH2/PD14,TIMER3_CH3/PD15) 11:10 TIMER2_REMAP [1:0] TIMER2 remapping These bits are set and cleared by software 00: No remap (TIMER2_CH0/PA6,TIMER2_CH1/PA7,TIMER2_CH2/PB0,...
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Page 162: Exti Sources Selection Register 0 (Afio_Extiss0)
GD32F20x User Manual USART2_CK/PB12,USART2_CTS/PB13, USART2_RTS/PB14) 01: Partial remap (USART2_TX/PC10, USART2_RX /PC11, USART2_CK/PC12,USART2_CTS/PB13, USART2_RTS/PB14) 10: Not used 11: Full remap (USART2_TX/PD8, USART2_RX /PD9, USART2_CK/PD10,USART2_CTS/PD11, USART2_RTS/PD12) USART1_REMAP USART1 remapping This bit is set and cleared by software 0: No remap (USART1_CTS/PA0, USART1_RTS/PA1,USART1_TX/PA2,... - Page 163 GD32F20x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:12 EXTI3_SS [3:0] EXTI 3 sources selection 0000: PA3 pin 0001: PB3 pin 0010: PC3 pin 0011: PD3 pin 0100: PE3 pin 0101: PF3 pin 0110: PG3 pin...
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Page 164: Exti Sources Selection Register 1 (Afio_Extiss1)
GD32F20x User Manual 0110: PG0 pin 0111: PH0 pin 1000: PI0 pin Other configurations are reserved. EXTI sources selection register 1 (AFIO_EXTISS1) 7.5.11. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved... -
Page 165: Exti Sources Selection Register 2 (Afio_Extiss2)
GD32F20x User Manual EXTI5_SS [3:0] EXTI 5 sources selection 0000: PA5 pin 0001: PB5 pin 0010: PC5 pin 0011: PD5 pin 0100: PE5 pin 0101: PF5 pin 0110: PG5 pin 0111: PH5 pin 1000: PI5 pin Other configurations are reserved. - Page 166 GD32F20x User Manual 0011: PD11 pin 0100: PE11 pin 0101: PF11 pin 0110: PG11 pin 0111: PH11 pin 1000: PI11 pin Other configurations are reserved. 11:8 EXTI10_SS [3:0] EXTI 10 sources selection 0000: PA10 pin 0001: PB10 pin 0010: PC10 pin...
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Page 167: Exti Sources Selection Register 3 (Afio_Extiss3)
GD32F20x User Manual EXTI sources selection register 3 (AFIO_EXTISS3) 7.5.13. Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved EXTI15_SS [3:0] EXTI14_SS [3:0] EXTI13_SS [3:0] EXTI12_SS [3:0] Bits Fields Descriptions 31:16 Reserved... -
Page 168: Afio Port Configuration Register 1 (Afio_Pcf1)
GD32F20x User Manual EXTI12_SS [3:0] EXTI 12 sources selection 0000: PA12 pin 0001: PB12 pin 0010: PC12 pin 0011: PD12 pin 0100: PE12 pin 0101: PF12 pin 0110: PG12 pin Other configurations are reserved. AFIO port configuration register 1 (AFIO_PCF1) 7.5.14. -
Page 169: Afio Port Configuration Register 2 (Afio_Pcf2)
GD32F20x User Manual 1: Remap (PF8) TIMER10_REMAP TIMER10 remapping This bit is set and cleared by software, it controls the mapping of the TIMER10_CH0 alternate function onto the GPIO ports 0: No remap (PB9) 1: Remap (PF7) TIMER9_REMAP TIMER9 remapping... - Page 170 GD32F20x User Manual DCI_HSYNC_ DCI_HSYNC remapping REMAP This bit is set and cleared by software. 0: No remap (PA4) 1: DCI_HSYNC remapped to PH8 28:27 DCI_D13_ DCI_D13 remapping REMAP [1:0] This bit is set and cleared by software. 00: No remap (PG7)
- Page 171 GD32F20x User Manual 00: No remap (PB9) 01: DCI_D7 remapped to PE6 10: Reserved 11: DCI_D7 remapped to PI7 15:14 DCI_D6_ DCI_D6 remapping REMAP [1:0] This bit is set and cleared by software. 00: No remap (PB8) 01: DCI_D6 remapped to PE5...
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Page 172: Afio Port Configuration Register 3 (Afio_Pcf3)
GD32F20x User Manual DCI_D0_ DCI_D0 remapping REMAP [1:0] This bit is set and cleared by software. 00: No remap (PA9) 01: DCI_D0 remapped to PC6 10: Reserved 11: DCI_D0 remapped to PH9 DCI_VSYNC_ DCI_VSYNC remapping REMAP [1:0] This bit is set and cleared by software. - Page 173 GD32F20x User Manual 1: TLI_G3 remapped to PG10 TLI_CLK_PG7 TLI_CLK_PG7 remapping _REMAP This bit is set and cleared by software. 0: TLI_ CLK not remapped to PG7 1: TLI_ CLK remapped to PG7 TLI_R7_PG6 TLI_R7_PG6 remapping _REMAP This bit is set and cleared by software.
- Page 174 GD32F20x User Manual 0: TLI_ G0 not remapped to PE5 1: TLI_ G0 remapped to PE5 TLI_B0_PE4 TLI_B0_PE4 remapping _REMAP This bit is set and cleared by software. 0: TLI_ B0 not remapped to PE4 1: TLI_ B0 remapped to PE4...
- Page 175 GD32F20x User Manual _REMAP This bit is set and cleared by software. 0: TLI_ B7 not remapped to PB9 1: TLI_ B7 remapped to PB9 TLI_B6_PB8 TLI_B6_PB8 remapping _REMAP This bit is set and cleared by software. 0: TLI_ B6 not remapped to PB8...
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Page 176: Afio Port Configuration Register 4 (Afio_Pcf4)
GD32F20x User Manual AFIO port configuration register 4 (AFIO_PCF4) 7.5.17. Address offset: 0x44 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). SPI2_ SPI1_ TLI_R1_P TLI_R0_P TLI_HSY TLI_VSY TLI_B7_P TLI_B6_P TLI_B5_P Reserved MOSI_ SCK_ NC_PI10 NC_PI9_... - Page 177 GD32F20x User Manual _REMAP This bit is set and cleared by software. 0: TLI_ VSYNC not remapped to PI9 1: TLI_ VSYNC remapped to PI9 TLI_B7_PI7 TLI_B7_PI7 remapping _REMAP This bit is set and cleared by software. 0: TLI_ B7 not remapped to PI7...
- Page 178 GD32F20x User Manual TLI_G2_PH13 TLI_G2_PH13 remapping _REMAP This bit is set and cleared by software. 0: TLI_ G2 not remapped to PH13 1: TLI_ G2 remapped to PH13 TLI_R6_PH12 TLI_R6_PH12 remapping _REMAP This bit is set and cleared by software.
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Page 179: Afio Port Configuration Register 5 (Afio_Pcf5)
GD32F20x User Manual 1: TLI_ B4 remapped to PG12 AFIO port configuration register 5 (AFIO_PCF5) 7.5.18. Address offset: 0x48 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). EXMC_S EXMC_S EXMC_S EXMC_S EXMC_S USART5_ USART5_ USART5_... - Page 180 GD32F20x User Manual USART5_RX_REMA USART5_RX remapping This bit is set and cleared by software 0: No remap (PC7) 1: USART5_RX remapped to PG9 USART5_TX_REMA USART5_TX remapping This bit is set and cleared by software 0: No remap (PC6) 1: USART5_TX remapped to PG14...
- Page 181 GD32F20x User Manual This bit is set and cleared by software 0: ETH_ PPS_OUT not remapped to PG8 1: ETH_ PPS_OUT remapped to PG8 ENET ETH_TXD3 remapping _TXD3_REMAP This bit is set and cleared by software 0: No remap. ETH_TXD3 mapped on PB8...
- Page 182 GD32F20x User Manual 1: TIMER7_CH0/ TIMER7_CH1/ TIMER7_CH2 / TIMER7_CH3/ TIMER7_ ETI / TIMER7_BKIN remapped to PI5/PI6/PI7/PI2/PI3/PI4 TIMER7_CHON_RE TIMER7_CH0_ON / TIMER7__CH1_ON / TIMER7_CH2_ON remapping MAP [1:0] This bit is set and cleared by software 00/01: No remap, TIMER7_CH0_ON / TIMER7_CH1_ON / TIMER7_CH2_ON...
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Page 183: Cyclic Redundancy Checks Management Unit (Crc)
GD32F20x User Manual Cyclic redundancy checks management unit (CRC) 8.1. Overview A cyclic redundancy check (CRC) is an error-detecting code commonly used in digital networks and storage devices to detect accidental changes to raw data. This CRC management unit can be used to calculate 32 bit CRC code with fixed polynomial. -
Page 184: Function Overview
GD32F20x User Manual 8.3. Function overview CRC management unit is used to calculate the 32-bit raw data, and CRC_DATA register will receive the raw data and store the calculation result. If the CRC_DATA register has not been cleared by software setting the CRC_CTL register, the new input raw data will be calculated based on the result of previous value of CRC_DATA. -
Page 185: Register Definition
GD32F20x User Manual 8.4. Register definition CRC base address: 0x4002 3000 Data register (CRC_DATA) 8.4.1. Address offset: 0x00 Reset value: 0xFFFF FFFF This register has to be accessed by word (32-bit). DATA [31:16] DATA [15:0] Bits Fields Descriptions 31:0 DATA [31:0] CRC calculation result bits Software writes and reads. -
Page 186: Control Register (Crc_Ctl)
GD32F20x User Manual by any other peripheral. The CRC_CTL register will take no effect to the byte. Control register (CRC_CTL) 8.4.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved Bits... -
Page 187: True Random Number Generator (Trng)
GD32F20x User Manual True random number generator (TRNG) 9.1. Overview The true random number generator (TRNG) module can generate a 32-bit random value by using continuous analog noise. GD32F207xx series microcontrollers have TRNG peripherals, GD32F205xx series microcontrollers do not have TRNG peripherals. -
Page 188: Operation Flow
GD32F20x User Manual generated random number depends on TRNG_CLK exclusively, no matter what HCLK frequency was set or not. The 32-bit value of LFSR will be transferred into TRNG_DATA register after a sufficient number of seeds have been sent to the LFSR. -
Page 189: Register Definition
GD32F20x User Manual 9.4. Register definition TRNG base address: 0x5006 0800 Control register (TRNG_CTL) 9.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte(8bit), half-word(16-bit) word (32-bit). Reserved Reserved TRNGEN Reserved Bits Fields Descriptions Must be kept at reset value. -
Page 190: Data Register (Trng_Data)
GD32F20x User Manual Bits Fields Descriptions Must be kept at reset value. 31:7 Reserved SEIF Seed error interrupt flag This bit will be set if more than 64 consecutive same bit or more than 32 consecutive 01 (or 10) changing are detected. - Page 191 GD32F20x User Manual Bits Fields Descriptions 31:0 TRNGDATA[31:0] 32-Bit Random data...
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Page 192: Cryptographic Acceleration Unit (Cau)
GD32F20x User Manual Cryptographic Acceleration Unit (CAU) 10.1. Overview The cryptographic acceleration unit (CAU) is used to encipher and decipher data with DES, Triple-DES or AES (128, 192, or 256) algorithms. It is fully compliant implementation of the following standards: ... -
Page 193: Cau Data Type And Initialization Vectors
GD32F20x User Manual 8*32-bit input and output FIFO Multiple data types are supported, including No swapping, Half-word swapping Byte swapping and Bit swapping Data can be transferred by DMA, CPU during interrupts, or without both of them 10.3. -
Page 194: Initialization Vectors
GD32F20x User Manual Figure 10-2. DATAM Byte swapping and Bit swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Byte swapping WORD 0 (MSB) WORD 1 WORD 2 WORD 3 (LSB) Bit swapping Initialization vectors 10.3.2. The initialization vectors are used in CBC and CTR modes to XOR with data blocks. They are independent of plaintext and ciphertext, and the DATAM value will not affect them. -
Page 195: Des/Tdes Cryptographic Acceleration Processor
GD32F20x User Manual Figure 10-3. CAU diagram CAU_ CAU_ CAU_ CAU_ CAU_ CAU_ CAU_CTL CAU_STAT0 DMAEN INTEN INTF STAT1 KEY0..3 IV0..1 AHB BUS CAU_DI CAU_DO Input FIFO Output FIFO Config 8*32 8*32 Data swapping Data swapping Cryptographic acceleration core (DES/TDES/AES) DES/TDES cryptographic acceleration processor 10.4.1. -
Page 196: Figure 10-4. Des/Tdes Ecb Encryption
GD32F20x User Manual DES/TDES ECB encryption The 64-bit input plaintext is first obtained after data swapping according to the data type. When the TDES algorithm is configured, the input data block is read in the DEA and encrypted using KEY1. The output is fed back directly to next DEA and then decrypted using KEY2. -
Page 197: Figure 10-5. Des/Tdes Ecb Decryption
GD32F20x User Manual Figure 10-5. DES/TDES ECB decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt SWAP CAU_DO Plaintext DES/TDES CBC encryption The input data of the DEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. -
Page 198: Figure 10-6. Des/Tdes Cbc Encryption
GD32F20x User Manual Figure 10-6. DES/TDES CBC encryption CAU_DI Plaintext DATAM SWAP CAU_IV0(H/L) KEY1 DEA, encrypt KEY2 DEA, decrypt KEY3 DEA, encrypt SWAP CAU_DO Ciphertext DES/TDES CBC decryption In DES/TDES CBC decryption, when the TDES algorithm is configured, the first ciphertext block is used directly after data swapping according to the data type, it is read in the DEA and decrypted using KEY3. -
Page 199: Aes Cryptographic Acceleration Processor
GD32F20x User Manual Figure 10-7. DES/TDES CBC decryption CAU_DI Ciphertext DATAM SWAP KEY3 DEA, decrypt KEY2 DEA, encrypt KEY1 DEA, decrypt CAU_IV0(H/L) SWAP CAU_DO Plaintext AES cryptographic acceleration processor 10.4.2. The AES cryptographic acceleration processor consists of three components, including the AES algorithm (AEA), multiple keys and the initialization vectors or Nonce. -
Page 200: Figure 10-8. Aes Ecb Encryption
GD32F20x User Manual Figure 10-8. AES ECB encryption CAU_DI Plaintext DATAM SWAP CAU_KEY0...3 AEA, encrypt SWAP CAU_DO Ciphertext AES-ECB mode decryption First of all, the key derivation must be completed to prepare the decryption keys, the input key of the key schedule is the same to that used in encryption. The last round key obtained from the above operation is then used as the first round key in the decryption. -
Page 201: Figure 10-10. Aes Cbc Encryption
GD32F20x User Manual AES-CBC mode encryption The input data of the AEA block in CBC mode consists of two aspects: the input plaintext after data swapping according to the data type, and the initialization vectors. The XOR result of the swapped plaintext data block and the 128-bit initialization vector CAU_IV0..1 is read in the... -
Page 202: Figure 10-11. Aes Cbc Decryption
GD32F20x User Manual plaintext is also obtained after data swapping according to the data type. The procedure of AES CBC mode decryption is illustrated in Figure 10-11. AES CBC decryption. Figure 10-11. AES CBC decryption CAU_DI Ciphertext DATAM SWAP CAU_KEY0..3 AEA, decrypt CAU_IV0..1(H/L) -
Page 203: Operating Modes
GD32F20x User Manual Figure 10-13. AES CTR encryption/decryption Plaintext/ CAU_DI Ciphertext DATAM SWAP CAU_IV0..1(H/L) AEA, encrypt/ CAU_KEY0..3 decryp SWAP Ciphertext CAU_DO Plaintext 10.5. Operating modes Encryption Disable the CAU by resetting the CAUEN bit in the CAU_CTL register Select and configure the key length with the KEYM bits in the CAU_CTL register if AES algorithm is chosen. -
Page 204: Cau Dma Interface
GD32F20x User Manual Decryption 1. Disable the CAU by resetting the CAUEN bit in the CAU_CTL register Select and configure the key length with the KEYM bits in the CAU_CTL register if AES algorithm is chosen. Configure the CAU_KEY0..3(H/L) registers according to the algorithm Configure the DATAM bit in the CAU_CTL register to select the data swapping type Configure the ALGM bits to “111”... -
Page 205: Cau Suspended Mode
GD32F20x User Manual Any of input and output FIFO interrupt can be enabled or disabled by configuring the Interrupt Enable register CAU_INTEN. Value 1 of the register enable the interrupts. Input FIFO interrupt The input FIFO interrupt is asserted when the number of words in the input FIFO is less than four words, then ISTA is asserted. - Page 206 GD32F20x User Manual suspended at the end of a block processing. Disable the CAU by clearing the CAUEN bit in the CAU_CTL register. Save the configuration, including the key size, data type, operation mode, direction and the key values. When it is CBC or CTR chaining mode, the initialization vectors should also be stored.
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Page 207: Register Definition
GD32F20x User Manual 10.9. Register definition CAU start address: 0x5006 0000 CAU control register (CAU_CTL) 10.9.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved CAUEN FFLUSH Reserved KEYM[1:0] DATAM[1:0] ALGM[2:0] CAUDIR... -
Page 208: Cau Status Register 0 (Cau_Stat0)
GD32F20x User Manual ALGM[2:0] Encryption/decryption algorithm mode, must be configured when BUSY=0 000: TDES-ECB with CAU_KEY1, 2, 3. Initialization vectors (CAU_IV0..1) are not used 001: TDES-CBC with CAU_KEY1, 2, 3. Initialization vectors (CAU_IV0) is used to XOR with data blocks 010: DES-ECB with only CAU_KEY1 Initialization vectors (CAU_IV0..1) are not used... -
Page 209: Cau Data Input Register (Cau_Di)
GD32F20x User Manual - CAU is disabled by CAUEN=0 or the processing has been completed. - No enough data or no enough space in the input/output FIFO to perform a data block 1: CAU is processing data or key derivation. -
Page 210: Cau Data Output Register (Cau_Do)
GD32F20x User Manual CAU data output register (CAU_DO) 10.9.4. Address offset: 0x0C Reset value: 0x0000 0000 The data output register is a read only register. It is used to receive plaintext or ciphertext results from the output FIFO. Similar to CAU_DI, the MSB is read at first while the LSB is read at last. -
Page 211: Cau Interrupt Enable Register (Cau_Inten)
GD32F20x User Manual CAU interrupt enable register (CAU_INTEN) 10.9.6. Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved OINTEN IINTEN Bits Fields Descriptions 31:2 Reserved Must keep the reset value. OINTEN... -
Page 212: Cau Interrupt Flag Register (Cau_Intf)
GD32F20x User Manual 0: IN FIFO interrupt not pending 1: IN FIFO interrupt flag pending CAU interrupt flag register (CAU_INTF) 10.9.8. Address offset: 0x1C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved OINTF... - Page 213 GD32F20x User Manual NOTE: “||” is a concatenation operator. For example, X || Y denotes the concatenation of two bit strings X and Y. CAU_KEY0H Address offset: 0x20 Reset value: 0x0000 0000 KEY0H[31:16] KEY0H[15:0] CAU_KEY0L Address offset: 0x24 Reset value: 0x0000 0000...
- Page 214 GD32F20x User Manual CAU_KEY2H Address offset: 0x30 Reset value: 0x0000 0000 KEY2H[31:16] KEY2H[15:0] CAU_KEY2L Address offset: 0x34 Reset value: 0x0000 0000 KEY2L[31:16] KEY2L[15:0] CAU_KEY3H Address offset: 0x38 Reset value: 0x0000 0000 KEY3H[31:16] KEY3H[15:0] CAU_KEY3L Address offset: 0x3C Reset value: 0x0000 0000...
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Page 215: Cau Initial Vector Registers (Cau_Iv0
GD32F20x User Manual KEY0...3(H/L) The key for DES, TDES, AES 31:0 CAU Initial vector registers (CAU_IV0..1(H/L)) 10.9.10. Address offset: 0x40 to 0x4C Reset value: 0x0000 0000 This registers have to be accessed by word (32-bit), and all of them must be written when BUSY is 0. - Page 216 GD32F20x User Manual CAU_IV1L Address offset: 0x4C Reset value: 0x0000 0000 IV1L[31:16] IV1L[15:0] Bits Fields Descriptions IV0...1(H/L) The initialization vector for DES, TDES, AES 31:0...
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Page 217: Hash Acceleration Unit (Hau)
GD32F20x User Manual Hash Acceleration Unit (HAU) 11.1. Overview The hash acceleration unit is used for information security. The secure hash algorithm (SHA- 1, SHA-224, SHA-256), the message-digest algorithm (MD5) and the keyed-hash message authentication code (HMAC) algorithm are supported for various applications. The digest will... -
Page 218: Figure 11-1. Datam No Swapping And Half-Word Swapping
GD32F20x User Manual Byte swapping and Bit swapping illustrate the data swapping according to different data types. Figure 11-1. DATAM No swapping and Half-word swapping word0 word0 WORD 0 (MSB) word1 word1 WORD 1 word2 word2 WORD 2 word3 WORD 3 (LSB) -
Page 219: Hau Core
GD32F20x User Manual 11.4. HAU core The hash acceleration unit is used to compute condensed information of input messages with secure hash algorithms. The digest result has a length of 160/224/256/128 bits for a message up to (2 - 1) bits computed by SHA-1, SHA-224, SHA256 and MD5 algorithms respectively. -
Page 220: Digest Computing
GD32F20x User Manual set 1 to start the calculation of the digest of the last block. Data Padding Example: The input message is “HAU”, which ASCII hexadecimal code is: 484155 Then the VBL bits in the HAU_CFG register is set as decimal 24 because of the valid bit length. -
Page 221: Hash Mode
GD32F20x User Manual The intermediate block computing can be started when HAU_DI is filled with another new word of the next block. The last block computing can be started when CALEN bit in the HAU_CFG register is 1. - Page 222 GD32F20x User Manual Any of interrupts can be enabled or disabled by configuring the HAU interrupt enable register HAU_INTEN. Value 1 of the register enable the interrupts. Input FIFO interrupt The input FIFO interrupt is asserted when there is enough space in the input FIFO, then DINT is asserted.
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Page 223: Register Definition
GD32F20x User Manual 11.6. Register definition HAU base address: 0x5006 0400 HAU control register (HAU_CTL) 11.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ALGM[1] Reserved Reserved DINE NWIF[3:0] ALGM[0] DATAM[1:0]... -
Page 224: Hau Data Input Register (Hau_Di)
GD32F20x User Manual ALGM[0] Algorithm selection bit 0 This bit and bit 18 of CTL are written by software to select the SHA-1, SHA-224, SHA256 or the MD5 algorithm: 00: Select SHA-1 algorithm 01: Select MD5 algorithm 10: Select SHA224 algorithm... -
Page 225: Hau Configuration Register (Hau_Cfg)
GD32F20x User Manual This register has to be accessed by word (32-bit). DI[31:16] DI[15:0] Bits Fields Descriptions 31:0 DI[31:0] Message data input When write to these registers, the current content pushed to IN FIFO and new value updates. When read, returns the current content. -
Page 226: Hau Data Output Register (Hau_Do0
GD32F20x User Manual 0x1F: Only bits [0] of the last data written to HAU_DI after data swapping are valid. Note: This bits must be configured before setting the CALEN bit. HAU data output register (HAU_DO0..7) 11.6.4. Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) The data output registers are read only registers. - Page 227 GD32F20x User Manual HAU_DO3 Address offset: 0x18 and 0x31C DO3[31:16] DO3[15:0] HAU_DO4 Address offset: 0x1C and 0x320 DO4[31:16] DO4[15:0] HAU_DO5 Address offset: 0x324 DO5[31:16] DO5[15:0] HAU_DO6 Address offset: 0x328 DO6[31:16] DO6[15:0] HAU_DO7 Address offset: 0x32C DO7[31:16]...
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Page 228: Hau Interrupt Enable Register (Hau_Inten)
GD32F20x User Manual DO7[15:0] Bits Fields Descriptions 31:0 DO0..7[31:0] message digest result of hash algorithm HAU interrupt enable register (HAU_INTEN) 11.6.5. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CCIE... - Page 229 GD32F20x User Manual 31:4 Reserved Must keep the reset value. BUSY Busy bit 0: No processing 1: Data block is in process DMAS DMA status 0: DMA is disabled (DMAE =0) and no transfer is processing 1: DMA is enabled (DMAE =1) or a transfer is processing...
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Page 230: Direct Memory Access Controller (Dma)
GD32F20x User Manual Direct memory access controller (DMA) 12.1. Overview The direct memory access (DMA) controller provides a hardware method of transferring data between peripherals and/or memory without intervention from the CPU, thereby freeing up bandwidth for other system functions. Data can be quickly moved by DMA between peripherals and memory as well as memory and memory without any CPU actions. -
Page 231: Block Diagram
GD32F20x User Manual Block diagram 12.3. Figure 12-1. Block diagram of DMA AHB slave interface Configuration … Channel 6 peri_req AHB master interface Channel 2 Master peri_req Port Channel 1 peri_req Channel 0 peri_req Memory control state & counter management... -
Page 232: Table 12-1. Dma Transfer Operations (Normal Mode)
GD32F20x User Manual The DMA transmission is disabled by clearing the CHEN bit in the DMA_CHxCTL register. If the DMA transmission is not completed when the CHEN bit is cleared, two situations may be occurred when restart this DMA channel: –... -
Page 233: Peripheral Handshake
GD32F20x User Manual Transfer size Transfer operations Source Destination Source Destination 3: Read B2[7:0] @0x2 3: Write 000000B2[31:0] @0x8 4: Read B3[7:0] @0x3 4: Write 000000B3[31:0] @0xC 1: Read B0[7:0] @0x0 1, Write 00B0[15:0] @0x0 2: Read B1[7:0] @0x1 2, Write 00B1[15:0] @0x2... -
Page 234: Arbitration
GD32F20x User Manual – Request signal asserted by peripheral to DMA controller, indicating that the peripheral is ready to transmit or receive data – Acknowledge signal responded by DMA to peripheral, indicating that the DMA controller has initiated an AHB command to access the peripheral Figure 12-2. -
Page 235: Circular Mode
GD32F20x User Manual Circular mode 12.4.5. Circular mode is implemented to handle continue peripheral requests (for example, ADC scan mode). The circular mode is enabled by setting the CMEN bit in the DMA_CHxCTL register. In circular mode, the CNT bits are automatically reloaded with the pre-programmed value and the full transfer finish flag is asserted at the end of every DMA transfer. -
Page 236: Dma Request Mapping
GD32F20x User Manual Each interrupt event has a dedicated flag bit in the DMA_INTF register, a dedicated clear bit in the DMA_INTC register, and a dedicated enable bit in the DMA_CHxCTL register. The relationship is described in the following Table 12-3. Interrupt events. -
Page 237: Figure 12-4. Dma0 Request Mapping
GD32F20x User Manual request from peripheral for each channel of DMA1. Figure 12-4. DMA0 request mapping Hardware priority ADC0 TIMER1_CH2 high Channel 0 TIMER3_CH0 SPI0_RX USART2_TX TIMER0_CH0 Channel 1 TIMER1_UP TIMER2_CH2 SPI0_TX USART2_RX TIMER0_CH1 Channel 2 TIMER2_CH3 TIMER2_UP SPI1/I2S1_RX USART0_TX... -
Page 238: Figure 12-5. Dma1 Request Mapping
GD32F20x User Manual Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 ● ● ● ● ● ● ADC0 ADC0 ● ● ● SPI/I2S SPI0_RX SPI0_TX SPI1/I2S1_RX SPI1/I2S1_TX ● USART USART2_TX USART2_RX USART0_TX USART0_RX USART1_RX USART1_TX ●... - Page 239 GD32F20x User Manual Table 12-5. DMA1 requests for each channel Peripheral Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 Channel 6 TIMER4_CH3 TIMER4_CH2 ● ● ● TIMER4 TIMER4_CH1 TIMER4_CH0 TIMER4_TG TIMER4_UP TIMER5/ TIMER5_UP/ ● ● ●...
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Page 240: Register Definition
GD32F20x User Manual Register definition 12.5. DMA0 base address: 0x4002 0000 DMA1 base address: 0x4002 0400 Interrupt flag register (DMA_INTF) 12.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved ERRIF6 HTFIF6... -
Page 241: Channel X Control Register (Dma_Chxctl)
GD32F20x User Manual This register has to be accessed by word (32-bit). Reserved ERRIFC6 HTFIFC6 FTFIFC6 GIFC6 ERRIFC5 HTFIFC5 FTFIFC5 GIFC5 ERRIFC4 HTFIFC4 FTFIFC4 GIFC4 ERRIFC3 HTFIFC3 FTFIFC3 GIFC3 ERRIFC2 HTFIFC2 FTFIFC2 GIFC2 ERRIFC1 HTFIFC1 FTFIFC1 GIFC1 ERRIFC0 HTFIFC0 FTFIFC0... - Page 242 GD32F20x User Manual 0: Disable Memory to Memory Mode 1: Enable Memory to Memory mode This bit can not be written when CHEN is ‘1’. 13:12 PRIO[1:0] Priority level Software set and cleared 00: Low 01: Medium 10: High 11: Ultra high These bits can not be written when CHEN is ‘1’.
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Page 243: Channel X Counter Register (Dma_Chxcnt)
GD32F20x User Manual Software set and cleared 0: Read from peripheral and write to memory 1: Read from memory and write to peripheral This bit can not be written when CHEN is ‘1’. ERRIE Enable bit for channel error interrupt... -
Page 244: Channel X Peripheral Base Address Register (Dma_Chxpaddr)
GD32F20x User Manual transaction can be issued whether the channel is enabled or not. Once the transmission of the channel is complete, the register can be reloaded automatically by the previously programmed value if the channel is configured in circular mode. -
Page 245: Dma Additional Configuration Register (Dma_Acfg)
GD32F20x User Manual ignored. Access is automatically aligned to a half word address. When MWIDTH in the DMA_CHxCTL register is 10 (32-bit), the two LSBs of these bits are ignored. Access is automatically aligned to a word address. DMA additional configuration register (DMA_ACFG) 12.5.7. -
Page 246: Debug (Dbg)
13.1. Overview The GD32F20x series provide a large variety of debug, trace and test features. They are implemented with a standard configuration of the ARM CoreSightTM module toget her with a daisy chained standard TAP controller. Debug and trace functions are integ rated into the ARM Cortex-M3. -
Page 247: Jtag Daisy Chained Structure
GD32F20x User Manual S, SWCLK multiplexed with JTCK. The JTDO is also used as Trace async data outp ut (TRACESWO) when async trace enabled. Table 13-1. Pin assignment Debug interface PA15 JTDI PA14 JTCK/SWCLK PA13 JTMS/SWDIO NJTRST JTDO By default, 5-pin standard JTAG debug mode is chosen after reset. Users can also use JTAG function without NJTRST pin, then the PB4 can be used to other GPIO functions. -
Page 248: Debug Hold Function Overview
GD32F20x User Manual 13.3. Debug hold function overview Debug support for power saving mode 13.3.1. When STB_HOLD bit in DBG control register (DBG_CTL) is set and entering the stan dby mode, the clock of AHB bus and system clock are provided by CK_IRC8M, and the debugger can debug in standby mode. -
Page 249: Register Definition
GD32F20x User Manual 13.4. Register definition DBG base address: 0xE004 2000 ID code register (DBG_ID) 13.4.1. Address offset: 0x00 Read only This register has to be accessed by word(32-bit). ID_CODE[31:16] ID_CODE[15:0] Bits Fields Descriptions 31:0 ID_CODE[31:0] DBG ID code register These bits read by software. - Page 250 GD32F20x User Manual 0: no effect 1: hold the TIMER10 counter for debug when core halted TIMER9_HOLD TIMER9 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER9 counter for debug when core halted...
- Page 251 GD32F20x User Manual 1: hold the TIMER4 counter for debug when core halted TIMER7_HOLD TIMER7 hold bit This bit is set and reset by software 0: no effect 1: hold the TIMER7 counter for debug when core halted I2C1_HOLD I2C1 hold bit...
- Page 252 GD32F20x User Manual 0: no effect 1: hold the FWDGT counter clock for debug when core halted TRACE_MODE[1:0] Trace pin allocation mode This bit is set and reset by software 00: Trace pin used in asynchronous mode 01: Trace pin used in synchronous mode and the data length is 1...
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Page 253: Analog-To-Digital Converter (Adc)
GD32F20x User Manual Analog-to-digital converter (ADC) 14.1. Overview A 12-bit successive approximation analog-to-digital converter module(ADC) is integrated on the MCU chip, which can sample analog signals from 16 external channels and 2 internal channels. The 18 ADC sampling channels all support a variety of operation modes. After... -
Page 254: Pins And Internal Signals
GD32F20x User Manual – Oversampling ratio adjustable from 2 to 256x. – Programmable data shift up to 8-bit. Module supply requirements: 2.6V to 3.6V, and typical power supply voltage is 3.3V. ≤V ≤V Channel input range: V REFN REFP. -
Page 255: Function Overview
GD32F20x User Manual 14.3. Function overview Figure 14-1. ADC module block diagram Trig select Routine channels Interrupt Interrupt Channel Management generator watchdog event Analog watchdog ADC_IN0 ADC_IN1 GPIO Over Routine data registers ADC_IN15 SAR ADC （16 bits） sampler SENSE REFINT... -
Page 256: Adc Clock
GD32F20x User Manual Set RSTCLB (optional). Set CLB=1. Wait until CLB=0. ADC clock 14.3.2. The CK_ADC clock is synchronous with the AHB and APB2 clock and provided by the clock controller. The maximum frequency is 28MHz. ADC clock can be divided and configured by RCU controller. -
Page 257: Figure 14-3. Continuous Operation Mode
GD32F20x User Manual Make sure the DISRC, SM in the ADC_CTL0 register and CTN bit in the ADC_CTL1 register are reset. Configure RSQ0 with the analog channel number. Configure ADC_SAMPTx register. Configure ETERC and ETSRC bits in the ADC_CTL1 register if in need. -
Page 258: Figure 14-4. Scan Operation Mode, Continuous Disable
GD32F20x User Manual Scan operation mode The scan operation mode will be enabled when SM bit in the ADC_CTL0 register is set. In this mode, the ADC performs conversion on all channels with a specific routine sequence specified in the ADC_RSQ0~ADC_RSQ2 registers. When the ADCON has been set high, the ADC samples and converts specified channels one by one in the routine sequence till the end of the sequence, once the corresponding software trigger or external trigger is active. -
Page 259: Conversion Result Threshold Monitor Function
GD32F20x User Manual the next n channels configured in the ADC_RSQ0~ADC_RSQ2 registers until all the channels of routine sequence channels are done. The EOC will be set after every circle of the routine sequence. An interrupt will be generated if the EOCIE bit is set. -
Page 260: Sample Time Configuration
GD32F20x User Manual Figure 14-7. Data storage mode of 12-bit resolution Routine sequence data D11 D10 DAL=0 Routine sequence data D11 D10 DAL=1 Figure 14-8. Data storage mode of 10-bit resolution Routine sequence data DAL=0 Routine sequence data DAL=1 Figure 14-9. Data storage mode of 8-bit resolution... -
Page 261: External Trigger Configuration
GD32F20x User Manual External trigger configuration 14.3.9. The conversion of routine sequence can be triggered by rising edge of external trigger inputs. The external trigger source of routine sequence is controlled by the ETSRC[2:0] bits in the ADC_CTL1 register. Table 14-3. External trigger source for ADC0 and ADC1... -
Page 262: Programmable Resolution (Dres)
GD32F20x User Manual be used to measure the ambient temperature of the device. The sensor output voltage can be converted into a digital value by ADC. The sampling time for the temperature sensor is recommended to be set to at least µs. -
Page 263: On-Chip Hardware Oversampling
GD32F20x User Manual 232 ns 286 ns On-chip hardware oversampling 14.3.13. The on-chip hardware oversampling circuit performs data preprocessing to offload the CPU. It can handle multiple conversions and average them into a single data with increased data width, up to 16-bit. The on-chip hardware oversampling circuit is enabled by OVSEN bit in the ADC_OVSAMPCTL register. -
Page 264: Adc Sync Mode
GD32F20x User Manual Figure 14-12. Numerical example with 5-bits shift and rounding Raw 20-bit data Final result after 5-bit shift and rounding to nearest Table 14-6. Maximum output results vs N and M Grayed values indicates truncation below gives the data format for the various N and M combination, for a raw conversion data equal to 0xFFF. -
Page 265: Free Mode
GD32F20x User Manual ADC1 must be configured as triggered by the software. However, the external trigger must be enabled for ADC0 and ADC1. The following modes can be configured in Table 14-7. ADC sync mode table. Table 14-7. ADC sync mode table... -
Page 266: Routine Follow-Up Fast Mode
GD32F20x User Manual from the ADC0 routine sequence (configured by the ETSRC[2:0] bits in the ADC_CTL1 register) , and ADC1 routine sequence is configured as software trigger mode. At the end of conversion event on ADC0 or ADC1, an EOC interrupt is generated (if enabled on one of the two ADC interrupt) when the ADC0/ADC1 routine channels are all converted. -
Page 267: Routine Follow-Up Slow Mode
GD32F20x User Manual are set) Routine follow-up slow mode 14.4.4. The routine follow-up slow mode is applicable to sample the same channel of two ADCs. The source of external trigger comes from the ADC0 routine channel (selected by the ETSRC[2:0] bits in the ADC_CTL1 register).. -
Page 268: Adc Interrupts
GD32F20x User Manual 14.5. ADC interrupts The interrupt can be produced on one of the events: End of conversion for routine sequence. The analog watchdog event. The interrupts of ADC0 and ADC1 are mapped into the same interrupt vector. The interrupts... -
Page 269: Register Definition
GD32F20x User Manual 14.6. Register definition ADC0 base address: 0x4001 2400 ADC1 base address: 0x4001 2800 ADC2 base address: 0x4001 3C00 Status register (ADC_STAT) 14.6.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). - Page 270 GD32F20x User Manual This register has to be accessed by word(32-bit). Reserved RWDEN Reserved SYNCM[3:0] DISNUM[2:0] Reserved DISRC Reserved WDSC Reserved WDEIE EOCIE WDCHSEL[4:0] Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. RWDEN Routine channel analog watchdog enable...
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Page 271: Control Register 1 (Adc_Ctl1)
GD32F20x User Manual 0: Interrupt disable 1: Interrupt enable EOCIE Interrupt enable for EOC 0: Interrupt disable 1: Interrupt enable WDCHSEL[4:0] Analog watchdog channel select 00000: ADC channel0 00001: ADC channel1 00010: ADC channel2 00011: ADC channel 3 00100: ADC channel 4... - Page 272 GD32F20x User Manual Bits Fields Descriptions 31:24 Reserved Must be kept at reset value. TSVREN Channel 16 and 17 enable of ADC0. 0: Channel 16 and 17 of ADC0 disable 1: Channel 16 and 17 of ADC0 enable SWRCST Software start conversion of routine sequence .
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Page 273: Sample Time Register 0 (Adc_Sampt0)
GD32F20x User Manual 1: DMA request enable Reserved Must be kept at reset value. RSTCLB Reset calibration This bit is set by software and cleared by hardware after the calibration registers are initialized. 0: Calibration register initialize done. 1: Initialize calibration register start... -
Page 274: Sample Time Register 1 (Adc_Sampt1)
GD32F20x User Manual 11:9 SPT13[2:0] refer to SPT10[2:0] description SPT12[2:0] refer to SPT10[2:0] description SPT11[2:0] refer to SPT10[2:0] description SPT10[2:0] Channel sample time 000: channel sampling time is 1.5 cycles 001: channel sampling time is 7.5 cycles 010: channel sampling time is 13.5 cycles 011: channel sampling time is 28.5 cycles... -
Page 275: Watchdog High Threshold Register (Adc_Wdht)
GD32F20x User Manual Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:27 SPT9[2:0] refer to SPT0[2:0] description 26:24 SPT8[2:0] refer to SPT0[2:0] description 23:21 SPT7[2:0] refer to SPT0[2:0] description 20:18 SPT6[2:0] refer to SPT0[2:0] description 17:15 SPT5[2:0]... -
Page 276: Watchdog Low Threshold Register (Adc_Wdlt)
GD32F20x User Manual These bits define the high threshold for the analog watchdog. Watchdog low threshold register (ADC_WDLT) 14.6.7. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved WDLT[11:0] Bits Fields Descriptions... -
Page 277: Routine Sequence Register 1 (Adc_Rsq1)
GD32F20x User Manual RSQ12[4:0] refer to RSQ0[4:0] description Routine sequence register 1 (ADC_RSQ1) 14.6.9. Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved RSQ11[4:0] RSQ10[4:0] RSQ9[4:1] RSQ9[0] RSQ8[4:0] RSQ7[4:0] RSQ6[4:0] Bits Fields Descriptions... -
Page 278: Routine Data Register (Adc_Rdata)
GD32F20x User Manual 29:25 RSQ5[4:0] refer to RSQ0[4:0] description 24:20 RSQ4[4:0] refer to RSQ0[4:0] description 19:15 RSQ3[4:0] refer to RSQ0[4:0] description 14:10 RSQ2[4:0] refer to RSQ0[4:0] description RSQ1[4:0] refer to RSQ0[4:0] description RSQ0[4:0] The channel number (0..17) is written to these bits to select a channel as the nth conversion in the routine sequence. - Page 279 GD32F20x User Manual Bits Fields Descriptions 31:14 Reserved Must be kept at reset value. 13:12 DRES[1:0] ADC resolution 00: 12bit 01: 10bit 10: 8bit 11: 6bit 11:10 Reserved Must be kept at reset value. TOVS Triggered Oversampling This bit is set and cleared by software.
- Page 280 GD32F20x User Manual Reserved Must be kept at reset value. OVSEN Oversampler Enable This bit is set and cleared by software. 0: Oversampler disabled 1: Oversampler enabled Note: The software allows this bit to be written only when ADCON = 0 (this ensures...
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Page 281: Digital-To-Analog Converter (Dac)
GD32F20x User Manual Digital-to-analog converter (DAC) 15.1. Overview The Digital-to-analog converter converts 12-bit digital data to a voltage on the external pins. The digital data can be configured in 8-bit or 12-bit mode, left-aligned or right-aligned mode. DMA can be used to update the digital data on external triggers. The output voltage can be optionally buffered for higher drive capability. -
Page 282: Function Overview
GD32F20x User Manual description gives the pin description. Figure 15-1. DAC block diagram DAC control register DTSELx[2:0] DBOFFx TIMER5_TRGO TIMER2_TRGO TIMER6_TRGO TIMER4_TRGO TIMER1_TRGO TIMER3_TRGO EXTI_9 Buff SWTRx DAC_OUTx Control logic 12-bit 12-bit 12-bit Table 15-1. DAC I/O description Name Description... -
Page 283: Dac Data Configuration
GD32F20x User Manual The output buffer, which is turned on by default, can be turned off by setting the DBOFFx bits in the DAC_CTL register. DAC data configuration 15.3.3. The 12-bit DAC holding data (DACx_DH) can be configured by writing any one of the DACx_R12DH, DACx_L12DH and DACx_R8DH registers. -
Page 284: Dac Output Calculate
GD32F20x User Manual (DWBWx) bits in the DAC_CTL register. There is a Linear Feedback Shift Register (LFSR) in the DAC control logic. In the LFSR noise mode, the LFSR noise signal is added to the DACx_DH value. When the configured DAC noise wave bit width is less than 12, the noise signal equals to the LSB DWBWx bits of the LFSR register. -
Page 285: Dma Function
GD32F20x User Manual DMA function 15.3.8. When the external trigger is enabled, the DMA request is enabled by setting the DDMAENx bits of the DAC_CTL register. When an external hardware trigger (not a software trigger) occurs ,A DMA request will be generated by DAC. -
Page 286: Register Definition
GD32F20x User Manual 15.4. Register definition DAC base address: 0x4000 7400 Control register (DAC_CTL) 15.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DWBW1[3:0] DWM1[1:0] DTSEL1[2:0] DTEN1 DBOFF1 DEN1 DDMAEN1 Reserved DDMAEN0... - Page 287 GD32F20x User Manual 01: LFSR noise mode 1x: Triangle noise mode 21:19 DTSEL1[2:0] DAC1 trigger selection These bits select the external trigger of DAC1 when DTEN1=1. 000: Timer 5 TRGO 001: Timer 2 TRGO 010: Timer 6 TRGO 011: Timer 4 TRGO...
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Page 288: Software Trigger Register (Dac_Swt)
GD32F20x User Manual 1010: The bit width of the wave signal is 11 ≥1011: The bit width of the wave signal is 12 DWM0[1:0] DAC0 noise wave mode These bits specify the mode selection of the noise wave signal of DAC0 when external trigger of DAC0 is enabled (DTEN0=1). -
Page 289: Dac0 12-Bit Right-Aligned Data Holding Register (Dac0_R12Dh)
GD32F20x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SWTR1 DAC1 software trigger, cleared by hardware 0: Software trigger disabled 1: Software trigger enabled SWTR0 DAC0 software trigger, cleared by hardware 0: Software trigger disabled... -
Page 290: Dac0 8-Bit Right-Aligned Data Holding Register (Dac0_R8Dh)
GD32F20x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:4 DAC0_DH[11:0] DAC0 12-bit left-aligned data These bits specify the data that is to be converted by DAC0. Reserved Must be kept at reset value. DAC0 8-bit right-aligned data holding register (DAC0_R8DH) 15.4.5. -
Page 291: Dac1 12-Bit Left-Aligned Data Holding Register (Dac1_L12Dh)
GD32F20x User Manual DAC1 12-bit left-aligned data holding register (DAC1_L12DH) 15.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DH[11:0] Reserved Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. -
Page 292: Dac Concurrent Mode 12-Bit Left-Aligned Data Holding Register (Dacc_L12Dh)
GD32F20x User Manual This register has to be accessed by word(32-bit) Reserved DAC1_DH[11:0] Reserved DAC0_DH[11:0] Bits Fields Descriptions 31:28 Reserved Must be kept at reset value. 27:16 DAC1_DH[11:0] DAC1 12-bit right-aligned data These bits specify the data that is to be converted by DAC1. -
Page 293: Dac Concurrent Mode 8-Bit Right-Aligned Data Holding Register (Dacc_R8Dh)
GD32F20x User Manual DAC concurrent mode 8-bit right-aligned data holding register 15.4.11. (DACC_R8DH) Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved DAC1_DH [7:0] DAC0_DH [7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. -
Page 294: Dac1 Data Output Register (Dac1_Do)
GD32F20x User Manual DAC1 data output register (DAC1_DO) 15.4.13. Address offset: 0x30 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved DAC1_DO [11:0] Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0... -
Page 295: Watchdog Timer (Wdgt)
GD32F20x User Manual Watchdog timer (WDGT) The watchdog timer (WDGT) is a hardware timing circuitry that can be used to detect system failures due to software malfunctions. There are two watchdog timer peripherals in the chip: free watchdog timer (FWDGT) and window watchdog timer (WWDGT). They offer a combination of a high safety level, flexibility of use and timing accuracy. -
Page 296: Table 16-1. Min/Max Fwdgt Timeout Period At 40 Khz (Irc40K)
GD32F20x User Manual Figure 16-1. Free watchdog block diagram The free watchdog is enabled by writing the value (0xCCCC) in the control register (FWDGT_CTL), and the counter starts counting down. When the counter reaches the value 0x000, a reset is generated. - Page 297 GD32F20x User Manual Min timeout (ms) Max timeout (ms) Prescaler divider PSC[2:0] bits RLD[11:0]=0x000 RLD[11:0]=0xFFF 1 / 256 110 or 111 0.025 26208.025 The FWDGT timeout can be more accurate by calibrating the IRC40K. Note: After the execution of watchdog reload operation, if the MCU needs enter the deepsleep / standby mode immediately, more than 3 IRC40K clock intervals must be inserted in the middle of reload and deepsleep / standby mode commands by software setting.
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Page 298: Register Definition
GD32F20x User Manual Register definition 16.1.4. FWDGT start address: 0x4000 3000 Control register (FWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit) access. Reserved CMD[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. - Page 299 GD32F20x User Manual 000: 1 / 4 001: 1 / 8 010: 1 / 16 011: 1 / 32 100: 1 / 64 101: 1 / 128 110: 1 / 256 111: 1 / 256 If several prescaler values are used by the application, it is mandatory to wait until PUD bit is reset before changing the prescaler value.
- Page 300 GD32F20x User Manual This register can be accessed by half-word(16-bit) or word(32-bit) access. Reserved Reserved Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. Free watchdog timer counter reload value update. During a write operation to FWDGT_RLD register, this bit is set and the value read from FWDGT_RLD register is invalid.
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Page 301: Window Watchdog Timer (Wwdgt)
GD32F20x User Manual 16.2. Window watchdog timer (WWDGT) Overview 16.2.1. The window watchdog timer (WWDGT) is used to detect system failures due to software malfunctions. After the window watchdog timer starts, the value of downcounter reduces progressively. The watchdog timer causes a reset when the counter reached 0x3F (the CNT[6] bit becomes cleared). -
Page 302: Figure 16-3. Window Watchdog Timing Diagram
GD32F20x User Manual The window watchdog timer is always disabled after power on reset. The software starts the watchdog by setting the WDGTEN bit in the WWDGT_CTL register. Whenever window watchdog timer is enabled, the counter counts down all the time, the configured value of the counter should be greater than 0x3F (it implies that the CNT[6] bit should be set). -
Page 303: Table 16-2. Min/Max Timeout Value At 60 Mhz
GD32F20x User Manual Table 16-2. Min/max timeout value at 60 MHz (f PCLK1 Min timeout value Max timeout value Prescaler divider PSC[1:0] CNT[6:0] =0x40 CNT[6:0]=0x7F 68.2 μs 1 / 1 4.3ms 136.4 μs 1 / 2 8.6 ms 272.8μs 1 / 4 17.2 ms... -
Page 304: Register Definition
GD32F20x User Manual Register definition 16.2.4. WWDGT start address: 0x4000 2C00 Control register (WWDGT_CTL) Address offset: 0x00 Reset value: 0x0000 007F This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved WDGTEN CNT[6:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. - Page 305 GD32F20x User Manual bit of the RCU module. A write operation of ‘0’ has no effect. PSC[1:0] Prescaler. The time base of the watchdog timer counter 00: (PCLK1 / 4096) / 1 01: (PCLK1 / 4096) / 2 10: (PCLK1 / 4096) / 4...
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Page 306: Real-Time Clock(Rtc)
GD32F20x User Manual Real-time Clock(RTC) 17.1. Overview The RTC is usually used as a clock-calendar. The RTC circuits are located in two power supply domains, backup domain and VDD domain. The ones in the Backup Domain consist of a 32-bit up-counter, an alarm, a prescaler, a divider and the RTC clock configuration register. -
Page 307: Rtc Reset
GD32F20x User Manual the RTC will generate an alarm interrupt when the system time equals to the alarm time (stored in the RTC_ALRMH/L register). Figure 17-1. Block diagram of RTC A P B 1 B U S P C L K 1... -
Page 308: Rtc Flag Assertion
GD32F20x User Manual registers’ value can be set only when the peripheral enter configuration mode. And the CMF bit in the RTC_CTL register is used to indicate the configuration mode status. The write operation executes when the peripheral exit configuration mode, and it takes at least three RTCCLK cycles to complete. - Page 309 GD32F20x User Manual RTC second and overflow waveform example (RTC_PSC= 3) Figure 17-3.
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Page 310: Register Definition
GD32F20x User Manual 17.4. Register definition RTC start address: 0x4000 2800 RTC interrupt enable register(RTC_INTEN) 17.4.1. Address offset: 0x00 Reset value: 0x0000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved Reserved OVIE ALRMIE SCIE Bits Fields... -
Page 311: Rtc Prescaler High Register (Rtc_Psch)
GD32F20x User Manual Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. LWOFF Last write operation finished flag 0: Last write operation on RTC registers did not finished. 1: Last write operation on RTC registers finished. Configuration mode flag 0: Exit configuration mode. -
Page 312: Rtc Prescaler Low Register (Rtc_Pscl)
GD32F20x User Manual 31:4 Reserved Must be kept at reset value PSC[19:16] RTC prescaler value high RTC prescaler low register (RTC_PSCL) 17.4.4. Address offset: 0x0C Reset value: 0x8000 This register can be accessed by half-word (16-bit) or word (32-bit) Reserved... -
Page 313: Rtc Counter High Register(Rtc_Cnth)
GD32F20x User Manual Reserved DIV[15:0] Bits Fields Descriptions Reserved 31:16 Must be kept at reset value 15:0 DIV[15:0] RTC divider value low The RTC divider register is reloaded by hardware when the RTC prescaler or RTC counter register updated. RTC counter high register(RTC_CNTH) 17.4.7. -
Page 314: Rtc Alarm High Register(Rtc_Alrmh)
GD32F20x User Manual 15:0 CNT[15:0] RTC counter value low RTC alarm high register(RTC_ALRMH) 17.4.9. Address offset: 0x20 Reset value: 0xFFFF This register can be accessed by half-word (16-bit) or word (32-bit) Reserved ALRM[31:16] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value... -
Page 315: Timer
GD32F20x User Manual TIMER Table 18-1. Timers (TIMERx) are divided into five sorts TIMER TIMER0/7 TIMER1/2/3/4 TIMER8/11 TIMER9/10/12/13 TIMER5/6 Advanced General-L0 General-L1 General-L2 Basic TYPE Prescaler 16-bit 16-bit 16-bit 16-bit 16-bit Counter 16-bit 16-bit 16-bit 16-bit 16-bit UP,DOWN, UP,DOWN, UP,DOWN,... -
Page 316: Advanced Timer (Timerx, X=0, 7)
GD32F20x User Manual 18.1. Advanced timer (TIMERx, x=0, 7) Overview 18.1.1. The advanced timer module (Timer0 & Timer7) is a four-channel timer that supports both input capture and output compare. They can generate PWM signals to control motor or be used for power management applications. - Page 317 GD32F20x User Manual the advanced timer. Figure 18-1. Advanced timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler &Edge Detector CH2_IN CH3_IN ITI0 ITI1 ITI2 ITI3 TIMERx_CHxCV CK_TIMER Counter External Trigger Input logic Trigger processor PSC_CLK DMA REQ/ACK...
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Page 318: Figure 18-2. Timing Chart Of Internal Clock Divided By 1
GD32F20x User Manual Figure 18-2. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of... -
Page 319: Figure 18-3. Timing Chart Of Psc Value Change From 0 To 2
GD32F20x User Manual Figure 18-3. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. -
Page 320: Figure 18-5. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32F20x User Manual behavior for different clock prescaler factor when TIMERx_CAR=0x99. Figure 18-4. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG... -
Page 321: Figure 18-6. Timing Chart Of Down Counting Mode, Psc=0/2
GD32F20x User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter the counter will start counting down from the counter-reload value again and an underflow event will be generated. -
Page 322: Figure 18-7. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32F20x User Manual Figure 18-7. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118... -
Page 323: Figure 18-8. Timing Chart Of Center-Aligned Counting Mode
GD32F20x User Manual reload register, prescaler register) are updated. Figure 18-8. Timing chart of center-aligned counting mode shows some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 18-8. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow... -
Page 324: Figure 18-9. Repetition Counter Timing Chart Of Center-Aligned Counting Mode
GD32F20x User Manual The new written CREP value will not take effect until the next update event. When the value of CREP is odd, and the counter is counting in center-aligned mode, the update event is generated (on overflow or underflow) depending on when the written CREP value takes effect. -
Page 325: Figure 18-11. Repetition Counter Timing Chart Of Down Counting Mode
GD32F20x User Manual Figure 18-11. Repetition counter timing chart of down counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow TIMERx_CREP = 0x0 UPIF TIMERx_CREP = 0x1 UPIF TIMERx_CREP = 0x2 UPIF Input capture and output compare channels The advanced timer has four independent channels which can be used as capture inputs or compare match outputs. -
Page 326: Figure 18-12. Channel Input Capture Principle
GD32F20x User Manual Figure 18-12. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register Prescaler Prescaler （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_I NT Capture INT From Other Channal... -
Page 327: Figure 18-13. Channel Output Compare Principle (With Complementary Output, X=0,1,2)
GD32F20x User Manual interrupt and DMA request will be asserted based on the configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: if you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. -
Page 328: Figure 18-15. Output-Compare In Three Modes
GD32F20x User Manual (the output of CHx_O is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(high) level; If the output of OxCPRE is inactive(low) level, the output of CHx_O is active(low) level. 2) Configure CHxNP=0 (the active level of CHx_ON is low, contrary to OxCPRE), CHxNE=1 (the output of CHx_ON is enabled), If the output of OxCPRE is active(high) level, the output of CHx_O is active(low) level;... - Page 329 GD32F20x User Manual Figure 18-15. Output-compare in three modes CNT_CLK CNT_REG Overflow match toggle OxCPRE match set OxCPRE match clear OxCPRE Output PWM function In the output PWM function (by setting the CHxCOMCTL bits to 3’b110 (PWM mode0) or to 3’b 111(PWM mode1), the channel can generate PWM waveform according to the...
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Page 330: Figure 18-16. Timing Chart Of Eapwm
GD32F20x User Manual Figure 18-16. Timing chart of EAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CHxIF Figure 18-17. Timing chart of CAPWM CHxVAL PWM MODE0 Cx OUT PWM MODE1 Cx OUT Interrupt signal CAM=2'b01 down only... - Page 331 GD32F20x User Manual setting the CHxCOMCTL field to 0x02 or signal toggle by setting the CHxCOMCTL field to 0x03 when the counter value matches the content of the TIMERx_CHxCV register. The PWM mode 0 and PWM mode 1 outputs are also another kind of OxCPRE output which is setup by setting the CHxCOMCTL field to 0x06/0x07.
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Page 332: Table 18-2. Complementary Outputs Controlled By Parameters
GD32F20x User Manual Table 18-2. Complementary outputs controlled by parameters Complementary Parameters Output Status POEN ROS CHxEN CHxNEN CHx_O CHx_ON CHx_O / CHx_ON = LOW CHx_O / CHx_ON output disable. CHx_O = CHxP CHx_ON = CHxNP CHx_O/CHx_ON output disable. If clock is enable:... -
Page 333: Figure 18-18. Channel Output Complementary Pwm With Dead-Time Insertion
GD32F20x User Manual The dead time delay insertion ensures that no two complementary signals drive the active state at the same time. When the channel (x) match (TIMERx counter = CHxVAL) occurs, OxCPRE will be toggled Figure 18-18. Channel output because under PWM0 mode. -
Page 334: Figure 18-19. Output Behavior In Response To A Break (The Break High Active)
GD32F20x User Manual state, and then the dead-time generator is reactivated in order to drive the outputs with the level programmed in the ISOx and ISOxN bits after a dead-time. When a break occurs, the BRKIF bit in the TIMERx_INTF register is set. If BRKIE is 1, an interrupt generated. -
Page 335: Figure 18-20. Counter Behavior With Ci0Fe0 Polarity Non-Inverted In Mode 2
GD32F20x User Manual Table 18-3. Counting direction in different quadrature decoder mode CI0FE0 CI1FE1 Counting mode Level Fallin Rising Rising Falling CI1FE1= Down Quadrature decoder mode 0 SMC[2:0]=3’b000 CI1FE1= Down CI0FE0= Down Quadrature decoder mode 1 SMC [2:0]=3’b010 CI0FE0= Down... -
Page 336: Figure 18-22. Hall Sensor Is Used To Bldc Motor
GD32F20x User Manual Figure 18-22. Hall sensor is used to BLDC motor show how to connect. And we can see we need two timers. First TIMER_in (Advanced/GeneralL0 TIMER) should accept three HALL sensor signals. Each of the three input of HALL sensors provides a pulse that applied to an input capture pin, can then be analyzed and both speed and position can be deduced. -
Page 337: Figure 18-23. Hall Sensor Timing Between Two Timers
GD32F20x User Manual Figure 18-23. Hall sensor timing between two timers Advanced/General L0 TIMER_in under input capture mode CH0_INPUT CH1_INPUT CH2_INPUT CI0(OXR) Counter CH0VAL Advanced TIMER_out under output compare mode(PWM with Dead -time) CH0_O CH0_ON CH1_O CH1_ON CH2_O CH2_ON Master-slave management... -
Page 338: Figure 18-24. Restart Mode
GD32F20x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 101: CI0FE0 If ETIFP is selected as prescaler can be 110: CI1FE1 the trigger source, used. 111: ETIFP configure the ETP for For the ETIFP, filter polarity selection and can be used by inversion. -
Page 339: Figure 18-26. Event Mode
GD32F20x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Event mode ETPSC = 1, ETI is The counter will start ETP = 0, the polarity TRGS[2:0] =3’b111 divided by 2. to count when a rising of ETI does not ETIFP is selected. -
Page 340: Figure 18-28. Timer0 Master/Slave Mode Timer Example
GD32F20x User Manual Figure 18-27. Single pulse mode, TIMERx_CHxCV = 4, TIMERx_CAR=99 TIMER_CK (PSC_CLK) Under SPM, counter stop CNT_REG OxCPRE Timers interconnection Timer can be configured as interconnection, that is, one timer which operate in the master mode outputs TRGO signal to control another timer which operate in the slave mode, TRGO include reset evevt, start evevt, update evevt, capture/compare pulse evevt, compare evevt. -
Page 341: Table 18-5. Input Trigger Of Timer0 And Timer7
GD32F20x User Manual Figure 18-28. Timer0 master/slave mode timer example TRGS TIMER0 TIMER 4 Master ITI0 TRGO Prescaler Counter mode control TIMER 1 Master TRGO ITI1 Prescaler Counter mode control TIMER 2 Master ITI2 TRGO Prescaler Counter mode control Trigger... -
Page 342: Figure 18-29. Triggering Timer0 With Enable Signal Of Timer2
GD32F20x User Manual (MMC=3’b010 in the TIMER2_CTL1 register). Then timer2 drives a periodic signal on each counter overflow. 2. Configure the Timer2 period (TIMER2_CAR registers). 3. Select the Timer0 input trigger source from Timer2 (TRGS=3’b010 in the TIMERx_SMCFG register). 4. Configure Timer0 in external clock mode 0 (SMC=3’b111 in TIMERx_SMCFG register). -
Page 343: Figure 18-30. Triggering Timer0 And Timer2 With Timer2'S Ci0 Input
GD32F20x User Manual triggered by its CI0 input rises edge. To ensure 2 timers start synchronously, Timer2 must be configured in Master/Slave mode. Do as follow: 1. Configure Timer2 in slave mode to get the input trigger from CI0 (TRGS=3’b100 in the TIMER2_SMCFG register). - Page 344 GD32F20x User Manual TIMERx_DMATC is not 0, such as 3( 4 transfers), then timer will send 3 more requests to DMA, and DMA will access timer’s registers DMATA+0x4, DMATA+0x8, DMATA+0xc at the next 3 accesses to TIMERx_DMATB. In one word, one time DMA internal interrupt event assert, DMATC+1 times request will be send by TIMERx.
- Page 345 GD32F20x User Manual Register definition 18.1.5. TIMER0 base address: 0x4001 2C00 TIMER7 base address: 0x4001 3400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved CKDIV[1:0] ARSE...
- Page 346 GD32F20x User Manual TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only.
- Page 347 GD32F20x User Manual Reserved Reserved ISO3 ISO2N ISO2 ISO1N ISO1 ISO0N ISO0 TI0S MMC[2:0] DMAS CCUC Reserved CCSE Bits Fields Descriptions 31:15 Reserved Must be kept at reset value ISO3 Idle state of channel 3 output Refer to ISO0 bit...
- Page 348 GD32F20x User Manual 001: Enable. When a conter start event occurs, a TRGO trigger signal is output. The counter start source : CEN control bit is set The trigger input in pause mode is high 010: When an update event occurs, a TRGO trigger signal is output. The update source depends on UPDIS bit and UPS bit.
- Page 349 GD32F20x User Manual Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value External trigger polarity This bit specifies the polarity of ETI signal 0: ETI is active at rising edge or high level .
- Page 350 GD32F20x User Manual EXTFC[3:0] Times SAMP 4’b0000 Filter disabled. 4’b0001 4’b0010 CK_TIMER 4’b0011 4’b0100 DTS_CK 4’b0101 4’b0110 DTS_CK 4’b0111 4’b1000 DTS_CK 4’b1001 4’b1010 4’b1011 DTS_CK 4’b1100 4’b1101 4’b1110 DTS_CK 4’b1111 Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time.
- Page 351 GD32F20x User Manual 010: Quadrature decoder mode 1.The counter counts on CI1FE1 edge, while the direction depends on CI0FE0 level. 011: Quadrature decoder mode 2.The counter counts on both CI0FE0 and CI1FE1 edge, while the direction depends on each other.
- Page 352 GD32F20x User Manual 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled BRKIE Break interrupt enable 0: disabled 1: enabled TRGIE Trigger interrupt enable 0: disabled 1: enabled...
- Page 353 GD32F20x User Manual Reserved Reserved CH3OF CH2OF CH1OF CH0OF Reserved BRKIF TRGIF CMTIF CH3IF CH2IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value.
- Page 354 GD32F20x User Manual Refer to CH0IF description Channel 2 ‘s capture/compare interrupt flag CH2IF Refer to CH0IF description Channel 1 ‘s capture/compare interrupt flag CH1IF Refer to CH0IF description Channel 0 ‘s capture/compare interrupt flag CH0IF This flag is set by hardware and cleared by software. When channel 0 is in input mode, this flag is set when a capture event occurs.
- Page 355 GD32F20x User Manual can occur if enabled. 0: No generate a trigger event 1: Generate a trigger event CMTG Channel commutation event generation This bit is set by software and cleared by hardware automatically. When this bit is set, channel’s capture/compare control registers (CHxEN, CHxNEN and CHxCOMCTL bits) are updated based on the value of CCSE (in the TIMERx_CTL1).
- Page 356 GD32F20x User Manual Reserved CH1COM CH1COM CH1COM CH0COM CH0COM CH0COM CH1COMCTL[2:0] CH0COMCTL[2:0] CH1MS[1:0] CH0MS[1:0] CH1CAPFLT[3:0] CH1CAPPSC[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description...
- Page 357 GD32F20x User Manual equals to the output compare register TIMERx_CH0CV. 010: Clear the channel output. O0CPRE signal is forced low when the counter is equals to the output compare register TIMERx_CH0CV. 011: Toggle on match. O0CPRE toggles when the counter is equals to the output compare register TIMERx_CH0CV.
- Page 358 GD32F20x User Manual 11: Channel 0 is programmed as input mode, IS0 is connected to ITS Note: When CH0MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register. Input capture mode: Bits Fields Descriptions...
- Page 359 GD32F20x User Manual 00: Prescaler disable, input capture occurs on every channel input edge 01: The input capture occurs on every 2 channel input edges 10: The input capture occurs on every 4 channel input edges 11: The input capture occurs on every 8 channel input edges...
- Page 360 GD32F20x User Manual Note: When CH3MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register. CH2COMCEN Channel 2 output compare clear enable. When this bit is set, if the ETIFP signal is detected as high level, the O2CPRE signal will be cleared.
- Page 361 GD32F20x User Manual CH2COMFEN Channel 2 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM1 or PWM2 mode.
- Page 362 GD32F20x User Manual 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH2CAPPSC[1:0] Channel 2 input capture prescaler This bit-field specifies the factor of the prescaler on channel 2 input. The prescaler is reset when CH2EN bit in TIMERx_CHCTL2 register is clear.
- Page 363 GD32F20x User Manual CH2NP Channel 2 complementary output polarity Refer to CH0NP description CH2NEN Channel 2 complementary output enable Refer to CH0NEN description CH2P Channel 2 capture/compare function polarity Refer to CH0P description CH2EN Channel 2 capture/compare function enable Refer to CH0EN description...
- Page 364 GD32F20x User Manual 11 or 10. CH0EN Channel 0 capture/compare function enable When channel 0 is configured in output mode, setting this bit enables CH0_O signal in active state. When channel 0 is configured in input mode, setting this bit enables the capture event in channel0.
- Page 365 GD32F20x User Manual 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
- Page 366 GD32F20x User Manual This bit-filed specifies the update event generation rate. Each time the repetition counter counting down to zero, an update event is generated. The update rate of the shadow registers is also affected by this bit-filed when these shadow registers are enabled.
- Page 367 GD32F20x User Manual 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only. When channel 1 is configured in output mode, this bit-filed contains value to be compared to the counter.
- Page 368 GD32F20x User Manual 31:16 Reserved Must be kept at reset value 15:0 CH3VAL[15:0] Capture or compare value of channel 3 When channel3 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only.
- Page 369 GD32F20x User Manual BRKP Break input polarity This bit specifies the polarity of the BRKIN input signal. 0: BRKIN input active low 1; BRKIN input active high BRKEN Break input enable This bit can be set to enable the BRKIN and CKM clock failure event inputs.
- Page 370 GD32F20x User Manual DTCFG[7:0] Dead time configure The relationship between DTVAL value and the duration of dead-time is as follow: DTCFG[7:5] The duration of dead-time 3’b0xx DTCFG[7:0] * t DTS_CK 3’b10x (64+ DTCFG[5:0]) * t DTS_CK 3’b110 (32+ DTCFG[4:0]) * t DTS_CK 3’b111...
- Page 371 GD32F20x User Manual This register has to be accessed by word (32-bit) Reserved DMATB[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 DMATB[15:0] DMA transfer buffer When a read or write operation is assigned to this register, the register located at the address range (Start Addr + Transfer Timer* 4) will be accessed.
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Page 372: Figure 18-31. General Level 0 Timer Block Diagram
GD32F20x User Manual 18.2. General level0 timer (TIMERx, x=1, 2, 3, 4) Overview 18.2.1. The general level0 timer module (Timer1, 2, 3, 4) is a four-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications. - Page 373 GD32F20x User Manual configuration of the general level0 timer. Figure 18-31. General Level 0 timer block diagram CH0_IN Input Logic CH1_IN Synchronizer&Filter Edge selector Prescaler CH2_IN &Edge Detector CH3_IN ITI0 ITI1 ITI2 ITI3 CK_TIMER TIMERx_CHxCV Counter External Trigger Input logic...
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Page 374: Figure 18-32. Timing Chart Of Internal Clock Divided By 1
GD32F20x User Manual Figure 18-32. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of... -
Page 375: Figure 18-33. Timing Chart Of Psc Value Change From 0 To 2
GD32F20x User Manual Figure 18-33. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. -
Page 376: Figure 18-34. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F20x User Manual Figure 18-34. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 18-35. -
Page 377: Figure 18-36. Timing Chart Of Down Counting Mode, Psc=0/2
GD32F20x User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter will start counting down from the counter-reload value. The update event is generated at each counter underflow. -
Page 378: Figure 18-37. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32F20x User Manual Figure 18-37. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118... -
Page 379: Figure 18-38. Timing Chart Of Center-Aligned Counting Mode
GD32F20x User Manual Figure 18-38. Timing chart of center-aligned counting mode shows some examples of the counter behavior for different clock frequencies when TIMERx_CAR=0x99, TIMERx_PSC=0x0. Figure 18-38. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2... -
Page 380: Figure 18-39. Channel Input Capture Principle
GD32F20x User Manual TIMERx_CHxCV register, at the same time the CHxIF bit is set and the channel interrupt is generated if enabled by CHxIE = 1. Figure 18-39. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP... -
Page 381: Figure 18-40. Channel Output Compare Principle (X=0,1,2,3)
GD32F20x User Manual And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or interrupt, you can set CHxG by software directly. -
Page 382: Figure 18-41. Output-Compare In Three Modes
GD32F20x User Manual So the process can be divided to several steps as below: Step1: Clock configuration. Such as clock source, clock prescaler and so on. Step2: Compare mode configuration. * Set the shadow enable mode by CHxCOMSEN * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL. -
Page 383: Figure 18-42. Eapwm Timechart
GD32F20x User Manual The EAPWM period is determined by TIMERx_CAR and duty cycle is by TIMERx_CHxCV. Figure 18-42. EAPWM timechart shows the EAPWM output and interrupts waveform. The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by 2*TIMERx_CHxCV. -
Page 384: Table 18-7. Examples Of Slave Mode
GD32F20x User Manual Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function. These include, keeping the original level by setting the... -
Page 385: Figure 18-44. Restart Mode
GD32F20x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler 011: ITI3 the polarity selection be used by configuring 100: CI0F_ED and inversion. CHxCAPFLT, no 101: CI0FE0 If ETIFP is selected as prescaler can be 110: CI1FE1 the trigger source, used. -
Page 386: Figure 18-45. Pause Mode
GD32F20x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-45. Pause mode TIMER_CK CNT_REG CI0FE0 TRGIF Event mode ETPSC = 1, ETI is The counter will start ETP = 0, the polarity TRGS[2:0] =3’b111 divided by 2. -
Page 387: Table 18-9. Ouput Trigger Of Timerx(X=1,2,3,4)
GD32F20x User Manual Table 18-8. Input trigger of Timerx(x=1,2,3,4) ITI0 ITI1 ITI2 ITI3 (Note) TIMER1 TIMER0_TRGO TIMER1TRGO1_REMAP TIMER2_TRGO TIMER3_TRGO TIMER2 TIMER0_TRGO TIMER1_TRGO TIMER4_TRGO TIMER3_TRGO TIMER3 TIMER0_TRGO TIMER1_TRGO TIMER2_TRGO TIMER7_TRGO TIMER1_TRGO TIMER2_TRGO TIMER3_TRGO TIMER7_TRGO TIMER4 In connectivity line devices, the source of TIMER1_ITI1 is decided by TIMER1ITI1_REMAP bit... - Page 388 GD32F20x User Manual Register definition 18.2.5. TIMER1 base address: 0x4000 0000 TIMER2 base address: 0x4000 0400 TIMER3 base address: 0x4000 0800 TIMER4 base address: 0x4000 0C00 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
- Page 389 GD32F20x User Manual 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00.
- Page 390 GD32F20x User Manual This register has to be accessed by word (32-bit) Reserved Reserved TI0S MMC[2:0] DMAS Reserved Bits Fields Descriptions 31:8 Reserved Must be kept at reset value TI0S Channel 0 trigger input selection 0: The TIMERx_CH0 pin input is selected as channel 0 trigger input.
- Page 391 GD32F20x User Manual Slave mode configuration register (TIMERx_SMCFG) Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved SMC1 ETPSC[1:0] ETFC[3:0] TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value...
- Page 392 GD32F20x User Manual according to f and record the number of times of the same level of the signal. SAMP After reaching the filtering capacity configured by this bit-field, it is considered to be an effective level. The filtering capability configuration is as follows:...
- Page 393 GD32F20x User Manual 000: Disable mode. The slave mode is disabled; The prescaler is clocked directly by the internal clock (TIMER_CK) when CEN bit is set high. 001: Quadrature decoder mode 0.The counter counts on CI0FE0 edge, while the direction depends on CI1FE1 level.
- Page 394 GD32F20x User Manual CH1DEN Channel 1 capture/compare DMA request enable 0: disabled 1: enabled CH0DEN Channel 0 capture/compare DMA request enable 0: disabled 1: enabled UPDEN Update DMA request enable 0: disabled 1: enabled Reserved Must be kept at reset value.
- Page 395 GD32F20x User Manual Reserved CH3OF CH2OF CH1OF CH0OF Reserved TRGIF Reserved CH3IF CH3IF CH1IF CH0IF UPIF rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. CH3OF Channel 3 over capture flag...
- Page 396 GD32F20x User Manual 1: Channel 1 interrupt occurred UPIF Update interrupt flag This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG)
- Page 397 GD32F20x User Manual high. 0: No generate a channel 1 capture or compare event 1: Generate a channel 1 capture or compare event This bit can be set by software, and cleared by hardware automatically. When this bit is set, the counter is cleared if the center-aligned or up counting mode is selected, else (down counting) it takes the auto-reload value.
- Page 398 GD32F20x User Manual 10: Channel 1 is programmed as input mode, IS1 is connected to CI0FE1 11: Channel 1 is programmed as input mode, IS1 is connected to ITS. Note: When CH1MS[1:0]=11, it is necessary to select an internal trigger input through TRGS bits in TIMERx_SMCFG register.
- Page 399 GD32F20x User Manual 11 and CH0MS bit-filed is 00. CH0COMFEN Channel 0 output compare fast enable When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode.
- Page 400 GD32F20x User Manual 4’b0011 4’b0100 4’b0101 4’b0110 4’b0111 4’b1000 4’b1001 4’b1010 4’b1011 4’b1100 4’b1101 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear.
- Page 401 GD32F20x User Manual 14:12 CH3COMCTL[2:0] Channel 3 compare output control Refer to CH0COMCTL description CH3COMSEN Channel 3 output compare shadow enable Refer to CH0COMSEN description CH3COMFEN Channel 3 output compare fast enable Refer to CH0COMFEN description CH3MS[1:0] Channel 3 mode selection This bit-field specifies the direction of the channel and the input signal selection.
- Page 402 GD32F20x User Manual when the counter is larger than TIMERx_CH2CV, and low otherwise. If configured in PWM mode, the O2CPRE level changes only when the output compare mode is adjusted from “Timing” mode to “PWM” mode or the comparison result changes.
- Page 403 GD32F20x User Manual Refer to CH0CAPPSC description CH3MS[1:0] Channel 3 mode selection Same as Output compare mode CH2CAPFLT[3:0] Channel 2 input capture filter control The CI2 input signal can be filtered by digital filter and this bit-field configure the filtering capability.
- Page 404 GD32F20x User Manual This register has to be accessed by word (32-bit) Reserved Reserved CH3P CH3EN Reserved CH2P CH2EN Reserved CH1P CH1EN Reserved CH0P CH0EN Bits Fields Descriptions 31:14 Reserved Must be kept at reset value CH3P Channel 3 capture/compare function polarity...
- Page 405 GD32F20x User Manual the capture event in channel0. 0: Channel 0 disabled 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CNT[15:0] Bits Fields Descriptions...
- Page 406 GD32F20x User Manual Counter auto reload register (TIMERx_CAR) Address offset: 0x2C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
- Page 407 GD32F20x User Manual Channel 1 capture/compare value register (TIMERx_CH1CV) Address offset: 0x38 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH1VAL[15:0]...
- Page 408 GD32F20x User Manual Channel 3 capture/compare value register (TIMERx_CH3CV) Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CH3VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH3VAL[15:0]...
- Page 409 GD32F20x User Manual This filed define the first address for the DMA access the TIMERx_DMATB. When access is done through the TIMERx_DMA address first time, this bit-field specifies the address you just access. And then the second access to the TIMERx_DMATB, you will access the address of start address + 0x4.
- Page 410 GD32F20x User Manual 18.3. General level1 timer (TIMERx, x=8, 11) Overview 18.3.1. The general level1 timer module (Timer8, 11) is a two-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications.
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Page 411: Figure 18-47. General Level1 Timer Block Diagram
GD32F20x User Manual Block diagram 18.3.3. Figure 18-47. General level1 timer block diagram provides details on the internal configuration of the general level1 timer. Figure 18-47. General level1 timer block diagram CH0_IN Input Logic Synchronizer&Filter CH1_IN Edge selector Prescaler &Edge Detector... -
Page 412: Figure 18-48. Timing Chart Of Internal Clock Divided By 1
GD32F20x User Manual Figure 18-48. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG SMC [2:0] == 3’b111 (external clock mode 0). External input pin is selected as timer clock source The TIMER_CK, which drives counter’s prescaler to count, can be triggered by the event of... -
Page 413: Figure 18-49. Timing Chart Of Psc Value Change From 0 To 2
GD32F20x User Manual Figure 18-49. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. -
Page 414: Figure 18-50. Timing Chart Of Up Counting Mode, Psc=0/2
GD32F20x User Manual Figure 18-50. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 18-51. -
Page 415: Figure 18-52. Timing Chart Of Down Counting Mode, Psc=0/2
GD32F20x User Manual Counter down counting In this mode, the counter counts down continuously from the counter-reload value, which is defined in the TIMERx_CAR register, to 0 in a count-down direction. Once the counter reaches to 0, the counter will start counting down from the counter-reload value. The update event is generated each time when underflows. -
Page 416: Figure 18-53. Timing Chart Of Down Counting Mode, Change Timerx_Car Ongoing
GD32F20x User Manual Figure 18-53. Timing chart of down counting mode, change TIMERx_CAR ongoing TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118... -
Page 417: Figure 18-54. Timing Chart Of Center-Aligned Counting Mode
GD32F20x User Manual Figure 18-54. Timing chart of center-aligned counting mode show some examples of the counter behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 18-54. Timing chart of center-aligned counting mode TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11... -
Page 418: Figure 18-55. Channel Input Capture Principle
GD32F20x User Manual generated if enabled by CHxIE = 1. Figure 18-55. Channel input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock CI1FE0 Register presclare Processer （CH0VAL） CH0IF CH0CAPPSC... -
Page 419: Figure 18-56. Channel Output Compare Principle (X=0,1)
GD32F20x User Manual And CHxIF is asserted. If the CHxIF is high, the CHxOF will be asserted also. The interrupt and DMA request will be asserted based on the your configuration of CHxIE and CHxDEN in TIMERx_DMAINTEN Direct generation: If you want to generate a DMA request or Interrupt, you can set CHxG by software directly. -
Page 420: Figure 18-57. Output-Compare Under Three Modes
GD32F20x User Manual Step1: Clock configuration. Such as clock source, clock prescaler and so on. Step2: Compare mode configuration. * Set the shadow enable mode by CHxCOMSEN * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL. * Select the active high polarity by CHxP/CHxNP... -
Page 421: Figure 18-58. Eapwm Timechart
GD32F20x User Manual The EAPWM period is determined by TIMERx_CAR and duty cycle is by TIMERx_CHxCV. Figure 18-58. EAPWM timechart shows the EAPWM output and interrupts waveform. The CAPWM period is determined by 2*TIMERx_CAR, and duty cycle is determined by Figure 18-59. -
Page 422: Table 18-10. Slave Mode Examples
GD32F20x User Manual Channel output prepare signal When the TIMERx is used in the compare match output mode, the OxCPRE signal (Channel x Output prepare signal) is defined by setting the CHxCOMCTL filed. The OxCPRE signal has several types of output function. These include, keeping the original level by setting the... -
Page 423: Figure 18-60. Restart Mode
GD32F20x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Restart mode The counter will be For the ITI0, no filter TRGS[2:0] = 3’b000 For ITI0, no polarity cleared and restart and prescaler can be ITI0 is selected. -
Page 424: Figure 18-62. Event Mode
GD32F20x User Manual Mode Selection Source Selection Polarity Selection Filter and Prescaler Figure 18-62. Event mode TIMER_CK CI0FE0 CNT_REG TRGIF Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event. -
Page 425: Table 18-11. Input Trigger Of Timerx(X=8,11)
GD32F20x User Manual Figure 18-63. Single pulse mode TIMERx_CHxCV = 4 TIMERx_CAR=99 TIMER_CK (PSC_CLK) Under SPM, counter stop CNT_REG OxCPRE Timers interconnection Timer can be configured as interconnection, that is, one timer which operate in the master mode outputs TRGO signal to control another timer which operate in the slave mode, TRGO include reset evevt, start evevt, update evevt, capture/compare pulse evevt, compare evevt. - Page 426 GD32F20x User Manual Register definition 18.3.5. TIMER8 base address: 0x4001 4C00 TIMER11 base address: 0x4001 1800 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved CKDIV[1:0] ARSE...
- Page 427 GD32F20x User Manual can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00. Direction 0: Count up 1: Count down If the timer work in center-aligned mode or encoder mode, this bit is read only.
- Page 428 GD32F20x User Manual Reserved Reserved TRGS[2:0] Reserved SMC[2:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value Master-slave mode This bit can be used to synchronize selected timers to begin counting at the same time. The TRGI is used as the start event, and through TRGO, timers are connected together.
- Page 429 GD32F20x User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved TRGIE Reserved CH1IE CH0IE UPIE Bits Fields Descriptions 31:7 Reserved Must be kept at reset value.
- Page 430 GD32F20x User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. CH1OF Channel 1 over capture flag Refer to CH0OF description CH0OF Channel 0 over capture flag When channel 0 is configured in input mode, this flag is set by hardware when a capture event occurs while CH0IF flag has already been set.
- Page 431 GD32F20x User Manual Reserved TRGG Reserved. CH1G CH0G Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. TRGG Trigger event generation This bit is set by software and cleared by hardware automatically. When this bit is set, the TRGIF flag in TIMERx_STAT register is set, related interrupt or DMA transfer can occur if enabled.
- Page 432 GD32F20x User Manual Output compare mode: Bits Fields Descriptions 31:16 Reserved Must be kept at reset value CH1COMCEN Channel 1 output compare clear enable Refer to CH0COMCEN description 14:12 CH1COMCTL[2:0] Channel 1 compare output control Refer to CH0COMCTL description CH1COMSEN...
- Page 433 GD32F20x User Manual 100: Force low. O0CPRE is forced to low level. 101: Force high. O0CPRE is forced to high level. 110: PWM mode0. When counting up, O0CPRE is high when the counter is smaller than TIMERx_CH0CV, and low otherwise. When counting down, O0CPRE is low when the counter is larger than TIMERx_CH0CV, and high otherwise.
- Page 434 GD32F20x User Manual Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:12 CH1CAPFLT[3:0] Channel 1 input capture filter control Refer to CH0CAPFLT description 11:10 CH1CAPPSC[1:0] Channel 1 input capture prescaler Refer to CH0CAPPSC description CH1MS[1:0] Channel 1 mode selection...
- Page 435 GD32F20x User Manual Same as Output compare mode Channel control register 2 (TIMERx_CHCTL2) Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved CH1P CH1EN Reserved CH0P CH0EN Bits Fields Descriptions 31:6...
- Page 436 GD32F20x User Manual Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value. Writing to this bit-filed can change the value of the counter.
- Page 437 GD32F20x User Manual Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter. Note: When the timer is configured in input capture mode, this register must be configured a non-zero value (such as 0xFFFF) which is larger than user expected value.
- Page 438 GD32F20x User Manual Reserved CH1VAL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CH1VAL[15:0] Capture or compare value of channel1 When channel 1 is configured in input mode, this bit-filed indicates the counter value corresponding to the last capture event. And this bit-filed is read-only.
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Page 439: Figure 18-64. General Level2 Timer Block Diagram
GD32F20x User Manual 18.4. General level2 timer (TIMERx, x=9, 10, 12, 13) Overview 18.4.1. The general level2 timer module (Timer9, 10, 12, 13) is a one-channel timer that supports input capture, output compare. They can generate PWM signals to control motor or be used for power management applications. - Page 440 GD32F20x User Manual Figure 18-64. General level2 timer block diagram Input Logic CH0_IN Prescaler Synchronizer&Filter &Edge Detector Trigger processor CK_TIMER Trigger Selector&Counter Counter TIMERx_CHxCV TIMERx_TRGO TIMER_CK PSC_CLK Register /Interrupt APB BUS Output Logic generation of outputs signals in Register set and update...
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Page 441: Figure 18-65. Timing Chart Of Internal Clock Divided By 1
GD32F20x User Manual Figure 18-65. Timing chart of internal clock divided by 1 CK_TIMER update event generate(UPG) Reload Pulse Update event (UPE) PSC_CLK = TIMER_CK CNT_REG Clock prescaler The counter clock (PSC_CK) is obtained by the TIMER_CK through the prescaler, and the prescale factor can be configured from 1 to 65536 through the prescaler register (TIMERx_PSC). -
Page 442: Figure 18-67. Up-Counter Timechart, Psc=0/2
GD32F20x User Manual Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. Once the counter reaches the counter reload value, the counter will start counting up from 0 again. The update event is generated at each counter overflow. -
Page 443: Figure 18-68. Up-Counter Timechart, Change Timerx_Car On The Go
GD32F20x User Manual Figure 18-68. Up-counter timechart, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 114 115 116 117 118 119 120... - Page 444 GD32F20x User Manual in different clock frequencies when TIMERx_CAR=0x99. Figure 18-69. Down-counter timechart, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF)
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Page 445: Figure 18-70. Down-Counter Timechart, Change Timerx_Car On The Go
GD32F20x User Manual Figure 18-70. Down-counter timechart, change TIMERx_CAR on the go TIMER_CK PSC_CLK ARSE = 0 CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) Auto-reload register change CAR Vaule ARSE = 1 CNT_REG 119 118 Update event (UPE) - Page 446 GD32F20x User Manual behavior when TIMERx_CAR=0x99. TIMERx_PSC=0x0 Figure 18-71. Center-aligned counter timechart TIMER_CK PSC_CLK CNT_REG Underflow Overflow UPIF CHxCV=2 TIMERx_CTL0 CAM = 2'b11 CHxIF TIMERx_CTL0 CAM = 2'b10 (upcount only CHxIF TIMERx_CTL0 CAM = 2'b10 (downcount only CHxIF Hardware set...
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Page 447: Figure 18-72. Channels Input Capture Principle
GD32F20x User Manual Figure 18-72. Channels input capture principle Edge Detector Synchronizer Edge selector &inverter Based on Filter CH0P&CH0NP TIMER_CK CI0FED CI0FE0 Rising&Falling Rising/Falling Capture Clock presclare Register Processer （CH0VAL） CH0IF CH0CAPPSC CH0_CC_I CH0IE CH0MS TIMERx_CC_INT Capture INT From Other Channal... -
Page 448: Figure 18-73. Channel Output Compare Principle (X=0)
GD32F20x User Manual Direct generation: If you want to generate a DMA request or Interrupt, you can set CHxG by software directly. The channel input capture function can be also used for pulse width measurement from signals on the TIMERx_CHx pins. For example, PWM signal connect to CI0 input. Select channel 0 capture signals to CI0 by setting CH0MS to 2’b01 in the channel control register... -
Page 449: Figure 18-74. Output-Compare Under Three Modes
GD32F20x User Manual * Set the output mode (Set/Clear/Toggle) by CHxCOMCTL. * Select the active high polarity by CHxP/CHxNP * Enable the output by CHxEN Step3: Interrupt/DMA-request enables configuration by CHxIE Step4: Compare output timing configuration by TIMERx_CAR and TIMERx_CHxCV. - Page 450 GD32F20x User Manual level is changed according to the counting direction and the relationship between the counter value and the TIMERx_CHxCV content. With regard to a more detail description refer to the relative bit definition. Another special function of the OxCPRE signal is a forced output which can be achieved by setting the CHxCOMCTL field to 0x04/0x05.
- Page 451 GD32F20x User Manual Register definition 18.4.5. TIMER9 base address: 0x4001 5000 TIMER10 base address: 0x4001 5400 TIMER12 base address: 0x4000 1C00 TIMER13 base address: 0x4000 2000 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
- Page 452 GD32F20x User Manual 11: Center-aligned and counting up/down assert mode. The counter counts under center-aligned and channel is configured in output mode (CHxMS=00 in TIMERx_CHCTL0 register). Both when counting up and counting down, CHxF bit can be set. After the counter is enabled, cannot be switched from 0x00 to non 0x00.
- Page 453 GD32F20x User Manual Reserved Reserved MMC[2:0] Reserved Bits Fields Descriptions 31:7 Reserved Must be kept at reset value MMC[2:0] Master mode control These bits control the selection of TRGO signal, which is sent in master mode to slave timers for synchronization function.
- Page 454 GD32F20x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CH0IE Channel 0 capture/compare interrupt enable 0: disabled 1: enabled UPIE Update interrupt enable 0: disabled 1: enabled Interrupt flag register (TIMERx_INTF) Address offset: 0x10 Reset value: 0x0000 0000...
- Page 455 GD32F20x User Manual This bit is set by hardware on an update event and cleared by software. 0: No update interrupt occurred 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
- Page 456 GD32F20x User Manual CH0COM CH0COM Reserved CH0COMCTL[2:0] Reserved. CH0MS[1:0] CH0CAPFLT[3:0] CH0CAPPSC[1:0] Output compare mode: Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. CH0COMCTL[2:0] Channel 0 compare output control This bit-field specifies the compare output mode of the the output prepare signal O0CPRE.
- Page 457 GD32F20x User Manual When this bit is set, the effect of an event on the trigger in input on the capture/compare output will be accelerated if the channel is configured in PWM0 or PWM1 mode. The output channel will treat an active edge on the trigger input as a compare match, and CH0_O is set to the compare level independently from the result of the comparison.
- Page 458 GD32F20x User Manual 4’b1110 4’b1111 CH0CAPPSC[1:0] Channel 0 input capture prescaler This bit-field specifies the factor of the prescaler on channel 0 input. The prescaler is reset when CH0EN bit in TIMERx_CHCTL2 register is clear. 00: Prescaler disable, input capture occurs on every channel input edge...
- Page 459 GD32F20x User Manual 1: Channel 0 enabled Counter register (TIMERx_CNT) Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CNT[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CNT[15:0] This bit-filed indicates the current counter value.
- Page 460 GD32F20x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved CARL[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 CARL[15:0] Counter auto reload value This bit-filed specifies the auto reload value of the counter.
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Page 461: Figure 18-75. Basic Timer Block Diagram
GD32F20x User Manual 18.5. Basic timer (TIMERx, x=5, 6) Overview 18.5.1. The basic timer module (Timer5, 6) reference is a 16-bit counter that can be used as an unsigned counter. The basic timer can be configured to generate DMA request and TRGO to DAC. -
Page 462: Figure 18-76. Timing Chart Of Internal Clock Divided By 1
GD32F20x User Manual The TIMER_CK, driven counter’s prescaler to count, is equal to CK_TIMER used to drive the counter prescaler. When the CEN is set, the CK_TIMER will be divided by PSC value to generate PSC_CLK. Figure 18-76. Timing chart of internal clock divided by 1... -
Page 463: Figure 18-77. Timing Chart Of Psc Value Change From 0 To 2
GD32F20x User Manual Figure 18-77. Timing chart of PSC value change from 0 to 2 TIMER_CK PSC value Prescaler shadow Prescaler CNT PSC_CLK CNT_REG Reload Pulse Counter up counting In this mode, the counter counts up continuously from 0 to the counter-reload value, which is defined in the TIMERx_CAR register, in a count-up direction. -
Page 464: Figure 18-79. Timing Chart Of Up Counting Mode, Change Timerx_Car Ongoing
GD32F20x User Manual Figure 18-78. Timing chart of up counting mode, PSC=0/2 TIMER_CK PSC = 0 PSC_CLK CNT_REG Update event (UPE) Hardware set Update interrupt flag (UPIF) PSC = 2 PSC_CLK CNT_REG Update event (UPE) Software clear Update interrupt flag (UPIF) Hardware set Figure 18-79. - Page 465 GD32F20x User Manual Single pulse mode Single pulse mode is opposite to the repetitive mode, which can be enabled by setting SPM in TIMERx_CTL0. When you set SPM, the counter will be clear and stop when the next update event.
- Page 466 GD32F20x User Manual Register definition 18.5.5. TIMER5 base address: 0x4000 1000 TIMER6 base address: 0x4000 1400 Control register 0 (TIMERx_CTL0) Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved ARSE Reserved...
- Page 467 GD32F20x User Manual The UPG bit is set The counter generates an overflow or underflow event The restart mode generates an update event. 1: Update event disable. Note: When this bit is set to 1, setting UPG bit or the restart mode does not generate an update event, but the counter and prescaler are initialized.
- Page 468 GD32F20x User Manual Interrupt enable register (TIMERx_DMAINTEN) Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved UPDEN Reserved UPIE Bits Fields Descriptions 31:9 Reserved Must be kept at reset value. UPDEN...
- Page 469 GD32F20x User Manual 1: Update interrupt occurred Software event generation register (TIMERx_SWEVG) Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved Bits Fields Descriptions 31:1 Reserved Must be kept at reset value.
- Page 470 GD32F20x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved PSC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value 15:0 PSC[15:0] Prescaler value of the counter clock The TIMER_CK clock is divided by (PSC+1) to generate the counter clock. The value of this bit-filed will be loaded to the corresponding shadow register at every update event.
- Page 471 GD32F20x User Manual Universal synchronous/asynchronous receiver /transmitter (USART) 19.1. Overview The Universal Synchronous/Asynchronous Receiver/Transmitter (USART) provides a flexible serial data exchange interface. Data frames can be transferred in full duplex or half duplex mode, synchronously or asynchronously through this interface. A programmable baud rate generator divides the UCLK to produce a dedicated baud rate lock for the USART transmitter and receiver.
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Page 472: Table 19-1. Usart Important Pins Description
GD32F20x User Manual Character mode (T=0). – Block mode (T=1). – Direct and inverse convention. – Multiprocessor communication. Enter into mute mode if address match does not occur. – Wake up from mute mode by idle frame or address match detection. -
Page 473: Figure 19-1. Usart Module Block Diagram
GD32F20x User Manual Figure 19-1. USART module block diagram CPU/DMA Transmit Shift Register SW_RX IrDA USART Data Register Block Receive Shift Register USART Guard Time and Prescaler Register nRTS Hardware CK Controller Flow nCTS Controller USART Control Registers USART Address... - Page 474 GD32F20x User Manual STB[1:0] stop bit length (bit) usage description normal USART and single-wire modes Smartcard mode for transmitting and receiving In an idle frame, all the frame bits are logic 1. The frame length is equal to the normal USART frame.
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Page 475: Figure 19-3. Usart Transmit Procedure
GD32F20x User Manual the USART_DATA register and will be set by hardware after the data is put into the transmit shift register. If a data is written to the USART_DATA register while a transmission is ongoing, it will be firstly stored in the transmit buffer, and transferred to the transmit shift register after the current transmission is done. -
Page 476: Figure 19-4. Oversampling Method Of A Receive Frame Bit
GD32F20x User Manual Enable DMA (DENR bit) in USART_CTL2 if multibuffer communication is selected. Set the baud rate in USART_BAUD. Set the UEN bit in USART_CTL0 to enable the USART. Set the REN bit in USART_CTL0. After being enabled, the receiver receives a bit stream after a valid start pulse has been detected. -
Page 477: Figure 19-5. Configuration Step When Using Dma For Usart Transmission
GD32F20x User Manual If a noise error (NERR), parity error (PERR), frame error (FERR) or overrun error (ORERR) is generated during a receiving process, then NERR, PERR, FERR or ORERR will be set at same time with RBNE. If DMA is disabled, the software needs to check whether the RBNE interrupt is caused by noise error, parity error, framing error or overflow error when the RBNE interrupt occurs. -
Page 478: Figure 19-6. Configuration Step When Using Dma For Usart Reception
GD32F20x User Manual occurs if the TCIE bit in USART_CTL0 is set. When DMA is used for USART reception, DMA transfers data from the receive data buffer of the USART to the internal sram. The configuration step is shown in Figure 19-6. -
Page 479: Figure 19-7. Hardware Flow Control Between Two Usarts
GD32F20x User Manual Figure 19-7. Hardware flow control between two USARTs TX module RX module nCTS nRTS USART 1 USART 2 RX module TX module nRTS nCTS RTS flow control The USART receiver outputs the nRTS, which reflects the status of the receive buffer. When data frame is received, the nRTS signal goes high to prevent the transmitter from sending next frame. - Page 480 GD32F20x User Manual big burden for a device to monitor all of the messages on the RX pin. To reduce the burden of a device, software can put an USART module into a mute mode by setting the RWU bit in USART_CTL0 register.
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Page 481: Figure 19-9. Break Frame Occurs During Idle State
GD32F20x User Manual Figure 19-9. Break frame occurs during idle state As shown in Figure 19-10. Break frame occurs during a frame, if a break frame occurs during a frame on the RX pin, the FERR status will be asserted for the current frame. -
Page 482: Figure 19-11. Example Of Usart In Synchronous Mode
GD32F20x User Manual Figure 19-11. Example of USART in synchronous mode Data output Data input USART Device (master mode) (slave mode) Clock input Figure 19-12. 8-bit format USART synchronous waveform (CLEN=1) IrDA SIR ENDEC mode 19.3.10. The IrDA mode is enabled by setting the IREN bit in USART_CTL2. The LMEN, STB[1:0], CKEN bits in USART_CTL1 and HDEN, SCEN bits in USART_CTL2 should be reset in IrDA mode. -
Page 483: Figure 19-13. Irda Sir Endec Module
GD32F20x User Manual Figure 19-13. IrDA SIR ENDEC module inside chip outside chip RX pin Receive Decoder Infrared Normal IREN USART TX pin Transmit Encoder SIR MODULE In IrDA mode, the polarity of the TX pin and RX pin is different. The TX pin is usually at low state, while the RX pin is usually at high state. -
Page 484: Figure 19-15. Iso7816-3 Frame Format
GD32F20x User Manual Half-duplex communication mode 19.3.11. The half-duplex communication mode is enabled by setting the HDEN bit in USART_CTL2. The LMEN, CKEN bits in USART_CTL1 and SCEN, IREN bits in USART_CTL2 should be reset in half-duplex communication mode. In the half-duplex mode the receive line is internally connected to the TX pin, and the RX pin is no longer used. - Page 485 GD32F20x User Manual During USART transmission, if a parity error event is detected, the smartcard may NACK the current frame by pulling down the TX pin during the last 1 bit time of the stop bits. The USART can automatically resend data according to the protocol by SCRTNUM times. An interframe gap of 2.5 bits time will be inserted before the start of a resented frame.
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Page 486: Table 19-3. Usart Interrupt Requests
GD32F20x User Manual (0x0) before the start of the block. With this value, the end of the block interrupt occurs after the 4th received character. The block length value can be read from the receive buffer at the third byte. -
Page 487: Figure 19-16. Usart Interrupt Mapping Diagram
GD32F20x User Manual Figure 19-16. USART interrupt mapping diagram IDLEF IDLEIE ORERR RBNEIE PERR PEIE FERR NERR ORERR ERRIE LBDF LBDIE USART_INT RBNE RBNEIE TCIE TBEIE CTSF CTSIE RTIE EBIE... - Page 488 GD32F20x User Manual 19.4. Register definition USART0 base address: 0x4001 3800 USART1 base address: 0x4000 4400 USART2 base address: 0x4000 4800 USART5 base address: 0x4001 7000 UART3 base address: 0x4000 4C00 UART4 base address: 0x4000 5000 UART6 base address: 0x4000 7800...
- Page 489 GD32F20x User Manual 1: The USART has detected a LIN break. Transmit data buffer empty This bit is set after power on or when the transmit data has been transferred to the transmit shift register. An interrupt occurs if the TBEIE bit in USART_CTL0 is set.
- Page 490 GD32F20x User Manual registers one by one. 0: The USART does not detect a noise error. 1: The USART has detected a noise error. FERR Frame error flag This bit is set when the RX pin is detected low during the stop bits of a receive frame.
- Page 491 GD32F20x User Manual Baud rate register (USART_BAUD) 19.4.3. Address offset: 0x08 Reset value: 0x0000 0000 The software must not write this register when the USART is enabled (UEN=1). This register has to be accessed by word (32-bit). Reserved INTDIV [11:0]...
- Page 492 GD32F20x User Manual Wakeup method in mute mode 0: wake up by idle frame. 1: wake up by address match. This bit field cannot be written when the USART is enabled (UEN=1). PCEN Parity check function enable 0: Parity check function disabled.
- Page 493 GD32F20x User Manual Receiver wakeup from mute mode. Software can set this bit to make the USART work in mute mode and reset this bit to wake up the USART. In wake up by idle frame mode (WM=0), this bit can be reset by hardware when an idle frame has been detected.
- Page 494 GD32F20x User Manual Only 1 stop bit and 2 stop bits are available for UART3/4/6/7. CKEN CK pin enable 0: CK pin disabled 1: CK pin enabled This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved for UART3/4/6/7.
- Page 495 GD32F20x User Manual Control register 2 (USART_CTL2) 19.4.6. Address offset: 0x14 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). Reserved Reserved CTSIE CTSEN RTSEN DENT DENR SCEN NKEN HDEN IRLP IREN ERRIE Bits Fields Descriptions...
- Page 496 GD32F20x User Manual 1: Smartcard Mode enabled This bit field cannot be written when the USART is enabled (UEN=1). This bit is reserved for UART3/4/6/7. NKEN NACK enable in Smartcard mode This bit enables the NACK transmission when parity error occurs in smartcard mode.
- Page 497 GD32F20x User Manual GUAT[7:0] PSC[7:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:8 GUAT[7:0] Guard time value in Smartcard mode TC flag assertion time is delayed by GUAT[7:0] baud clock cycles. This bit field cannot be written when the USART is enabled (UEN=1).
- Page 498 GD32F20x User Manual Reserved MSBF DINV TINV RINV Reserved EBIE RTIE SCRTNUM[2:0] RTEN Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. MSBF Most significant bit first This bit specifies the sequence of the data bits in transmission and reception.
- Page 499 GD32F20x User Manual In reception mode, a frame reception can be tried by (SCRTNUM+1) times. If the parity bit mismatch event occurs (SCRTNUM+1) times for a frame, the RBNE and PERR bits are set. When these bits are configured as 0x0, there will be no automatic retransmission in transmit mode.
- Page 500 GD32F20x User Manual 23:0 RT[23:0] Receiver timeout threshold These bits are used to specify receiver timeout value in terms of number of baud clocks. If Smartcard mode is not enabled, the RTF bit of USART_STAT1 is set if no new start bit is detected longer than RT bits time after the last received character.
- Page 501 GD32F20x User Manual This bit is set when the RX pin is in idle state for longer than RT bits time. An interrupt occurs if the RTIE bit in USART_CTL3 is set. Software can clear this bit by writing 0 to it.
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Page 502: Figure 20-1. I2C Module Block Diagram
GD32F20x User Manual Inter-integrated circuit interface (I2C) 20.1. Overview The I2C (inter-integrated circuit) module provides an I2C interface which is an industry standard two-line serial interface for MCU to communicate with external I2C interface. I2C bus uses two serial lines: a serial data line, SDA, and a serial clock line, SCL. -
Page 503: Table 20-1. Definition Of I2C-Bus Terminology (Refre To The I2C Specification Of Philips Semiconductors)
GD32F20x User Manual Figure 20-1. I2C module block diagram PEC register CRC Calculation / Check SDA Controller Shift Register SCL Controller Data Register SMBA Control Registers Timing and Control Logic Status Flags DMA / Interrupts Table 20-1. Definition of I2C-bus terminology (refre to the I2C specification of philips... -
Page 504: Figure 20-2. Data Validation
GD32F20x User Manual AND function. Data on the I2C-bus can be transferred at rates of up to 100 Kbit/s in the standard mode and up to 400 Kbit/s in the fast mode. Due to the variety of different technology devices (CMOS, NMOS, bipolar) that can be connected to the I2C-bus, the voltage levels of the logical ‘0’... -
Page 505: Figure 20-4. Clock Synchronization
GD32F20x User Manual transition of this clock may not change the state of the SCL line. The SCL line is therefore held LOW by the master with the longest LOW period. Masters with shorter LOW period enter a HIGH wait-state during this time. -
Page 506: Figure 20-6. I2C Communication Flow With 7-Bit Address
GD32F20x User Manual addresses match with each other, the I2C slave will send an ACK to the I2C bus and respond to the following command on I2C bus: transmitting or receiving the desired data. Additionally, if General Call is enabled by software, the I2C slave always responses to a General Call Address (0x00). - Page 507 GD32F20x User Manual Programming model in slave transmitting mode As is shown in Figure 20-9. Programming model for slave transmitting (10-bit address mode), the following software procedure should be followed if users wish to transmit data in slave transmitter mode: First of all, enable I2C peripheral clock as well as configure clock related registers in I2C_CTL1 to make sure correct I2C timing.
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Page 508: Figure 20-9. Programming Model For Slave Transmitting (10-Bit Address Mode)
GD32F20x User Manual Figure 20-9. Programming model for slave transmitting (10-bit address mode) I2C Line State Hardware Action Software Flow IDLE 1) Software initialization Master generates START condition Master sends Header Slave sends Acknowledge Master sends Address Slave sends Acknowledge... -
Page 509: Figure 20-11. Programming Model For Master Transmitting (10-Bit Address Mode)
GD32F20x User Manual After the last byte is received, RBNE is set. Software reads the last byte. STPDET bit is set when I2C detects a STOP signal on I2C bus and software reads I2C_STAT0 and then writes I2C_CTL0 to clear the STPDET bit. - Page 510 GD32F20x User Manual Now I2C enters data transmission stage and hardware sets TBE bit because both the shift register and data register I2C_DATA are empty. Software now writes the first byte data to I2C_DATA register, but the TBE will not be cleared because the byte written in I2C_DATA is moved to internal shift register immediately.
- Page 511 GD32F20x User Manual Figure 20-11. Programming model for master transmitting (10-bit address mode) I2C Line State Software Flow Hardware Action 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master 3) Clear SBSEND...
- Page 512 GD32F20x User Manual reading I2C_STAT0 and writing 10-bit lower address to I2C_DATA. After the 7-bit or 10-bit address has been sent, the I2C hardware sets the ADDSEND bit and software should clear the ADDSEND bit by reading I2C_STAT0 and then I2C_STAT1.
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Page 513: Figure 20-12. Programming Model For Master Receiving Using Solution A (10-Bit Address Mode)
GD32F20x User Manual Figure 20-12. Programming model for master receiving using Solution A (10-bit address mode) Hardware I2C Line State Software Flow Action 1) Software initialization IDLE 2) Set START START Condition Set SBSEND SCL Strechd 3) Clear SBSEND Master sends Header... - Page 514 GD32F20x User Manual register and enters master mode. Now software should clear the SBSEND bit by reading I2C_STAT0 and then writing a 7-bit address or header of a 10-bit address to I2C_DATA. I2C begins to send address or header to I2C bus as soon as SBSEND bit is cleared. If...
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Page 515: Figure 20-13. Programming Model For Master Receiving Mode Using Solution B
GD32F20x User Manual Figure 20-13. Programming model for master receiving mode using solution B (10-bit address mode) I2C Line State Hardware Action Software Flow 1) Software initialization IDLE 2) Set START Master generates START condition Set SBSEND SCL stretched by master... - Page 516 GD32F20x User Manual When works in slave mode, the SCL line stretching function can be disabled by setting the SS bit in the I2C_CTL0 register. If this bit is set, the software is required to be quick enough to serve the TBE, RBNE and BTC status, otherwise, overflow or underflow situation might occur.
- Page 517 GD32F20x User Manual related chips such as a laptop's rechargeable battery subsystem (see Smart Battery Data). SMBus protocol Each message transaction on SMBus follows the format of one of the defined SMBus protocols. The SMBus protocols are a subset of the data transfer formats defined in the I2C specifications.
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Page 518: Table 20-2. Event Status Flags
GD32F20x User Manual a less common "Host Notify Protocol", providing similar notifications which is based on the I2C multi-master mode but it can pass more data. SMBus programming flow The programming flow for SMBus is similar to normal I2C. In order to use SMBus mode, the application should configure several SMBus specific registers, respond to some SMBus specific flags and implement the upper protocols described in SMBus specification. - Page 519 GD32F20x User Manual 20.4. Register definition I2C0 base address: 0x4000 5400 I2C1 base address: 0x4000 5800 I2C2 base address: 0x4000 C000 Control register 0 (I2C_CTL0) 20.4.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit).
- Page 520 GD32F20x User Manual being received. PECTRANS bit indicates that the current receiving byte is a PEC byte. 1: ACKEN bit specifies whether to send ACK or NACK for the next byte that is to be received, PECTRANS bit indicates the next byte that is to be received is a PEC byte.
- Page 521 GD32F20x User Manual 1: SMBus mode I2CEN I2C peripheral enable 0: I2C is disabled 1: I2C is enabled Control register 1 (I2C_CTL1) 20.4.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by half-word (16-bit) or word (32-bit).
- Page 522 GD32F20x User Manual Reserved Must be kept the reset value. I2CCLK[5:0] I2C Peripheral clock frequency I2CCLK[5:0] should be the frequency of input APB1 clock in MHz which is at least 000000 - 000001: Not allowed 000010 - 111100: 2 MHz ~ 60MHz...
- Page 523 GD32F20x User Manual This register can be accessed by half-word (16-bit) or word (32-bit). Reserved Reserved ADDRESS2[7:1] DUADEN Bits Fields Descriptions 31:16 Reserved Must be kept the reset value. 15:8 Reserved Must be kept the reset value. ADDRESS2[7:1] The second I2C address for the slave in Dual-Address mode...
- Page 524 GD32F20x User Manual LOSTAR ADD10S ADDSEN SMBALT SMBTO Reserved PECERR OUERR AERR BERR RBNE Reserved STPDET SBSEND rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 rc_w0 Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. SMBALT SMBus Alert status This bit is set by hardware and cleared by writing 0.
- Page 525 GD32F20x User Manual This bit is set by hardware and cleared by writing 0. 0: No bus error 1: A bus error detected I2C_DATA is empty during transmitting This bit is set by hardware after it moves a byte from I2C_DATA to shift register and cleared by writing a byte to I2C_DATA.
- Page 526 GD32F20x User Manual I2C_STAT1. 0: In slave mode, no address is received or the received address does not match witih its own address. In master mode, no address is sent or address has been sent but not received the ACK from slave.
- Page 527 GD32F20x User Manual RXGC General call address (0x00) received. This bit is cleared by hardware after a STOP or a START signal or I2CEN=0. 0: No general call address received 1: General call address received Reserved Must be kept the reset value.
- Page 528 GD32F20x User Manual 1: T =16/9 high 13:12 Reserved Must be kept at reset value. 11:0 CLKC[11:0] I2C clock control in master mode In standard speed mode: T =CLKC*T high PCLK1 In fast speed mode if DTCY=0: =CLKC*T =2*CLKC*T high...
- Page 529 GD32F20x User Manual Serial peripheral interface/Inter-IC sound (SPI/I2S) 21.1. Overview The SPI/I2S module can communicate with external devices using the SPI protocol or the I2S audio protocol. The Serial Peripheral Interface (SPI) provides a SPI protocol of data transmission and reception function in master or slave mode.
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Page 530: Figure 21-1. Block Diagram Of Spi
GD32F20x User Manual 21.3. SPI function overview SPI block diagram 21.3.1. Figure 21-1. Block diagram of SPI SYSCLK MOSI TXBuffer MISO RX Buffer SPI signal description 21.3.2. Normal configuration (Not Quad-SPI Mode) Table 21-1. SPI signal description Pin Name Direction... -
Page 531: Figure 21-2. Spi Timing Diagram In Normal Mode
GD32F20x User Manual Pin Name Direction Description application. Slave in hardware NSS mode: NSS input, as a chip select signal for slave. Quad-SPI configuration SPI is in single wire mode by default and enters into Quad-SPI mode after QMOD bit in SPI_QCTL register is set (only available in SPI0). -
Page 532: Figure 21-3. Spi Timing Diagram In Quad-Spi Mode (Ckpl=1, Ckph=1, Lf=0)
GD32F20x User Manual Figure 21-3. SPI timing diagram in Quad-SPI mode (CKPL=1, CKPH=1, LF=0) sample MOSI D0[4] D0[0] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] In normal mode, the length of data is configured by the FF16 bit in the SPI_CTL0 register. -
Page 533: Table 21-4. Nss Function In Master Mode
GD32F20x User Manual (SWNSSEN=1). Then, once the NSS pin (in hardware NSS mode) or the SWNSS bit (in software NSS mode) goes low, the SPI automatically enters to slave mode and triggers a master fault flag CONFERR. If the application wants to use NSS line to control the SPI slave, NSS should be configured to hardware output mode (SWNSSEN=0, NSSDRV=1). - Page 534 GD32F20x User Manual Mode Description Register configuration Data pin usage BDOEN: Don’t care MSTMOD = 1 Master reception with RO = 1 MOSI: not used unidirectional connection BDEN = 0 MISO: reception BDOEN: Don’t care MSTMOD = 1 Master transmission with...
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Page 535: Figure 21-4. A Typical Full-Duplex Connection
GD32F20x User Manual Figure 21-4. A typical full-duplex connection Figure 21-5. A typical simplex connection (Master: Receive, Slave: Transmit) Figure 21-6. A typical simplex connection (Master: Transmit only, Slave: Receive) Master Slave MISO MISO MOSI MOSI Figure 21-7. A typical bidirectional connection... - Page 536 GD32F20x User Manual Initialization sequence Before transmitting or receiving data, application should follow the SPI initialization sequence described below: If master mode is used, program the PSC [2:0] bits in SPI_CTL0 register to generate SCK with desired baud rate, otherwise, ignore this step.
- Page 537 GD32F20x User Manual SPI operation sequence in different modes (not Quad-SPI) In full-duplex mode, either MFD or SFD, application should monitor the RBNE and TBE flags and then follow the sequences described above. The transmission mode (MTU, MTB, STU or STB) is similar to the transmission sequence of full-duplex mode except that the RBNE bit need to be ignored.
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Page 538: Figure 21-8. Timing Diagram Of Write Operation In Quad-Spi Mode
GD32F20x User Manual Figure 21-8. Timing diagram of write operation in Quad-SPI mode Software write SPI_DATA Hardware sets TBE again sample MOSI D0[0] D0[4] D1[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6] D1[2] D0[7] D0[3] D1[7] D1[3] Quad read operation SPI works in quad read mode when QMOD and QRD are both set in SPI_QCTL register. -
Page 539: Figure 21-9. Timing Diagram Of Read Operation In Quad-Spi Mode
GD32F20x User Manual Figure 21-9. Timing diagram of read operation in Quad-SPI mode Software writes Software writes SPI_DATA Hardware sets TBE SPI_DATA Software reads SPI_DATA sample RBNE MOSI D0[0] D1[4] D0[4] D1[0] MISO D0[5] D0[1] D1[5] D1[1] D0[6] D0[2] D1[6]... - Page 540 GD32F20x User Manual DMA function 21.3.6. The DMA function frees the application from data writing and reading process during transfer, thus improving the system efficiency. DMA function in SPI is enabled by setting DMATEN and DMAREN bits in SPI_CTL1 register.
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Page 541: Table 21-6. Spi Interrupt Requests
GD32F20x User Manual This bit is set when the transmit buffer is empty, the software can write the next data to the transmit buffer by writing the SPI_DATA register. Receive buffer not empty flag (RBNE) This bit is set when receive buffer is not empty, which means that one data is received and stored in the receive buffer, and software can read the data by reading the SPI_DATA register. -
Page 542: Figure 21-10. Block Diagram Of I2S
GD32F20x User Manual Interrupt Flag Description Clear Method Enable bit read SPI_STAT register. CRCERR CRC error Write 0 to CRCERR bit 21.4. I2S function overview I2S block diagram 21.4.1. Figure 21-10. Block diagram of I2S CK_I2S I2S_MCK Control Clock Generator... -
Page 543: Figure 21-11. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F20x User Manual I2S audio standards 21.4.3. The I2S audio standard is selected by the I2SSTD bits in the SPI_I2SCTL register. Four audio standards are supported, including I2S Phillips standard, MSB justified standard, LSB justified standard, and PCM standard. All standards except PCM handle audio data time-multiplexed on two channels (the left channel and the right channel). -
Page 544: Figure 21-13. I2S Phillips Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=0)
GD32F20x User Manual Figure 21-13. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD Figure 21-14. I2S Phillips standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 (channel left) -
Page 545: Figure 21-17. I2S Phillips Standard Timing Diagram (Dtlen=00, Chlen=1, Ckpl=0)
GD32F20x User Manual Figure 21-17. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 16-bit 0 16-bit data I2S_SD Figure 21-18. I2S Phillips standard timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 (channel left) -
Page 546: Figure 21-22. Msb Justified Standard Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32F20x User Manual Figure 21-22. MSB justified standard timing diagram (DTLEN=10, CHLEN=1, CKPL=1) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 32-bit data I2S_SD Figure 21-23. MSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 (channel left) -
Page 547: Figure 21-27. Lsb Justified Standard Timing Diagram (Dtlen=01, Chlen=1, Ckpl=0)
GD32F20x User Manual Figure 21-27. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 (channel left) frame 2 (channel right) I2S_CK I2S_WS 24-bit data 8-bit 0 I2S_SD Figure 21-28. LSB justified standard timing diagram (DTLEN=01, CHLEN=1, CKPL=1) frame 1 (channel left) -
Page 548: Figure 21-31. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=0, Ckpl=0)
GD32F20x User Manual configurable using the PCMSMOD bit in the SPI_I2SCTL register. The SPI_DATA register is handled in the exactly same way as that for I2S Phillips standard. The timing diagrams for each configuration of the short frame synchronization mode are shown below. -
Page 549: Figure 21-38. Pcm Standard Short Frame Synchronization Mode Timing Diagram (Dtlen=00, Chlen=1, Ckpl=1)
GD32F20x User Manual (DTLEN=01, CHLEN=1, CKPL=1) Figure 21-37. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=0) Figure 21-38. PCM standard short frame synchronization mode timing diagram (DTLEN=00, CHLEN=1, CKPL=1) frame 1 frame 2 16-bit data 16-bit 0 The timing diagrams for each configuration of the long frame synchronization mode are shown below. -
Page 550: Figure 21-42. Pcm Standard Long Frame Synchronization Mode Timing Diagram (Dtlen=10, Chlen=1, Ckpl=1)
GD32F20x User Manual (DTLEN=10, CHLEN=1, CKPL=0) Figure 21-42. PCM standard long frame synchronization mode timing diagram (DTLEN=10, CHLEN=1, CKPL=1) Figure 21-43. PCM standard long frame synchronization mode timing diagram (DTLEN=01, CHLEN=1, CKPL=0) frame 1 frame 2 13 bits 24-bit data 8-bit 0 Figure 21-44. -
Page 551: Figure 21-47. Block Diagram Of I2S Clock Generator
GD32F20x User Manual I2S clock 21.4.4. Figure 21-47. Block diagram of I2S clock generator 8-bit CK_I2S Configurable I2S_MCK MCKOEN Divider MCKOEN DIV4 CHLEN Frequency dividing ratio = DIV * 2 + OF I2S_CK DIV2 Figure 21-47. Block diagram of I2S... -
Page 552: Table 21-9. Direction Of I2S Interface Signals For Each Operation Mode
GD32F20x User Manual Operation 21.4.5. Operation modes The operation mode is selected by the I2SOPMOD bits in the SPI_I2SCTL register. There are four available operation modes, including master transmission mode, master reception mode, slave transmission mode, and slave reception mode. The direction of I2S interface Table 21-9. -
Page 553: Figure 21-48. I2S Initialization Sequence
GD32F20x User Manual Figure 21-48. I2S initialization sequence Start Configure the DIV [7:0] bits, the OF Is the MSTMOD bit is 1 bit, and the MCKOEN bit to define the I2S bitrate and master clock Configure the CKPL bit to define the clock polarity... - Page 554 GD32F20x User Manual transmission sequence begins. The data is parallel loaded into the 16-bit shift register, and shifted out serially to the I2S_SD pin, MSB first. The next data should be written to the SPI_DATA register, when the TBE flag is high.
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Page 555: Figure 21-49. I2S Master Reception Disabling Sequence
GD32F20x User Manual Figure 21-49. I2S master reception disabling sequence Start If DTLEN == 2b'00 && CHLEN == 2b'1 && I2SSTD ==2b'10 ? If DTLEN == 2b'00 && CHLEN == Wait for the second last RBNE 2b'1 && I2SSTD != 2b'10 ? - Page 556 GD32F20x User Manual I2S slave reception sequence The reception sequence in slave mode is similar to that in master mode. The differences between them are described below. In slave mode, the slave has to be enabled before the external master starts the communication.
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Page 557: Table 21-10. I2S Interrupt
GD32F20x User Manual Error flags There are two error flags: Transmission Underrun Error Flag (TXURERR) This condition occurs when the transmit buffer is empty when the valid SCK signal starts in slave transmission mode. Reception Overrun Error Flag (RXORERR) This condition occurs when the receive buffer is full and a newly incoming data has been completely received. - Page 558 GD32F20x User Manual 21.5. Register definition SPI0 base address: 0x4001 3000 SPI1/I2S1 base address: 0x4000 3800 SPI2/I2S2 base address: 0x4000 3C00 Control register 0 (SPI_CTL0) 21.5.1. Address offset: 0x00 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
- Page 559 GD32F20x User Manual received. FF16 Data frame format 0: 8-bit data frame format 1: 16-bit data frame format Receive only When BDEN is cleared, this bit determines the direction of transfer. 0: Full-duplex mode 1: Receive-only mode SWNSSEN NSS Software Mode Selection 0: NSS hardware mode.
- Page 560 GD32F20x User Manual 0: Capture the first data at the first clock transition 1: Capture the first data at the second clock transition Control register 1 (SPI_CTL1) 21.5.2. Address offset: 0x04 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit).
- Page 561 GD32F20x User Manual Status register (SPI_STAT) 21.5.3. Address offset: 0x08 Reset value: 0x0000 0002 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved Reserved TRANS RXORERR CONFERR CRCERR TXURERR I2SCH RBNE rc_w0 Bits Fields...
- Page 562 GD32F20x User Manual This bit is not used in SPI mode. I2SCH I2S channel side 0: The next data needs to be transmitted or the data just received is channel left. 1: The next data needs to be transmitted or the data just received is channel right.
- Page 563 GD32F20x User Manual This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved CRCPOLY[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value. 15:0 CRCPOLY[15:0] CRC polynomial register This register contains the CRC polynomial and it is used for CRC calculation. The default value is 0007h.
- Page 564 GD32F20x User Manual TX CRC register (SPI_TCRC) 21.5.7. Address offset: 0x18 Reset value: 0x0000 0000 This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved TCRC[15:0] Bits Fields Descriptions 31:16 Reserved Must be kept at reset value.
- Page 565 GD32F20x User Manual 0: SPI mode 1: I2S mode This bit should be configured when SPI mode or I2S mode is disabled. I2SEN I2S enable 0: I2S is disabled 1: I2S is enabled This bit is not used in SPI mode.
- Page 566 GD32F20x User Manual CHLEN Channel length 0: 16 bits 1: 32 bits The channel length must be equal to or greater than the data length. This bit should be configured when I2S mode is disabled. This bit is not used in SPI mode.
- Page 567 GD32F20x User Manual This register can be accessed by byte (8-bit) or half-word (16-bit) or word (32-bit). Reserved Reserved IO23_DRV QMOD Bits Fields Descriptions 31:3 Reserved Must be kept at reset value. IO23_DRV Drive IO2 and IO3 enable 0: IO2 and IO3 are not driven in single wire mode 1: IO2 and IO3 are driven to high in single wire mode This bit is only available in SPI0.
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Page 568: Figure 22-1. Dci Module Block Diagram
GD32F20x User Manual Digital camera interface(DCI) 22.1. Overview DCI is a parallel interface to capture video or picture from a camera. It supports various color space such as YUV/RGB, as well as compression format such as JPEG. 22.2. Characteristics ... -
Page 569: Figure 22-2. Hardware Synchronization Mode
GD32F20x User Manual synchronization information from pixel data, and then recover horizontal and vertical synchronization signals. The window timing module performs image cutting function. This module calculates a pixel’s position using synchronization signals either from DCI interface or embedded sync detection module and then decides whether this pixel data needs to be received according to the configuration of DCI_CWSPOS and DCI_CWSZ registers. -
Page 570: Figure 22-3. Hardware Synchronization Mode: Jpeg Format Supporting
GD32F20x User Manual DCI supports JPEG video/picture compression format in hardware synchronization mode. In JPEG mode (JM bit in DCI_CTL is set), the DCI_Vs is used to indicate start of a new frame, and DCI_Hs is used as stream data valid signal. -
Page 571: Table 22-2. Memory View In Byte Padding Mode
GD32F20x User Manual FR[1:0]=00, DCI captures each frame, and if FR[1:0]=01, DCI only captures every alternate frame. In continuous mode, software may clear the CAP bit any time when DCI is capturing data, but DCI doesn’t stop capture immediately. It always stops after a complete frame ends. Software should read back the CAP bit to know whether the DCI stops effectively. -
Page 572: Table 22-3. Memory View In Half-Word Padding Mode
GD32F20x User Manual Half-word padding mode Half-word padding is used if data width of DCI interface is configured into 10/12/14. In this mode each pixel data is extended into 16-bits length by filling zero at higher position, so the 32-bits width data buffer is able to hold two pixel data. DCI pushes the data buffer into pixel FIFO each time the buffer is full or line end. - Page 573 GD32F20x User Manual 22.7. Register definition DCI start address: 0x5005 0000 Control register (DCI_CTL) 22.7.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved DCIEN Reserved DCIF[1:0] FR[1:0] WDEN SNAP Bits...
- Page 574 GD32F20x User Manual 1: High level during blanking period Clock Polarity Selection 0: Capture at falling edge 1: Capture at rising edge Embedded Synchronous Mode 0: Embedded synchronous mode is disabled 1: Embedded synchronous mode is enabled JPEG Mode 0: JPEG mode is disabled...
- Page 575 GD32F20x User Manual 0: Not in vertical blanking period 1: In vertical blanking period HS line status 0: Not in horizontal blanking period 1: In horizontal blanking period Status register1 (DCI_STAT1) 22.7.3. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit)
- Page 576 GD32F20x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved ELIE VSIE ESEIE OVRIE EFIE Bits Fields Descriptions 31:5 Reserved Must keep the reset value ELIE End of Line Interrupt Enable 0: End of line flag won’t generate interrupt...
- Page 577 GD32F20x User Manual Bits Fields Descriptions 31:5 Reserved Must keep the reset value ELIF End of Line Interrupt Flag VSIF Vsync Interrupt Flag ESEIF Embedded Synchronous Error Interrupt Flag OVRIF FIFO Overrun Interrupt Flag EFIF End of Frame Interrupt Flag Interrupt flag clear register (DCI_INTC) 22.7.6.
- Page 578 GD32F20x User Manual Synchronization codes register (DCI_SC) 22.7.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) FE[7:0] LE[7:0] LS[7:0] FS[7:0] Bits Fields Descriptions 31:24 FE[7:0] Frame End Code in Embedded Synchronous Mode...
- Page 579 GD32F20x User Manual Cropping window start position register (DCI_CWSPOS) 22.7.9. Address offset: 0x20 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved WVSP[12:0] Reserved WHSP[13:0] Bits Fields Descriptions 31:29 Reserved Must keep the reset value...
- Page 580 GD32F20x User Manual 13:0 WHSZ[13:0] Window Horizontal Size WHSZ=X means X+1 pixels in a line DATA register (DCI_DATA) 22.7.11. Address offset: 0x28 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) DT3[[7:0] DT2[7:0] DT1[7:0] DT0[7:0] Bits...
- Page 581 GD32F20x User Manual TFT-LCD interface (TLI) 23.1. Overview The TLI (TFT-LCD Interface) module handles the synchronous LCD interface and provides pixel data, clock and timing signals for passive LCD display. It supports a wide variety of displays with fully programmable timing parameters. A built-in DMA engine continuously move data from system memory to TLI and then, output to an external LCD display.
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Page 582: Figure 23-1. Tli Module Block Diagram
GD32F20x User Manual Figure 23-1. TLI module block diagram 23.4. Signal description TLI provides a 24-bit RGB parallel display interface, which is shown in table below. Table 23-1. Pins of display interface provided by TLI Direction Name Width Description Output... - Page 583 GD32F20x User Manual VTSZ VASZ VBPSZ VPSZ HTSZ HASZ HBPSZ HPSZ PIXCLK RED[7:0], GREEN[7:0], BLUE[7:0] Pixel DMA function 23.5.2. Following the configuration of register module, the Pixel DMA reads pixel data from memory to the pixel buffer in internal PPU (Pixel Process Unit) continuously.
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Page 584: Table 23-2. Supported Pixel Formats
GD32F20x User Manual Pixel formats 23.5.3. The Pixel DMA pushes pixel data into PPU in word format and PPU (Pixel Process Unit) is responsible for converting various pixel formats into an internal ARGB8888 format. TLI supports up to eight pixel formats as shown in the table below. The PPF[2:0] in TLI_LxPPF register defines the pixel format. -
Page 585: Figure 23-3. Block Diagram Of Blending
GD32F20x User Manual define a window inside the layer. The pixel inside the window will keep its original value, while the pixel outside will be replaced with a default pixel defined in TLI_LxDC register. The blending units first blends Layer0 and BG Layer into a temporary layer, and then blends Layer1 and the temporary layer into destination layer. -
Page 586: Table 23-3. Status Flags
GD32F20x User Manual Dithering function 23.5.6. The dithering module adds a 2-bit pseudo-random value to each pixel channel. This function is able to make the image smoother when 18-bits interface is used to display a 24-bit data. Application may switch on this function using DFEN bit in TLI_CTL register. - Page 587 GD32F20x User Manual 23.6. Register definition TLI start address: 0x4001 6800 Synchronous pulse size register (TLI_SPSZ) 23.6.1. Address offset: 0x08 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved HPSZ[11:0] Reserved VPSZ[11:0] Bits Fields Descriptions...
- Page 588 GD32F20x User Manual Bits Fields Descriptions 31:28 Reserved Must keep the reset value 27:16 HBPSZ[11:0] Size of the horizontal back porch plus synchronous pulse The HBPSZ value should be configured to the pixels number of horizontal back porch and synchronous pulse minus 1.
- Page 589 GD32F20x User Manual This register has to be accessed by word (32-bit) Reserved HTSZ[11:0] Reserved VTSZ[11:0] Bits Fields Descriptions 31:28 Reserved Must keep the reset value 27:16 HTSZ[11:0] Horizontal total size of the display, including active area, back porch, synchronous...
- Page 590 GD32F20x User Manual 1: Vertical Synchronous Pulse active high DEPS Data Enable Polarity Selection 0: Data Enable active low 1: Data Enable active high CLKPS Pixel Clock Polarity Selection 0: Pixel Clock is TLI clock 1: Pixel Clock is inverted TLI clock...
- Page 591 GD32F20x User Manual Bits Fields Descriptions 31:2 Reserved Must keep the reset value Frame Blank Reload This bit is set by software and cleared by hardware after reloading 0: Reload disable 1: The layer configuration will be reloaded into core at frame blank...
- Page 592 GD32F20x User Manual Reserved LCRIE TEIE FEIE LMIE Bits Fields Descriptions 31:4 Reserved Must keep the reset value LCRIE Layer Configuration Reloaded Interrupt Enable 0: Layer configuration reloaded flag won’t generate an interrupt 1: Layer configuration reloaded flag will generate an interrupt...
- Page 593 GD32F20x User Manual 0: No transaction error flag 1: A transaction error on AHB bus occurs FIFO Error Flag 0: No FIFO error flag 1: A FIFO under-run error occurs The under-run error occurs when the value written in TLI_LxFLLEN and TLI_LxFTLN is less than required.
- Page 594 GD32F20x User Manual Line mark register (TLI_LM) 23.6.11. Address offset: 0x40 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Reserved Reserved LM[10:0] Bits Fields Descriptions 31:11 Reserved Must keep the reset value 10:0 LM[10:0] Line Mark value...
- Page 595 GD32F20x User Manual Reset value: 0x0000 000F This register has to be accessed by word (32-bit) Reserved Reserved Bits Fields Descriptions 31:4 Reserved Must keep the reset value Current HS status of the TLI Current VS status of the TLI...
- Page 596 GD32F20x User Manual Bits Fields Descriptions 31:5 Reserved Must keep the reset value LUTEN LUT Enable 0: LUT is disabled 1: LUT is enabled Reserved Must keep the reset value CKEYEN Color Keying Enable 0: Color keying is disabled 1: Color keying is enabled...
- Page 597 GD32F20x User Manual Reserved WBP[11:0] Reserved WTP[11:0] Bits Fields Descriptions 31:27 Reserved Must keep the reset value 26:16 WBP[11:0] Window Bottom Position 15:12 Reserved Must keep the reset value 11:0 WTP[11:0] Window Top Position Layer x color key register (TLI_LxCKEY) 23.6.17.
- Page 598 GD32F20x User Manual This register has to be accessed by word (32-bit) Reserved Reserved PPF[2:0] Bits Fields Descriptions 31:3 Reserved Must keep the reset value PPF[2:0] Packeted Pixel Format These bits configures the Packeted Pixel format 000: ARGB8888 001: RGB888...
- Page 599 GD32F20x User Manual Layer x default color register (TLI_LxDC) 23.6.20. Address offset: 0x9C+0x80*x x=0 or1 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) DCA[7:0] DCR[7:0] DCG[7:0] DCB[7:0] Bits Fields Descriptions 31:24 DCA[7:0] The Default Color ALPHA...
- Page 600 GD32F20x User Manual 011: Reserved 100: normalization Specified Alpha 101: Reserved 110: normalization Pixel Alpha x normalization Specified Alpha 111: Reserved Reserved Must keep the reset value ACF2[2:0] Alpha Calculation Factor 2 of Blending Method 000: Reserved 001: Reserved 010: Reserved...
- Page 601 GD32F20x User Manual Reserved FLL[13:0] Bits Fields Descriptions 31:30 Reserved Must keep the reset value 29:16 STDOFF[13:0] Frame Buffer Stride Offset This value defines the bytes number from start of a line to the start of next line 15:14 Reserved...
- Page 602 GD32F20x User Manual TG[7:0] TB[7:0] Bits Fields Descriptions 31:24 TADD[7:0] Look Up Table Write Address The entry at this address in LUT will be updated with the value of RED, GREEN and BLUE written 23:16 TR [7:0] Red Channel of a LUT entry...
- Page 603 GD32F20x User Manual Secure digital input/output interface (SDIO) 24.1. Overview The secure digital input/output interface (SDIO) defines the SD, SD I/O, MMC and CE-ATA card host interface, which provides command/data transfer between the AHB system bus and SD memory cards, SD I/O cards, Multimedia Card (MMC) and CE-ATA devices.
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Page 604: Figure 24-1 Sdio "No Response" And "No Data" Operations
GD32F20x User Manual host to a card. A command is transferred serially on the CMD line. Response: a response is a token which is sent from the card to the host as an answer to a previously received command. A response is transferred serially on the CMD line. -
Page 605: Figure 24-2. Sdio Multiple Blocks Read Operation
GD32F20x User Manual has an optional busy before it is ready to receive the data. Figure 24-2. SDIO multiple blocks read operation Figure 24-3. SDIO multiple blocks write operation Command Response Command Response Host to Device Device to Host Host to Device... -
Page 606: Figure 24-5. Sdio Sequential Write Operation
GD32F20x User Manual Figure 24-5. SDIO sequential write operation SDIO_CMD Command Response Command Response Host to Device Device to Host Host to Device Device to Host SDIO_DAT DATA STREAM Host to Device Data Write operation Data stop operation 24.4. SDIO function overview The following figure shows the SDIO structure. -
Page 607: Table 24-1. Sdio I/O Definitions
GD32F20x User Manual The SDIO_CLK frequency can vary between 0 MHz and 20 MHz for a Multimedia Card V3.31, between 0 and 48 MHz for a Multimedia Card V4.2, or between 0 and 25 MHz for an SD/SD I/O card. - Page 608 GD32F20x User Manual So, the FIFO can access by AHB bus. Command unit The command unit implements command transfer to the card. The data transfer flow is controlled by Command State Machine (CSM). After a write operation to SDIO_CMDCTL register and CSMEN in SDIO_CMDCTL register is 1, the command transfer starts. It firstly sends a command to the card.
- Page 609 GD32F20x User Manual → 1.Response Received in CE-ATA mode and interrupt CS_Waitcompl disabled and wait for CE-ATA Command Completion signal enabled → 2.Response Received in CE-ATA mode and interrupt CS_Pend disabled and wait for CE-ATA Command Completion signal disabled →...
- Page 610 GD32F20x User Manual DS_Send Transmit data to the card. → 1.Data block transmitted DS_Busy → 2.DSM disabled DS_Idle → 3.Data FIFO underrun error occurs DS_Idle → 4. Internal CRC error DS_Idle DS_Busy Waits for the CRC status flag. → 1.Receive a positive CRC status DS_WaitS →...
- Page 611 GD32F20x User Manual 1. Complete the card identification process 2. Increase the SDIO_CLK frequency 3. Send CMD7 to select the card and configure the bus width 4. Configure the DMA1 as follows: Enable DMA1 controller and clear any pending interrupts. Configure the DMA1_Channel3 source address register with the memory base address and DMA1_Channel3 destination address register with the SDIO_FIFO register address.
- Page 612 GD32F20x User Manual 24.5. Card function overview Card registers 24.5.1. Within the card interface registers are defined: OCR, CID, CSD, EXT_CSD, RCA, DSR and SCR. These can be accessed only by corresponding commands. The OCR, CID, CSD and SCR registers carry the card/content specific information, while the RCA and DSR registers are configuration registers storing actual configuration parameters.
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Page 613: Figure 24-7. Command Token Format
GD32F20x User Manual length, transfer rate or number of cards). The CSD register carries the information about the DSR register usage. The default value of the DSR register is 0x404. The host can use CMD4 to get the content of this register. -
Page 614: Table 24-3. Card Command Classes (Cccs)
GD32F20x User Manual a CRC7. Every command code word is terminated by the end bit (always 1). Command classes The command set of the Card system is divided into several classes (See Table 24-3. Card command classes (CCCs)). Each class supports a set of card functionalities. - Page 615 GD32F20x User Manual Card command class(CCC) Supported Class command description CMD5 CMD6 CMD7 CMD8 CMD9 CMD10 CMD11 CMD12 CMD13 CMD14 CMD15 CMD16 CMD17 CMD18 CMD19 CMD20 CMD23 CMD24 CMD25 CMD26 CMD27 CMD28 CMD29 CMD30 CMD32 CMD33 CMD34 CMD35 CMD36 CMD37...
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Page 616: Table 24-4. Basic Commands (Class 0)
GD32F20x User Manual Card command class(CCC) Supported Class command description CMD42 CMD50 CMD52 CMD53 CMD55 CMD56 CMD57 CMD60 CMD61 ACMD6 ACMD13 ACMD22 ACMD23 ACMD41 ACMD42 ACMD51 Note: 1.CMD1, CMD11, CMD14, CMD19, CMD20, CMD23, CMD26, CMD39 and CMD40 are only available for MMC. CMD5, CMD32-34, CMD50, CMD52, CMD53, CMD57 and ACMDx are only available for SD card. - Page 617 GD32F20x User Manual Response type argument Abbreviation Description index format Asks the card, in idle state, to [31:0] OCR send its Operating Conditions CMD1 SEND_OP_COND without busy Register contents in the response on the CMD line. Asks any card to send the CID...
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Page 618: Table 24-5. Block-Oriented Read Commands (Class 2)
GD32F20x User Manual Response type argument Abbreviation Description index format Addressed card sends its card- [31:16] RCA CMD9 SEND_CSD specific data (CSD) on the CMD [15:0] stuff bits line. Addressed card sends its card [31:16] RCA CMD10 SEND_CID identification (CID) on CMD the [15:0] stuff bits line. -
Page 619: Table 24-6. Stream Read Commands (Class 1) And Stream Write Commands (Class 3)
GD32F20x User Manual Response type argument Abbreviation Description index format set larger than 512Bytes, the card sets the BLOCK_LEN_ERROR bit. In the case of a Standard Capacity SD and MMC, this command reads a block of the size selected by the... -
Page 620: Table 24-7. Block-Oriented Write Commands (Class 4)
GD32F20x User Manual Table 24-7. Block-Oriented write commands (class 4) Response type argument Abbreviation Description index format See description in Table 24-5. [31:0] block CMD16 SET_BLOCKLEN Block-Oriented read length commands (class Defines the number of blocks which are going to be transferred... -
Page 621: Table 24-8. Erase Commands (Class 5)
GD32F20x User Manual Response type argument Abbreviation Description index format Note: 1.The data transferred shall not cross a physical block boundary unless WRITE_BLK_MISALIGN is set in the CSD. In the case that write partial blocks is not supported, then the block length=default block length (given in CSD). -
Page 622: Table 24-10. Lock Card (Class 7)
GD32F20x User Manual Response type argument Abbreviation Description index format Card does not support this command. If the card provides write protection features, this [31:0] data CMD29 CLR_WRITE_PROT command clears the write address protection bit of the addressed group. If the card provides write... -
Page 623: Table 24-12. I/O Mode Commands (Class 9)
GD32F20x User Manual Response type argument Abbreviation Description index format CCS bit is assigned to OCR[30]. Connect[1]/Disconnect[0] the [31:1] stuff bits SET_CLR_CAR ACMD42 50K pull-up resistor on [0]set_cd D_DETECT CD/DAT3 (pin 1) of the card. Reads the SD Configuration ACMD51... - Page 624 GD32F20x User Manual Response type argument Abbreviation Description index format [14:8] register and a register and provides address the data for writing if the write [7:0] register data flag is set. The R4 response contains data read from the addressed register if the write flag is cleared to 0.
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Page 625: Table 24-13. Switch Function Commands (Class 10)
GD32F20x User Manual Table 24-13. Switch function commands (class 10) Response type argument Abbreviation Description index format [31] Mode 0:Check function 1:Switch function [30:24] reserved [23:20] reserved for function group 6 (0h or Fh) Only for SD memory [19:16] reserved for and SD I/O. -
Page 626: Figure 24-8. Response Token Format
GD32F20x User Manual Responses format Responses have two formats, as show in Figure 24-8. Response Token Format, all responses are sent on the CMD line. The code length depends on the response type. Except R2 is 136 bits length, others are all 48 bits length. -
Page 627: Table 24-15. Response R2
GD32F20x User Manual CMD9. Only the bits [127..1] of the CID and CSD are transferred, the reserved bit [0] of these registers is replaced by the end bit of the response. Table 24-15. Response R2 Bit position [133:128] [127:1] Width ‘0’... -
Page 628: Table 24-19. Response R5 For Mmc
GD32F20x User Manual Width ‘11111 ‘11111 ‘0’ ‘0’ ‘000’ Value 1’ 11’ Number of descripti start transmissi Reserv Memory Stuff Reserv S18A on bit Present Bits functions R5 (Interrupt request) For MMC only. Code length is 48 bits. If the response is generated by the host, the RCA field in the argument will be 0x0. -
Page 629: Figure 24-9. 1-Bit Data Bus Width
GD32F20x User Manual R7 (Card interface condition) For SD memory only. Code length is 48 bits. The card support voltage information is sent by the response of CMD8. Bits 19-16 indicate the voltage range that the card supports. The card that accepted the supplied voltage returns R7 response. - Page 630 GD32F20x User Manual 8-bit data packet format Figure 24-11. 8-bit data bus width Two status fields of the card 24.5.5. The SD Memory supports two status fields and others just support the first one: Card Status: Error and state information of a executed command, indicated in the response SD Status: Extended status field of 512 bits that supports special features of the SD Memory Card and future Application-Specific features.
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Page 631: Table 24-23. Card Status
GD32F20x User Manual Clear condition •A: According to current state of the card. •B: Always related to the previous command. Reception of a valid command will clear it (with a delay of one command). •C: Cleared by read Table 24-23. Card status... - Page 632 GD32F20x User Manual Bits Identifier Type Value Description Clear Condition ’1’= failure applied but failed to correct the data. ’0’= no error CC_ERROR Internal card controller error. ’1’= error ’0’= no error ERROR A general or an unknown ’1’= error error occurred during the operation.
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Page 633: Table 24-24. Sd Status
GD32F20x User Manual Bits Identifier Type Value Description Clear Condition 4 = transfer visible to the host in the 5 = send data response to the next 6 = receive data command. The four bits are 7 = programming interpreted as a binary coded 8 = disconnect number between 0 and 15. - Page 634 GD32F20x User Manual Bits Identifier Type Value Description Clear Condition ‘01’= reserved data bus width that was ‘10’= 4 bit width defined by ‘11’= reserved SET_BUS_WIDTH command ’0’= Not in the SECURED_MODE Card is in Secured Mode of operation (refer to the “SD mode ’1’= In Secured...
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Page 635: Table 24-25. Performance Move Field
GD32F20x User Manual Bits Identifier Type Value Description Clear Condition [311:0] reserved for manufacturer SIZE_OF_PROTECTED_AREA Setting this field differs between SDSC and SDHC/SDXC. In case of SDSC Card, the capacity of protected area is calculated as follows: Protected Area = SIZE_OF_PROTECTED_AREA_* MULT * BLOCK_LEN. -
Page 636: Table 24-26. Au_Size Field
GD32F20x User Manual This 4-bit field indicates AU Size and the value can be selected from 16 KB. Table 24-26. AU_SIZE field AU_SIZE Value Definition Not Defined 16 KB 32 KB 64 KB 128 KB 256 KB 512 KB 1 MB... -
Page 637: Table 24-29. Erase Timeout Field
GD32F20x User Manual ERASE_TIMEOUT This 6-bit field indicates the T and the value indicates erase timeout from offset when ERASE multiple AUs are erased as specified by ERASE_SIZE. The range of ERASE_TIMEOUT can be defined as up to 63 seconds and the card manufacturer can choose any combination of... - Page 638 GD32F20x User Manual identification clock rate F (400 kHz). Card reset The command GO_IDLE_STATE (CMD0) is the software reset command and sets MMC and SD memory card into Idle State regardless of the current card state. The reset command (CMD0) is only used for memory or the memory portion of Combo cards. In order to reset an I/O only card or the I/O portion of a combo card, use CMD52 to write 1 to the RES bit in the CCCR.
- Page 639 GD32F20x User Manual Send CMD5 first. If a response is received, then the card is SD I/O – If not, send ACMD41; if a response is received, then the card is SD. – Otherwise, the card is an MMC or CE-ATA.
- Page 640 GD32F20x User Manual the card. The block consists of start bits (1 or 4 bits LOW), data block, CRC and end bits(1 or 4 bits HIGH). If the CRC fails, the card indicates the failure on the SDIO_DAT line and the transferred data are discarded and not written, and all further transmitted blocks are ignored.
- Page 641 GD32F20x User Manual flag is set. Write data to SDIO_FIFO. Software should look for data error interrupts. If required, software can terminate the data transfer by sending the STOP command (CMD12). When a DTEND interrupt is received, the data transfer is over. For an open-ended block transfer, if the byte count is 0, the software must send the STOP command.
- Page 642 GD32F20x User Manual single-block and multiple-block transfers. For CE-ATA, first using CMD60 to write the ATA task file, then using CMD61 to read the data. After writing to the CMD register, the host starts executing the command, when the command is sent to the bus, the CMDRECV flag is set.
- Page 643 GD32F20x User Manual the card may not be able to process the data and will stop programming, and while ignoring all further data transfer, wait (in the Receive-data-State) for a stop command. As the host sends CMD12, the card will respond with the TXURE bit set and return to Transfer state Stream read There is a stream oriented data transfer controlled by READ_DAT_UNTIL_STOP (CMD11).
- Page 644 GD32F20x User Manual write blocks which are the basic writable units of the card. The size of the Erase Group is a card specific parameter and defined in the CSD. The host can erase a contiguous range of Erase Groups. Starting the erase process is a three steps sequence.
- Page 645 GD32F20x User Manual Protection management 24.6.8. In order to allow the host to protect data against erase or write, three methods for the cards are supported in the card: CSD register for card protection (optional) The entire card may be write protected by setting the permanent or temporary write protect bits in the CSD.
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Page 646: Table 24-31. Lock Card Data Structure
GD32F20x User Manual Table 24-31. Lock card data structure Byte Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved(all set to 0) ERASE LOCK_UNLOCK CLR_PWD SET_PWD PWDS_LEN …… Password data(PWD) PWDS_LEN+1 ERASE: 1 Defines Forced Erase Operation. In byte 0, bit 3 will be set to 1 (all other bits shall be 0). - Page 647 GD32F20x User Manual Reset the password Select a card (CMD7), if not previously selected. Define the block length (CMD16), given by the 8-bit card lock/unlock mode, the 8-bit password size (in bytes), and the number of bytes of the currently used password.
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Page 648: Figure 24-12. Read Wait Control By Stopping Sdio_Clk
GD32F20x User Manual Read Wait operation Suspend/resume operation Interrupts The SD I/O supports these operations only if the SDIO_DATACTL[11] bit is set, except for read suspend that does not need specific hardware implementation. SD I/O read wait operation The optional Read Wait (RW) operation is defined only for the SD 1-bit and 4-bit modes. -
Page 649: Figure 24-14. Function2 Read Cycle Inserted During Function1 Multiple Read Cycle
GD32F20x User Manual SDIO_DATACTL[8] = 1) and data direction is from card to SD I/O (SDIO_DATACTL[1] = 1), the DSM directly moves from Idle to Read Wait. In Read Wait the DSM drives SDIO_DAT[2] to 0 after 2 SDIO_CLK clock cycles. In this state, when you set the RWSTOP bit (SDIO_DATACTL[9]), the DSM remains in Wait for two more SDIO_CLK clock cycles to drive SDIO_DAT[2] to 1 for one clock cycle. -
Page 650: Figure 24-15. Read Interrupt Cycle Timing
GD32F20x User Manual bit SD mode, is used to signal the card’s interrupt to the host. The use of interrupt is optional for each card or function within a card. The SD I/O interrupt is “level sensitive”, that is, the interrupt line shall be held active (low) until it is either recognized and acted upon by the host or de-asserted due to the end of the Interrupt Period. -
Page 651: Figure 24-17. Multiple Block 4-Bit Read Interrupt Cycle Timing
GD32F20x User Manual Figure 24-17. Multiple block 4-Bit read interrupt cycle timing SDIO_CLK Command read data Response DAT0 Data Data DAT1 Data Data 2 CLK 2 CLK DAT1(mode) interrupt data data data Figure 24-18. Multiple block 4-Bit write interrupt cycle timing CE-ATA specific operations 24.7.2. -
Page 652: Figure 24-19. The Operation For Command Completion Disable Signal
GD32F20x User Manual issuing the command completion signal disable. The host shall only issue the command completion signal disable when it has received an R1b response for an outstanding RW_MULTIPLE_BLOCK (CMD61) command. Command completion signal disable is sent 8 bit cycles after the reception of a short response if the ‘enable CMD completion’... - Page 653 GD32F20x User Manual 24.8. Register definition SDIO base address: 0x4001 8000 Power control register (SDIO_PWRCTL) 24.8.1. Address offset: 0x00 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved PWRCTL[1:0] Bits Fields Descriptions 31:2 Reserved Must be kept at reset value PWRCTL[1:0] SDIO power control bits.
- Page 654 GD32F20x User Manual Bits Fields Descriptions DIV[8] MSB of Clock division This field defines the MSB division between the input clock (SDIOCLK) and the output clock, refer to bit 7:0 of SDIO_CLKCTL 30:15 Reserved Must be kept at reset value...
- Page 655 GD32F20x User Manual Command argument register (SDIO_CMDAGMT) 24.8.3. Address offset: 0x08 Reset value: 0x0000 0000 This register defines 32 bit command argument, which will be used as part of the command (bit 39 to bit 8). This register has to be accessed by word(32-bit)
- Page 656 GD32F20x User Manual 1: CE-ATA enable NINTEN No CE-ATA Interrupt (CE-ATA only) This bit defines if there is CE-ATA interrupt or not. This bit is only used when CE- ATA card. 0: CE-ATA interrupt enable 1: CE_ATA interrupt disable ENCMDC CMD completion signal enabled (CE-ATA only) This bit defines if there is command completion signal or not in CE-ATA card.
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Page 657: Table 24-32. Sdio_Respx Register At Different Response Type
GD32F20x User Manual Command index response register (SDIO_RSPCMDIDX) 24.8.5. Address offset: 0x10 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RSPCMDIDX[5:0] Bits Fields Descriptions 31:6 Reserved Must be kept at reset value RSPCMDIDX[5:0] Last response command index Read-only bits field. - Page 658 GD32F20x User Manual Register Short response Long response SDIO_RESP1 reserved Card response [95:64] SDIO_RESP2 reserved Card response [63:32] SDIO_RESP3 reserved Card response [31:1],plus bit 0 Data timeout register (SDIO_DATATO) 24.8.7. Address offset: 0x24 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
- Page 659 GD32F20x User Manual Bits Fields Descriptions 31:25 Reserved Must be kept at reset value 24:0 DATALEN[24:0] Data transfer length This register defined the number of bytes to be transferred. When the data transfer starts, the data counter loads this register and starts decrement.
- Page 660 GD32F20x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value IOEN SD I/O specific function enable(SD I/O only) 0: Not SD I/O specific function 1: SD I/O specific function RWTYPE Read wait type(SD I/O only) 0: Read Wait control using SDIO_DAT[2]...
- Page 661 GD32F20x User Manual 1: Read data from card. DATAEN Data transfer enable bit Write 1 to this bit to start data transfer regardless this bit is 0 or 1. The DSM moves to Readwait state if RWEN is set or to the WaitS, WaitR state depend on DATADIR bit.
- Page 662 GD32F20x User Manual RXDTVA Reserved ATAEND SDIOINT TXDTVAL DTBLK DTTMOU DTCRC CCRCER RXRUN TXRUN CMDRUN STBITE DTEND RXORE TXURE SEND RECV TMOUT Bits Fields Descriptions 31:24 Reserved Must be kept at reset value ATAEND CE-ATA command completion signal received (only for CMD61)
- Page 663 GD32F20x User Manual DTTMOUT Data timeout The data timeout period depends on the SDIO_DATATO register. CMDTMOUT Command response timeout The command timeout period has a fixed value of 64 SDIO_CLK clock periods. DTCRCERR Data block sent/received (CRC check failed) CCRCERR...
- Page 664 GD32F20x User Manual CMDRECVC CMDRECV flag clear bit Write 1 to this bit to clear the flag. RXOREC RXORE flag clear bit Write 1 to this bit to clear the flag. TXUREC TXURE flag clear bit Write 1 to this bit to clear the flag.
- Page 665 GD32F20x User Manual TXDTVALIE Data valid in transmit FIFO interrupt enable Write 1 to this bit to enable the interrupt. RFEIE Receive FIFO empty interrupt enable Write 1 to this bit to enable the interrupt. TFEIE Transmit FIFO empty interrupt enable Write 1 to this bit to enable the interrupt.
- Page 666 GD32F20x User Manual Write 1 to this bit to enable the interrupt. CMDTMOUTIE Command response timeout interrupt enable Write 1 to this bit to enable the interrupt. DTCRCERRIE Data CRC fail interrupt enable Write 1 to this bit to enable the interrupt.
- Page 667 GD32F20x User Manual Bits Fields Descriptions 31:0 FIFODT[31:0] Receive FIFO data or transmit FIFO data These bits are the data of receive FIFO or transmit FIFO. Write to or read from this register is write data to FIFO or read data from FIFO.
- Page 668 GD32F20x User Manual External memory controller (EXMC) 25.1. Overview The external memory controller EXMC, is used as a translator for CPU to access a variety of external memory, it automatically converts AMBA memory access protocol into a specific memory access protocol defined in the configuration register, such as SRAM, ROM, NOR Flash, PSRAM, NAND Flash, PC Card and SDRAM.
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Page 669: Figure 25-1. The Exmc Block Diagram
GD32F20x User Manual Figure 25-1. The EXMC block diagram AHB Bus Interface HCLK EXMC from clock interrupt controller to NVIC EXMC Configuration Register NOR- SDRAM NAND-Flash/PC Card Flash/PSRAM Controller Controller Controller NAND PC Card NOR/PSR PSRAM/ SDRAM Share NOR/PSRA Pins... -
Page 670: Figure 25-2. Exmc Memory Banks
GD32F20x User Manual External device address mapping 25.3.3. Figure 25-2. EXMC memory banks Supported memory Address Banks type 0x6000 0000 NOR/PSRAM Bank0(4x64M) SQPI-PSRAM 0x6FFF FFFF 0x7000 0000 Bank1(256M) 0x7FFF FFFF NAND 0x8000 0000 Bank2(256M) 0x8FFF FFFF 0x9000 0000 Bank3(256M) PC Card... -
Page 671: Figure 25-3. Four Regions Of Bank0 Address Mapping
GD32F20x User Manual NOR/PSRAM address mapping Figure 25-3. Four regions of bank0 address mapping reflects the address mapping of the four regions of bank0. Internal AHB address lines HADDR [27:26] bit are used to select the four regions. Figure 25-3. Four regions of bank0 address mapping... -
Page 672: Figure 25-4. Nand/Pc Card Address Mapping
GD32F20x User Manual Figure 25-4. NAND/PC card address mapping EXMC Memory Memory Space Address Bank 0x7000_0000 Common Memory 0x73FF_FFFF Space Bank1 0x7800_0000 Attribute Memory Space 0x7BFF_FFFF 0x8000_0000 Common Memory Space 0x83FF_FFFF Bank2 0x8800_0000 Attribute Memory Space 0x8BFF_FFFF 0x9000_0000 Common Memory... -
Page 673: Figure 25-6. Sdram Address Mapping
GD32F20x User Manual When HADDR [17:16] = 00, the data area is selected. When HADDR [17:16] = 01, the command area is selected. When HADDR [17:16] = 1X, the address area is selected. Application software uses these three areas to access NAND Flash, their definitions are as follows. -
Page 674: Table 25-2. Nor Flash Interface Signals Description
GD32F20x User Manual Maximum memory Memory width Internal bank Row address Column address capacity 256 Mbytes: 32-bit HADDR[27:26] HADDR[25:13] HADDR[12:2] 4 x 8K x 2K x 4 NOR/PSRAM controller 25.3.4. NOR/PSRAM memory controller controls bank0, which is designed to support NOR Flash, PSRAM, SRAM, ROM and honeycomb RAM external memory. -
Page 675: Table 25-4. Sqpi-Psram Signal Description
GD32F20x User Manual EXMC Pin Direction Mode Functional description EXMC_D[15:0] Input/output Async/Sync Data Bus Chip selection, EXMC_NE[x] Output Async/Sync x=0/1/2/3 EXMC_NOE Output Async/Sync Read enable EXMC_NWE Output Async/Sync Write enable EXMC_NWAIT Input Async/Sync Wait input signal Latch enable (address EXMC_NL(NADV) -
Page 676: Table 25-6. Nor / Psram Controller Timing Parameters
GD32F20x User Manual Memory Memory Access Mode Transaction Transaction Comments Size Size EXMC_NBL[1:0] Async Async Split into 2 EXMC Async accesses Split into 2 EXMC Async accesses Sync Sync Use of byte lanes Sync EXMC_NBL[1:0] Sync Sync Async Async Split into 2 EXMC... -
Page 677: Table 25-7. Exmc_Timing Models
GD32F20x User Manual Parameter Function Access mode Unit Min Max AHLD Address hold time Async(muxed) HCLK ASET Address setup time Async HCLK Table 25-7. EXMC_timing models Timing Extend Write timing Read timing Mode description model mode parameter parameter DSET DSET... -
Page 678: Figure 25-7. Mode 1 Read Access
GD32F20x User Manual Figure 25-7. Mode 1 read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Data Setup Time (ASET HCLK) (DSET HCLK) Figure 25-8. Mode 1 write access... -
Page 679: Figure 25-9. Mode A Read Access
GD32F20x User Manual Bit Position Bit Name Reference Setting Value Depends on memory NRTP Depends on memory, except 2(Nor Flash) NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 0x0000 29-28 ASYNCMOD No effect 27-24 DLAT No effect 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to EXMC_NE[x]... -
Page 680: Figure 25-10. Mode A Write Access
GD32F20x User Manual Figure 25-10. Mode A write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Byte Lane Select (EXMC_NBL[1:0]) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET HCLK) (WDSET HCLK) -
Page 681: Figure 25-11. Mode 2/B Read Access
GD32F20x User Manual Bit Position Bit Name Reference Setting Value EXMC_NE[x] falling edge Depends on memory and user (DSET+1 HCLK for 15-8 DSET write, DSET HCLK for read) AHLD No effect ASET Depends on memory and user EXMC_SNWTCFGx(Write) 31-30 Reserved... -
Page 682: Figure 25-13. Mode B Write Access
GD32F20x User Manual Figure 25-13. Mode B write access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time 1 HCLK (WASET HCLK) (WDSET HCLK) Table 25-10. Mode 2/B related registers configuration... -
Page 683: Figure 25-14. Mode C Read Access
GD32F20x User Manual Bit Position Bit Name Reference Setting Value ASET Depends on memory and user EXMC_SNWTCFGx(Write in mode B) 31-30 Reserved 0x0000 29-28 WASYNCMOD Mode B:0x1 27-24 DLAT No effect 23-20 CKDIV No effect 19-16 Reserved 0x000 15-8 WDSET... -
Page 684: Table 25-11. Mode C Related Registers Configuration
GD32F20x User Manual Table 25-11. Mode C related registers configuration Bit Position Bit Name Reference Setting Value EXMC_SNCTLx 31-20 Reserved 0x000 SYNCWR 18-16 Reserved ASYNCWTEN Depends on memory EXMODEN NRWTEN WREN Depends on user NRWTCFG No effect WRAPEN NRWTPOL Meaningful only when the bit 15 is set to 1... -
Page 685: Figure 25-16. Mode D Read Access
GD32F20x User Manual Figure 25-16. Mode D read access Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Memory Output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time (ASET HCLK) (AHLD HCLK) (DSET HCLK) Figure 25-17. -
Page 686: Figure 25-18. Multiplex Mode Read Access
GD32F20x User Manual Bit Position Bit Name Reference Setting Value Depends on memory NRTP Depends on memory NRMUX NRBKEN EXMC_SNTCFGx 31-30 Reserved 29-28 ASYNCMOD Mode D:0x3 Don’t care 27-24 DLAT 23-20 CKDIV No effect Time between EXMC_NE[x] rising edge to... -
Page 687: Figure 25-19. Multiplex Mode Write Access
GD32F20x User Manual Figure 25-19. Multiplex mode write access Address Address[25:16] (EXMC_A[25:16]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Data Address[15:0] EXMC output (EXMC_D[15:0]) Address Setup Time Address Hold Time Data Setup Time 1 HCLK... -
Page 688: Figure 25-20. Read Access Timing Diagram Under Async-Wait Signal Assertion
GD32F20x User Manual Bit Position Bit Name Reference Setting Value ASET Depends on memory and user Wait timing of asynchronous communication Wait feature is controlled by the bit ASYNCWAIT in register EXMC_SNCTLx. During extern memory access, data setup phase will be automatically extended by the active EXMC_NWAIT signal if ASYNCWAIT bit is set. -
Page 689: Figure 25-21. Write Access Timing Diagram Under Async-Wait Signal Assertion
GD32F20x User Manual Figure 25-21. Write access timing diagram under async-wait signal assertion Address (EXMC_A[25:0]) Chip Enable (EXMC_NEx) Wait (EXMC_NWAIT) NRWTPOL = 0 Wait (EXMC_NWAIT) NRWTPOL = 1 Write Enable (EXMC_NWE) Data EXMC Output (EXMC_D[15:0]) Address Setup Time Data Setup Time... -
Page 690: Figure 25-22. Read Timing Of Synchronous Multiplexed Burst Mode
GD32F20x User Manual The valid polarity of EXMC_NWAIT: NRWTPOL= 1: valid level of EXMC_NWAIT signal is high. NRWTPOL= 0: valid level of EXMC_NWAIT signal is low. In synchronous burst mode, EXMC_NWAIT signal has two kinds of configurations: NRWTCFG = 1: When EXMC_NWAIT signal is active, current cycle data is not valid. - Page 691 GD32F20x User Manual Bit Position Bit Name Reference Setting Value 31-20 Reserved 0x000 SYNCWR No effect 18-16 Reserved ASYNCWTEN EXMODEN NRWTEN Depends on memory WREN No effect NRWTCFG Depends on memory WRAPEN NRWTPOL Depends on memory SBRSTEN 0x1，burst read enable...
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Page 692: Figure 25-23. Write Timing Of Synchronous Multiplexed Burst Mode
GD32F20x User Manual Figure 25-23. Write timing of synchronous multiplexed burst mode HCLK Clock (EXMC_CLK) Address Address [25:16] (EXMC_A[25:16]) Chip Enable (EXMC_NEx) Address Valid (EXMC_NADV) Output Enable (EXMC_NOE) Write Enable (EXMC_NWE) Wait (EXMC_NWAIT) Data EXMC EXMC EXMC Address [15:0] (EXMC_D[15:0]) -
Page 693: Table 25-16. Spi/Qpi Interface
GD32F20x User Manual Bit Position Bit Name Reference Setting Value 23-20 CKDIV The figure above: 0x1,EXMC_CLK=2HCLK 19-16 BUSLAT No effect 15-8 DSET No effect AHLD No effect ASET No effect SPI/QPI-PSRAM access timing diagram SPI/QPI-PSRAM is controlled by EXMC memory bank0, region 0 only, it is a PSRAM with SPI and QPI interface, consisting of 6 IOs, the chip-enable, clock, and 4 data IOs, and they are summarized in the following table. -
Page 694: Figure 25-24. Spi-Psram Access
GD32F20x User Manual SPI-PSRAM access timing In SPI mode, the EXMC can communicate with the external memory through the SPI protocol, with 4 IOs, the clock, chip-enable, an input and an output. As shown in the diagram below, the command is first sent serially through the EXMC’s data output line, which sets the external memory operating mode, followed by the address section which could be of various size, depending on EXMC’s configuration, and lastly, the read or write data. -
Page 695: Figure 25-25. Sqpi-Psram Access
GD32F20x User Manual Figure 25-25. SQPI-PSRAM access Clock (EXMC_CLK) Chip Enable (EXMC_NEx) Data (EXMC_D[0]) Command Data (EXMC_D[1]) Data (EXMC_D[2]) Data (EXMC_D[3]) Command, width Address, 24-bits Wait Data 1 Data 2 depends on CMDBIT QPI-PSRAM access timing The only difference between SQPI and QPI mode is that the command is sent parallel on the 4 data IO lines as shown in the diagram below. -
Page 696: Table 25-17. 8-Bit Or 16-Bit Nand Interface Signal
GD32F20x User Manual NAND flash or PC card interface function Table 25-17. 8-bit or 16-bit NAND interface signal EXMC Pin Direction Functional description EXMC_A[17] Output NAND Flash address latch (ALE) EXMC_A[16] Output NAND Flash command latch (CLE) EXMC_D[7:0]/ 8-bit multiplexed, bidirectional address/data bus... -
Page 697: Figure 25-27. Access Timing Of Common Memory Space Of Nand Flash Or Pc Card Controller
GD32F20x User Manual Memory Mode AHB transaction size Comments Async Async Async Automatically split into 2 EXMC Async accesses NAND flash or PC card controller timing EXMC can generate the appropriate signal timing for NAND Flash, PC Cards and other devices. - Page 698 GD32F20x User Manual controller Clock (EXMC_CLK) Address (EXMC_A[25:0]) Chip Enable (EXMC_NCE) EXMC_NREG EXMC_NIORD EXMC_NIOWR EXMC_NWR EXMC_NOE Write Data Read Data Valid COMSETx + 1 HCLK COMHLDx HCLK COMHIZx HCLK COMWAITx + 1 HCLK NAND flash operation When EXMC sends command or address to NAND Flash, it needs to use the command latch signal (A[16]) or address latch signal (EXMC_A[17]), namely, the CPU needs to perform write operation in particular address.
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Page 699: Figure 25-28. Access To None "Nce Don't Care" Nand Flash
GD32F20x User Manual Taking TOSHIBA128 M x 8 bit NAND Flash as an example: Figure 25-28. Access to none "NCE don’t care" NAND Flash Chip Enable (EXMC_NCE) Command Latch Enable (EXMC_A[16]) Address Latch Enable (EXMC_A[17]) Write Enable (EXMC_NWE) Output Enable... - Page 700 GD32F20x User Manual PC/CF card access EXMC Bank3 is used exclusively for PC/CF Card, both memory and IO mode access are supported. This bank is divided further into three sub spaces, memory, attribute and IO space. EXMC_NCE3_0 and EXMC_NCE3_1 are the byte select signals, when only EXMC_NCE3_0...
- Page 701 GD32F20x User Manual SDRAM controller 25.3.6. Characteristics Two independent SDRAM devices. 8-,16- or 32-bit data bus width. Up to 13-bits Row Address, 11-bits Column Address and 2-bits internal banks address. Supported memory size: 4x16Mx32bit(256 MB), 4x16Mx16bit (128 MB) and 4x16Mx8bit (64 MB).
- Page 702 GD32F20x User Manual SDRAM control register EXMC_SDCTLx. Due to the volatile nature of SDRAM, periodic refresh cycle is necessary to maintain the stored information. Two refresh mode could be selected, self-refresh and auto-refresh mode. Self-refresh mode is typically set in low power mode when EXMC is suspended, refresh is provided by the SDRAM and timed by its internal counter.
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Page 703: Figure 25-29. Sdram Controller Block Diagram
GD32F20x User Manual Figure 25-29. SDRAM controller block diagram D[31:0] WADDR FIFO NBL[3:0] WDATA REFRESH SDCK FIFO TIMER GENERATOR ref_req ref_ok RADDR FIFO AHBS_IF_MEM ack_req ack_ok RDATA SDNE[1:0] FIFO EXTERNAL COMMAND SDRAM rw_req TIMERS ACTIVE rw_ok CACHE SIGNAL pre_req ADDRESS... -
Page 704: Table 25-22. Io Definition Of Sdram Controller
GD32F20x User Manual A[n] A[10] A[m] Command Mode Mode Load mode register SDRAM controller operation sequence IO configuration SDRAMC IO port must be configured first to interface with external SDRAM, otherwise it is left as general purpose IOs, and could be utilized by other modules. IO ports related to SDRAM operations are summarized in the following table. - Page 705 GD32F20x User Manual SDRAM devices, this is done by writing 0b001 to the CMD bits in the EXMC_SDCMD register, DS0 and DS1 selected which device will accept the command and start receiving EXMC_SDCLK. Power-up delay: typical delay is around 100us.
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Page 706: Figure 25-30. Burst Read Operation
GD32F20x User Manual Once the row has been activated, read/write commands are possible to that row. Activation requires a minimum amount of time, called the row-to-column delay (RCD) before read/write to it may occur. This time, rounded up to the next multiple of the clock period, specifies the minimum number of wait cycles between an active command and a read/write command. -
Page 707: Figure 25-31. Data Sampling Clock Delay Chain
GD32F20x User Manual A clock delay chain module is added after the HCLK input to the signal generator, this delayed clock is used as the sampling clock of the input data. The delay chain is controlled by the EXMC_SDRSCTL register, RSEN bit select whether the HCLK output is delay at all, SSCR bit select whether 1 additional HCLK cycle is added to the total delay, and SDSC select how many delay cells is add, the number of delay cell could be added is within 0 and 15. -
Page 708: Figure 25-33. Read Access When Fifo Not Hit (Brstrd=1, Cl=2, Sdclk=2, Piped=2)
GD32F20x User Manual accesses on the SDRAM memory according to the ratio of the data width between the AHB bus and the SDRAM memory interface. Inside the RW split module, there are two write FIFOs, which buffers the data and address of the AHB write commands. -
Page 709: Figure 25-34. Read Access When Fifo Hit (Brstrd=1)
GD32F20x User Manual Figure 25-34. Read access when FIFO hit (BRSTRD=1) AHB Master IF Data2 @0x8 Read @0x8 Data1 Data2 Data3 @0x4 @0x8 @0xC Read FIFO SDRAM Memroy The read FIFO will be flushed and ready to be filled with new data, when a write access or a precharge command occurs. -
Page 710: Figure 25-35. Cross Boundary Read Operation
GD32F20x User Manual Figure 25-35. Cross boundary read operation Clock (EXMC_SDCLK) Row n Address (EXMC_A[12:0]) Chip Enable (EXMC_SDNEx) Row Address Strobe (EXMC_NRAS) Column Address Strobe (EXMC_NCAS) Write Enable (EXMC_SDNWE) Data Data0 Data1 Data2 Data0 Data1 (EXMC_D[31:0]) RPD = 3 RCD = 3... -
Page 711: Figure 25-37. Process For Self-Refresh Entry And Exit
GD32F20x User Manual is performed, and this supports all row, column, and bus width configuration. When the current bank is the last bank, and row, column, and bus width are configured as, 13-bit, 11-bit, and 32-bit respectively, EXMC continues to read/write from the second SDRAM device (SDRAM device 1), assuming that the current SDRAM is device 0. -
Page 712: Figure 25-38. Process For Power-Down Entry And Exit
GD32F20x User Manual Figure 25-38. Process for power-down entry and exit Clock (EXMC_SDCLK) Clock Enable (EXMC_SDCKE]) Command Active Power-down Entry Power-down Exit Status and interrupt The not ready status NRDY bit in EXMC_SDSTAT register specifies whether the SDRAM controller is ready for a new command, this bit is cleared immediately after the command in the SDRAMC’s internal register is sent. - Page 713 GD32F20x User Manual 25.4. Register definition EXMC base address: 0xA000 0000 NOR/PSRAM controller registers 25.4.1. SRAM/NOR flash control registers (EXMC_SNCTLx) (x=0, 1, 2, 3) Address offset: 0x00 + 8 * x, (x = 0, 1, 2, and 3) Reset value: 0x0000 30DA This register has to be accessed by word (32-bit).
- Page 714 GD32F20x User Manual 1: Enabled write in the bank by the EXMC (default after reset) NRWTCFG NWAIT signal configuration, only work in synchronous mode 0: NWAIT signal is active one data cycle before wait state 1: NWAIT signal is active during wait state...
- Page 715 GD32F20x User Manual Reserved ASYNCMOD[1:0] DLAT[3:0] CKDIV[3:0] BUSLAT[3:0] DSET[7:0] AHLD[3:0] ASET[3:0] Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. 29:28 ASYNCMOD[1:0] Asynchronous access mode The bits are valid only when the EXMEN bit in the EXMC_SNCTLx register is 1.
- Page 716 GD32F20x User Manual and multiplexed mode. 0x0: Reserved 0x1: Address hold time = 2 * HCLK …… 0xF: Address hold time = 16 * HCLK ASET[3:0] Address setup time This field is used to set the time of address setup phase.
- Page 717 GD32F20x User Manual 0x1: EXMC_CLK period = 2 * HCLK period …… 0xF: EXMC_CLK period = 16 * HCLK period 19:16 Reserved Must be kept at reset value. 15:8 WDSET[7:0] Data setup time This field is meaningful only in asynchronous access.
- Page 718 GD32F20x User Manual 31:20 Reserved Must be kept at reset value. 19:17 ECCSZ[2:0] ECC size 000: 256 bytes 001: 512 bytes 010: 1024 bytes 011: 2048 bytes 100: 4096 bytes 101: 8192 bytes 16:13 ATR[3:0] ALE to RE delay 0x0: ALE to RE delay = 1 * HCLK ……...
- Page 719 GD32F20x User Manual NAND flash/PC card interrupt enable registers (EXMC_NPINTENx) (x=1, 2, 3) Address offset: 0x44 + 0x20 * x, (x = 1, 2, and 3) Reset value: 0x0000 0042 for bank1 and bank2, and 0x0000 0043 for bank3 This register has to be accessed by word(32-bit).
- Page 720 GD32F20x User Manual Reset value: 0xFFFF FFFF These operations applicable to common memory space for 16-bit PC Card, CF card and NAND Flash. This register has to be accessed by word(32-bit). COMHIZ[7:0] COMHLD[7:0] COMWAIT[7:0] COMSET[7:0] Bits Fields Description 31:24 COMHIZ[7:0] Common memory data bus HiZ time The bits are defined as time of bus keep high impedance state after writing the data.
- Page 721 GD32F20x User Manual NAND flash/PC card attribute space timing configuration registers (EXMC_NPATCFGx) (x=1, 2, 3) Address offset: 0x4C + 0x20 * x, (x = 1, 2, and 3) Reset value: 0xFFFF FFFF It is used for 8-bit accesses to the attribute memory space of the PC Card or to access the NAND Flash for the last address write access if another timing must be applied.
- Page 722 GD32F20x User Manual 0xFF: ATTSET = 256 * HCLK PC card I/O space timing configuration register (EXMC_PIOTCFG3) Address offset: 0xB0 Reset value: 0xFFFF FFFF This register has to be accessed by word(32-bit). IOHIZ[7:0] IOHLD[7:0] IOWAIT[7:0] IOSET[7:0] Bits Fields Description 31:24...
- Page 723 GD32F20x User Manual Reset value: 0x0000 0000 This register has to be accessed by word (32-bit). ECC[31:16] ECC[15:0] Bits Fields Description 31:0 ECC[31:0] ECC result ECCSZ[2:0] NAND Flash page size ECC bits 0b000 ECC[21:0] 0b001 ECC[23:0] 0b010 1024 ECC[25:0] 0b011...
- Page 724 GD32F20x User Manual Note: The corresponding bits in the EXMC_SDCTL1 register are reserved. BRSTRD Burst read When this bit is set, The SDRAM controller anticipates the next read commands during the CAS latency and stores data in the Read FIFO.
- Page 725 GD32F20x User Manual 10: 13 bits 11: reserved CAW[1:0] Column address bit width These bits specify the bit width of column address. 00: 8 bits 01: 9 bits 10: 10 bits 11: 11 bits. SDRAM timing configuration registers (EXMC_SDTCFGx) (x=0, 1)
- Page 726 GD32F20x User Manual These bits specify the delay between a Write and a Precharge command in SDRAM memory clock cycle unit. 0x0: 1 cycle 0x1: 2 cycles ..0xF: 16 cycles Note: The corresponding bits in the EXMC_SDTR1 register are reserved. If two SDRAM memories are used, the WRD must be programmed with the timings of the slower one.
- Page 727 GD32F20x User Manual 0xF: 16 cycles SDRAM command register (EXMC_SDCMD) Address offset: 0x150 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). Reserved MRC[12:7] MRC[6:0] NARF[3:0] CMD[2:0] Bits Fields Descriptions 31:22 Reserved Must be kept at reset value.
- Page 728 GD32F20x User Manual 100: Load Mode Register command 101: Self-refresh command 110: Power-down entry command 111: Reserved Note: At least one command device select bit (DS1 orDS0) must be set, when a command is issued. If both devices are used, the commands must be issued to the two devices by setting the DS1and DS0 bits at the same time.
- Page 729 GD32F20x User Manual Reserved Reserved NRDY STA1[1:0] STA0[1:0] REIF Bits Fields Descriptions 31:6 Reserved Must be kept at reset value. NRDY Not Ready status This bit specifies whether the SDRAM controller is ready for a new command 0: SDRAM Controller is ready for a new command...
- Page 730 GD32F20x User Manual SDSC[3:0] Select the delayed sample clock of read data 0x0: Select the clock after 0 delay cell 0x1: Select the clock after 1 delay cell …… 0xF: Select the clock after 15 delay cell Reserved Must be kept at reset value.
- Page 731 GD32F20x User Manual …… 0x1A: 26-bit address 0x1B: reserved …… 0x1F: reserved 23:18 Reserved Must be kept at reset value 17:16 CMDBIT[1:0] Bit number of SPI PSRAM command phase 00: 4 bit 01: 8 bit (default) 10: 16 bit 11: Reserved...
- Page 732 GD32F20x User Manual 15:0 RCMD[15:0] SPI read command for AHB read transfer. When CMDBIT is different, valid RCMD is different: CMDBIT=00,RCMD[3:0] are valid. CMDBIT=01,RCMD[7:0] are valid. CMDBIT=10,RCMD[15:0] are valid. SPI write command register (EXMC_SWCMD) Offset address: 0x330 Reset Value: 0x0000 0000 This register has to be accessed by word(32-bit).
- Page 733 GD32F20x User Manual SIDL[15:0] Bits Fields Descriptions 31:0 SIDL[31:0] ID low data saved for SPI read ID command SIDL[31:0] is valid when IDL=01 or 00. SIDL[15:0] is valid when IDL=10. SIDL[7:0] is valid when IDL=11. SPI ID high register (EXMC_SIDH)
- Page 734 GD32F20x User Manual Controller area network (CAN) 26.1. Overview CAN bus (Controller Area Network) is a bus standard designed to allow microcontrollers and devices to communicate with each other without a host computer. As CAN network interface, basic extended CAN supports the CAN protocols version 2.0A and B.
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Page 735: Figure 26-1. Can Module Block Diagram
GD32F20x User Manual 26.3. Function overview Figure 26-1. CAN module block diagram shows the CAN block diagram. Figure 26-1. CAN module block diagram Working mode 26.3.1. The CAN interface has three working modes: Sleep working mode. Initial working mode. - Page 736 GD32F20x User Manual Initial working mode When the configuration of CAN bus communication is needed to be changed, the CAN must enter initial working mode. When IWMOD bit in CAN_CTL register is set, the CAN enters the initial working mode. Then the IWS bit in CAN_STAT register is set.
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Page 737: Figure 26-2. Transmission Register
GD32F20x User Manual FIFOs, the RX pin is disconnected from the CAN network and the TX pin can still send messages to the CAN network. Setting LCMOD bit in CAN_BT register to enter loopback communication mode, while clearing it to leave. Loopback communication mode is useful for self-test. -
Page 738: Figure 26-3. State Of Transmission Mailbox
GD32F20x User Manual Transmit mailbox state A transmit mailbox can be used when it is free (empty state). If the mailbox is filled with data, set TEN bit in CAN_TMIx register to prepare for starting the transmission (pending state). If more than one mailbox is in the pending state, they need scheduling the transmission (scheduled state). -
Page 739: Figure 26-4. Reception Register
GD32F20x User Manual If the transmit mailbox’s status is pending or scheduled, the abort of transmission can be done immediately. In the transmit state, the abort of transmission does not take effect immediately until the transmission is finished. In case that the transmission is successful, the MTFNERR and MTF in CAN_TSTAT are set and state changes to be empty. - Page 740 GD32F20x User Manual RX FIFO Rx FIFO has three mailboxes. The reception frames are stored in the mailbox according to the arriving sequence. First arrived frame can be accessed by application firstly. The number of frames in the Rx FIFO and the status can be accessed by the register CAN_RFIFO0 and CAN_RFIFO1.
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Page 741: Figure 26-5. 32-Bit Filter
GD32F20x User Manual Figure 26-5. 32-bit filter Figure 26-6. 16-bit filter. 16-bit: SFID [10:0], FT, FF and EFID[17:15] bits. As shown in Figure 26-6. 16-bit filter Mask mode For the Identifier of a data frame to be filtered, the mask mode is used to specify which bits must be the same as the preset Identifier and which bits need not be judged. -
Page 742: Table 26-1. 32-Bit Filter Number
GD32F20x User Manual Filter number Filter consists of some filter bank. According to the mode and the scale of each of the filter banks, filter has different effect. For example, there are two filter banks. Bank 0 is configured as 32-bit mask mode. Bank 1 is Table 26-1. - Page 743 GD32F20x User Manual Filter Filter Filter Filter FIFO0 Active FIFO1 Active Bank Nunber Bank Nunber Mask F3DATA1[15:0]-16bit-ID F5DATA0-32bit-ID F3DATA1[31:16]-16bit- Mask F5DATA1-32bit-ID F7DATA0[15:0]-16bit-ID F6DATA0[15:0]-16bit-ID F7DATA0[31:16]-16bit-ID F6DATA0[31:16]-16bit-ID F7DATA1[15:0]-16bit-ID F6DATA1[15:0]-16bit-ID F7DATA1[31:16]-16bit-ID F6DATA1[31:16]-16bit-ID F8DATA0[15:0]-16bit-ID F10DATA0[15:0]-16bit-ID F10DATA0[31:16]-16bit- F8DATA0[31:16]-16bit-ID Mask F8DATA1[15:0]-16bit-ID F10DATA1[15:0]-16bit-ID F10DATA1[31:16]-16bit- F8DATA1[31:16]-16bit-ID Mask F9DATA0[15:0]-16bit-ID...
- Page 744 GD32F20x User Manual Communication parameters 26.3.7. Automatic retransmission forbid mode In time-triggered communication mode, the requirement for automatic retransmission must be disabled and can be met by setting ARD position 1 of the CAN_CTL register. In this mode, the data is sent only once, and if the transmission fails due to arbitration failure or bus error, the CAN bus controller does not automatically resend the data as usual.
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Page 745: Figure 26-11. The Bit Time
GD32F20x User Manual Figure 26-11. The bit time Normal Bit Time Sync Propagation delay Phase buffer Phase buffer protocol segment segment segment 1 segment2 SYNG_SEG BIT SEGMENT 1(BS1) BIT SEGMENT 2(BS2) The resynchronization Jump Width (SJW): it can be lengthened or shortened to compensate for the Synchronization error of the CAN network node. - Page 746 GD32F20x User Manual Bus-Off recovery The CAN controller is in Bus-Off state when TECNT is over than 255. In This state, BOERR bit is set in CAN_ERR register, and no longer able to transmit and receive messages. According to the ABOR configuration in register CAN_CTL, there are two ways to recover from Bus-Off (to an error active state).
- Page 747 GD32F20x User Manual Receive FIFO1 interrupt The receive FIFO1 interrupt can be generated by the following conditions: RX FIFO1 not empty: RFL1 bits in the CAN_RFIFO1 register are not ‘00’ and – RFNEIE1 in CAN_INTEN register is set. RX FIFO1 full: RFF1 bit in the CAN_RFIFO1 register is set and RFFIE1 in –...
- Page 748 GD32F20x User Manual 26.4. Register definition CAN0 base address: 0x4000 6400 CAN1 base address: 0x4000 6800 Control register (CAN_CTL) 26.4.1. Address offset: 0x00 Reset value: 0x0001 0002 This register has to be accessed by word(32-bit) Reserved SLPWMO SWRST Reserved ABOR...
- Page 749 GD32F20x User Manual 0: The sleeping working mode is left manually by software 1: The sleeping working mode is left automatically by hardware Automatic retransmission disable 0: Enable automatic retransmission 1: Disable automatic retransmission RFOD Rx FIFO overwrite disable 0: Enable Rx FIFO overwrite when Rx FIFO is full and overwrite the FIFO with the...
- Page 750 GD32F20x User Manual Receiving state 0: CAN is not working in the receiving state 1: CAN is working in the receiving state Transmitting state 0: CAN is not working in the transmitting state 1: CAN is working in the transmitting state Reserved Must be kept at reset value.
- Page 751 GD32F20x User Manual This bit is set by hardware when the CAN enters initial working mode after setting IWMOD bit in CAN_CTL register. If the CAN leaves normal working mode to initial working mode, it must wait the current frame transmission or reception to be completed.
- Page 752 GD32F20x User Manual TME0 Transmit mailbox 0 empty 0: Transmit mailbox 0 not empty 1: Transmit mailbox 0 empty 25:24 NUM[1:0] These bits are the number of the Tx FIFO mailbox in which the frame will be transmitted if at least one mailbox is empty.
- Page 753 GD32F20x User Manual MAL1 Mailbox 1 arbitration lost This bit is set when the arbitration lost occurs. This bit is reset by writting 1 to this bit or MTF1 bit in CAN_TSTAT register. This bit is reset by hardware when next transmit starts.
- Page 754 GD32F20x User Manual Receive message FIFO0 register (CAN_RFIFO0) 26.4.4. Address offset: 0x0C Reset value: 0x0000 0000 This register has to be accessed by word(32-bit) Reserved Reserved RFD0 RFO0 RFF0 Reserved RFL0[1:0] rc_w1 rc_w1 Bits Fields Descriptions 31:6 Reserved Must be kept at reset value.
- Page 755 GD32F20x User Manual Reserved RFD1 RFO1 RFF1 Reserved RFL1[1:0] rc_w0 rc_w1 Bits Fields Descriptions Must be kept at reset value. 31:6 Reserved Rx FIFO1 dequeue This bit is set by software to start dequeuing a frame from Rx FIFO1. RFD1 This bit is reset by hardware when the dequeuing is done.
- Page 756 GD32F20x User Manual 0: Wakeup interrupt disabled 1: Wakeup interrupt enabled ERRIE Error interrupt enable 0: Error interrupt disabled 1: Error interrupt enabled 14:12 Reserved Must be kept at reset value. ERRNIE Error number interrupt enable 0: Error number interrupt disabled...
- Page 757 GD32F20x User Manual TMEIE Transmit mailbox empty interrupt enable 0: Transmit mailbox empty interrupt disabled 1: Transmit mailbox empty interrupt enabled Error register (CAN_ERR) 26.4.7. Address offset: 0x18 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit)
- Page 758 GD32F20x User Manual by hardware. Bit timing register (CAN_BT) 26.4.8. Address offset: 0x1C Reset value: 0x0123 0000 This register has to be accessed by word(32-bit) SCMOD LCMOD Reserved SJW[1:0] Reserved BS2[2:0] BS1[3:0] Reserved BAUDPSC[9:0] Bits Fields Descriptions SCMOD Silent communication mode...
- Page 759 GD32F20x User Manual SFID[10:0]/EFID[28:18] EFID[17:13] EFID[12:0] Bits Fields Descriptions 31:21 SFID[10:0]/EFID[28:1 The frame identifier SFID[10:0]: Standard format frame identifier EFID[28:18]: Extended format frame identifier 20:16 EFID[17:13] The frame identifier EFID[17:13]: Extended format frame identifier 15:3 EFID[12:0] The frame identifier EFID[12:0]: Extended format frame identifier...
- Page 760 GD32F20x User Manual 31:16 TS[15:0] Time stamp The time stamp of frame in transmit mailbox. 15:9 Reserved Must be kept at reset value. TSEN Time stamp enable 0: Time stamp disabled 1: Time stamp enabled. The TS[15:0] will be transmitted in the DB6 and DB7 in This bit is available when the TTC bit in CAN_CTL is set.
- Page 761 GD32F20x User Manual DB5[7:0] DB4[7:0] Bits Fields Descriptions 31:24 DB7[7:0] Data byte 7 23:16 DB6[7:0] Data byte 6 15:8 DB5[7:0] Data byte 5 DB4[7:0] Data byte 4 Receive FIFO mailbox identifier register (CAN_RFIFOMIx) (x=0,1) 26.4.13. Address offset: 0x1B0, 0x1C0 Reset value: 0xXXXX XXXX...
- Page 762 GD32F20x User Manual Reserved Must be kept at reset value. Receive FIFO mailbox property register (CAN_RFIFOMPx) (x=0,1) 26.4.14. Address offset: 0x1B4, 0x1C4 Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) TS[15:0] FI[7:0] Reserved DLENC[3:0] Bits Fields...
- Page 763 GD32F20x User Manual DB0[7:0] Data byte 0 Receive FIFO mailbox data1 register (CAN_RFIFOMDATA1x) (x=0,1) 26.4.16. Address offset: 0x1BC, 0x1CC Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) DB7[7:0] DB6[7:0] DB5[7:0] DB4[7:0] Bits Fields Descriptions 31:24 DB7[7:0]...
- Page 764 GD32F20x User Manual Reserved Must be kept at reset value. Filter lock disable 0: Filter lock enabled 1: Filter lock disabled Filter mode configuration register (CAN_FMCFG) (Just for CAN0) 26.4.18. Address offset: 0x204 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). This register can be modified only when FLD bit in CAN_FCTL register is set.
- Page 765 GD32F20x User Manual 0: Filter x with 16-bit scale 1: Filter x with 32-bit scale Filter associated FIFO register (CAN_FAFIFO) (Just for CAN0) 26.4.20. Address offset: 0x214 Reset value: 0x0000 0000 This register has to be accessed by word(32-bit). This register can be modified only when FLD bit in CAN_FCTL register is set.
- Page 766 GD32F20x User Manual Filter x data y register (CAN_FxDATAy) (x=0..27, y=0,1) (Just for CAN0) 26.4.22. Address offset: 0x240+8*x+4*y, (x=0..27, y=0,1) Reset value: 0xXXXX XXXX This register has to be accessed by word(32-bit) FD31 FD30 FD29 FD28 FD27 FD26 FD25 FD24...
- Page 767 The support interface protocol for Ethernet is media independent interface (MII) and reduced media independent interface (RMII). This module is mainly compliant with the following two standards: IEEE 802.3-2002 and IEEE 1588-2002. Ethernet module is compatible with GD32F20x series. 27.2. Characteristics MAC feature ...
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Page 768: Figure 27-1. Enet Module Block Diagram
GD32F20x User Manual describes in IEEE 1588-2008, and 64 bit time stamps are given in each frame’s status. Two independent FIFO of 2K Byte for transmitting and receiving. Support special condition frame discards handling, e.g. late collision, excessive collisions, ... -
Page 769: Figure 27-2. Mac/Tagged Mac Frame Format
GD32F20x User Manual TxMTL, used to control, management and store the transmit data. TxFIFO is implemented in this module and used to cache transmitting data from memory for MAC transmission. The MAC transmission relative control registers, used to control frame transmit. -
Page 770: Table 27-1. Ethernet Pin Configuration
GD32F20x User Manual The Ethernet frame’s 32-bit CRC calculation value generating polynomial is fixed 0x04C11DB7 and this polynomial is used in all 32-bit CRC calculation places in Ethernet module, as follows: G(x) = x + x + 1 Ethernet signal description 27.2.3. - Page 771 GD32F20x User Manual RMII RMII MAC signals Pin configuration default remap default remap ETH_MII_TX_EN AF output push-pull PB11 TX_EN TX_EN ETH_RMII_TX_EN highspeed (50 MHz) ETH_MII_TXD0 AF output push-pull PB12 TXD0 TXD0 ETH_RMII_TXD0 highspeed (50 MHz) ETH_MII_TXD1 AF output push-pull PB13...
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Page 772: Figure 27-3. Station Management Interface Signals
GD32F20x User Manual Figure 27-3. Station management interface signals MDIO External PHY SMI write operation Applications need to write transmission data to the ENET_MAC_PHY_DATA register and operate the ENET_MAC_PHY_CTL register as follows: Set the PHY device address and PHY register address, and set PW to 1, so that can select write mode. -
Page 773: Figure 27-4. Media Independent Interface Signals
GD32F20x User Manual Table 27-2. Clock range AHB clock MDC clock Selection 35~60MHz AHB clock/26 20~35MHz AHB clock/16 100~120 MHz AHB clock/62 60~100MHz AHB clock/42 MII/RMII selection The application can select the MII or RMII mode through the configuration bit 23 of the AFIO_PCF0 register ENET_PHY_SEL while the Ethernet controller is under reset state or before enabling the clocks. -
Page 774: Table 27-3. Rx Interface Signal Encoding
GD32F20x User Manual It is active when either transmit or receive medium is in non idle state. The PHY must ensure that the MII_CRS signal remains asserted throughout the duration of a collision condition. This signal is not required to transition synchronously with respect to the TX and RX clock. -
Page 775: Figure 27-5. Reduced Media-Independent Interface Signals
GD32F20x User Manual Ethernet communication. According to the IEEE 802.3 standard, an MII contains 16 pins for data and control. The RMII specification is dedicated to reduce the pin count to 7. The RMII block has the following characteristics: ... - Page 776 GD32F20x User Manual Frame detecting/decoding and frame boundary delimitation. Addressing (handling source address and destination address). Error conditions detect. Medium access management in Half-duplex mode Medium allocation (prevent conflicts). Conflict resolution (dealing with conflicts). The MAC module can work in two modes ...
- Page 777 GD32F20x User Manual ENET_DMA_CTL register (when this bit is set, it will clear FIFO data and reset the FIFO pointer, after clear operation is completed, it will be reset), there will be a transmit data underflow fault occurs because of insufficient data in FIFO. At the same time MAC will identify such data underflow state and write relevant status flag.
- Page 778 GD32F20x User Manual TxFIFO is popping data to MAC. This results in an underflow event in the MAC transmitter, and the makes frame transmission abort. At the same time, MAC returns state information of frame and transmit status words transferred to the application. The status of such a frame is marked with both underflow and frame flush events (TDES0 bits 1 and 13).
- Page 779 GD32F20x User Manual frame. MAC automatically sends pause time when the RxFIFO is in some condition. When MAC is receiving frame, RxFIFO will be fill in many receive data. At same time RxFIFO pops out data to RxDMA for forwarding to memory. If the popping frequency is lower than MAC pushing frequency, the number of bytes in RxFIFO is getting great.
- Page 780 GD32F20x User Manual deep enough to store the whole transmit frame. If the depth of the TxFIFO is less than the frame length, the MAC only does calculation and insertion for IPv4 header checksum field. See IETF specifications RFC 791, RFC 793, RFC 768, RFC 792, RFC 2460 and RFC 4443 for IPv4, TCP, UDP, ICMP, IPv6 and ICMPv6 packet header specifications, respectively.
- Page 781 GD32F20x User Manual After calculated by checksum offload module, the result can be found in IPPE bit (bit 12 in TDES0). The following shows the conditions under which the IPPE bit can be set: In Store-and-Forward mode, frame has been forwarded to MAC transmitter but no EOF...
- Page 782 GD32F20x User Manual Hash list filtering In this filter mode, MAC uses a HASH mechanism. MAC uses a 64-bit hash list to filter the received unicast frame. This filter mode obeys the followings two filtering steps: 1) The MAC calculates the CRC value of the received frame’s destination address.
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Page 783: Table 27-4. Destination Address Filtering Table
GD32F20x User Manual or source address filtering. By setting the DAIFLT and SAIFLT bits in ENET_MAC_FRMF register, this address filter reverse function can be enabled. DAIFLT bit is used for unicast and multicast frames’ DA filtering result, SAIFLT bit is used for unicast and multicast frames SA filtering result. -
Page 784: Table 27-5. Source Address Filtering Table
GD32F20x User Manual Frame HPFLT DAIFLT HMF MFD BFRMD DA filter operation Type Fail on hash or perfect/group filter match and drop PAUSE control frames if PCFRM = 0x Table 27-5. Source address filtering table Frame SAIFLT SAFLT SA filter operation... - Page 785 GD32F20x User Manual RxFIFO up to the count specified in the length/type field, then starts dropping bytes (including the FCS field). If the value of Length/Type field is greater than or equal to 0x600, regardless of whether the option of automatic CRC and pad stripping function is enabled, the MAC pushes all received frame data to Rx FIFO.
- Page 786 GD32F20x User Manual Receive checksum offload Receive checksum offload is enabled when IPFCO bit in ENET_MAC_CFG register is set. Receive checksum offload can calculate the IPv4 header checksum and check whether it matches the contents of the IPv4 header checksum field. The MAC identifies IPv4 or IPv6 frames by checking for the value of 0x0800 or 0x86DD respectively in the received Ethernet frame type field.
- Page 787 GD32F20x User Manual receive descriptor and DMA status flag. Application can check these flags for upper protocol implementation. Note: The value of frame length is 0 means that for some reason (such as FIFO overflow or dynamically modify the filter value in the receiving process, resulting did not pass the filter, etc), frame data is not written to FIFO completely.
- Page 788 GD32F20x User Manual Wake up management: WUM 27.3.4. Ethernet (ENET) module supports two wakeup methods from Deep-sleep mode. The one is remote wakeup frame and the other is Magic Packet wakeup frame. For reduce power consuming, the host system and Ethernet can be powered down and thus the circuit driven by HCLK or transmit clock is stop working.
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Page 789: Figure 27-6. Wakeup Frame Filter Register
GD32F20x User Manual Figure 27-6. Wakeup frame filter register Wakeup Frame Filter Filter 0 Byte Mask Register 0 Wakeup Frame Filter Filter 1 Byte Mask Register 1 Wakeup Frame Filter Filter 2 Byte Mask Register 2 Wakeup Frame Filter Filter 3 Byte Mask... - Page 790 GD32F20x User Manual the destination and source address field, then there are 16 duplicate MAC addresses without any interruption and pause. If there is any discontinuity between repeating it 16 times, MAC needs to re-detect 0xFFFF FFFF FFFF in the receive frame. WUM module continuously monitors each frame received.
- Page 791 GD32F20x User Manual modify ENET_WKUP_IRQ interrupt handling procedures to clear the pending bit of the EXTI line 19. Set the MPEN or WFEN (or both) bit in ENET_MAC_WUM register to enable Magic Packet or Remote Wakeup frame(or both) detection. Setting PWD bit in ENET_MAC_WUM register to enter power-down state.
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Page 792: Figure 27-7. System Time Update Using The Fine Correction Method
GD32F20x User Manual If the coarse correction method is selected, application can configure PTP timestamp update register (ENET_PTP_TSUH and ENET_PTP_TSUL) for system time initialization or correction. If TMSSTI bit is set, PTP timestamp update register is used for initialization and if TMSSTU bit is set, PTP timestamp update register is used for adjust system time by adding or subtracting. - Page 793 GD32F20x User Manual represents the subsecond value of system time, the precision is 10 ns/2 =0.46ns. So in order to make the system time accuracy to 20ns, sub second increment register value should be set to 20/0.46 = 0d43. Note: The algorithm described below based on constant delay transferred between master and slave devices (Master-to-Slave-Delay).
- Page 794 GD32F20x User Manual 7) Configure the timestamp update high and low register with the value of system time application wants to initialize 8) Send initialization command by setting bit 2 in the ENET_PTP_TSCTL register 9) The timestamp counter starts counting as soon as the initialization process complete...
- Page 795 GD32F20x User Manual (HCLK) are synchronous. PTP pulse-per-second (PPS) output signal Application configures ETH_PPS_OUT pin to AF output push-pull to enable the PPS output function. This function can output a signal with the pulse width of 125ms which can be used to check the synchronization between all nodes in the network.
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Page 796: Figure 27-8. Descriptor Ring And Chain Structure
GD32F20x User Manual ring structure. At this time, the next descriptor pointer points back to the first descriptor address of the descriptor table. In chain structure, can also set TDES3 or RDES3 value to point back to the first descriptor address of the descriptor table. The DMA skips to the next frame buffer when the end of frame is detected. - Page 797 GD32F20x User Manual or more descriptors to indicate the frame information which means a frame data can be located in many buffers. When the DMA controller reads a descriptor which the FSG bit in TDES0 is set, it knows the current buffer is pointing to a new frame and the first byte of the frame is included.
- Page 798 GD32F20x User Manual DMA controller initialization for transmission and reception Before using the DMA controller, the initialization must be done as follow steps: 1) Set the bus access parameters by writing the ENET_DMA_BCTL register 2) Mask unnecessary interrupt source by configuring the ENET_DMA_INTEN register...
- Page 799 GD32F20x User Manual 4) When the DAV bit in TDES0[31] of the acquired descriptor is set, the DMA decodes the transmit frame configured and the data buffer address from the acquired descriptor 5) DMA retrieve data from the memory and push it into the TxFIFO of MAC 6) The TxDMA controller continues polling the descriptor table until the EOF data (LSG bit is set) is transferred.
- Page 800 GD32F20x User Manual previous frame is occurred, the TxDMA controller enters in suspend state and the next operation goes to Step 7. 7) In suspend state, when the status information and timestamp value (if the function is enable) of the transmitting frame is available, the TxDMA controller writes them back to descriptor and then close it by setting DAV=0 of descriptor.
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Page 801: Figure 27-9. Transmit Descriptor
GD32F20x User Manual The MAC FIFO is empty during sending a frame on interface which means an error of underflow occurs. In this case, the AI bit and TU bit in ENET_DMA_STAT register are set. Also the transmit error status will write back to transmit descriptor. - Page 802 GD32F20x User Manual 1: The descriptor is available for DMA not for CPU INTC Interrupt on completion bit This is valid only when the last segment (TDES0[29]) is set. 0: TS bit in ENET_DMA_STAT is not set when frame transmission complete.
- Page 803 GD32F20x User Manual 1: The descriptor table reached its final descriptor. The DMA descriptor pointer returns to the start address of the table. TCHM The second address chained mode bit This bit is used only in chain mode. When this bit, TCHM (TDES0[20]), is set, TB2S (TDES1[28:16]) is don’t care.
- Page 804 GD32F20x User Manual 1:The MAC transmitter has experienced a jabber timeout FRMF Frame flushed bit This bit is set to flush the Tx frame by software IPPE IP payload error bit The transmitter checks the payload length received in the IPv4 or IPv6...
- Page 805 GD32F20x User Manual 0: No excessive deferral occurred 1: The transmission has ended because of excessive deferral time is over 3036 bytes Underflow error bit This bit indicates that the TxDMA comes across an empty TxFIFO while transmitting the frame before EOF which is caused by pushing data to TxFIFO late from memory.
- Page 806 GD32F20x User Manual TB1AP/TTSL[15:0] Bits Fields Descriptions 31:0 TB1AP/TTSL[31:0] Transmit buffer 1 address pointer/Transmit frame timestamp low 32-bit value bits Before transmitting frame, application must configure these bits for transmit buffer 1 address (TB1AP). When the transmitting frame is complete, these bits can be changed to the timestamp low 32-bit value (TTSL) for transmitting frame.
- Page 807 GD32F20x User Manual reset which means this receive descriptor cannot be used by RxDMA, the RxDMA controller will enter suspend state and operation goes to Step 9 3) From the valid receive descriptor (DAV=1), the RxDMA controller marks the receiving...
- Page 808 GD32F20x User Manual Writing any value to receive poll enable register ENET_DMA_RPEN Process of receiving frame When a frame is presented on the interface, the MAC starts to receive it. At the same time, the address filter block is running for this received frame. If the received frame fails the address filtering it will be discarded from RxFIFO in MAC and not be forwarded to buffer by RxDMA controller.
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Page 809: Figure 27-10. Receive Descriptor
GD32F20x User Manual Receive DMA descriptor with IEEE 1588 timestamp format If the IEEE 1588 function enabled, the MAC writes the timestamp value to RDES2 and RDES3 after a frame with timestamp reception complete and before the RxDMA controller clears the DAV bit. - Page 810 GD32F20x User Manual DERR=0 (RDES0[14]). If LDES=0 and ERRS=0, these bits indicate the accumulated number of bytes that have been transferred for the current frame. ERRS Error summary bit This field is valid only when the LDES (RDES0[8]) is set.
- Page 811 GD32F20x User Manual 0: The current descriptor does not store the SOF of the received frame 1: The current descriptor buffer saves the SOF of the received frame LDES Last descriptor bit This bit indicates that current descriptor contains the EOF of the received frame...
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Page 812: Table 27-6. Error Status Decoding In Rdes0, Only Used For Normal Descriptor
GD32F20x User Manual This bit is valid only when the LDES (RDES0[8]) is set and indicates FCS field in received frame is mismatch with the calculation result of the hardware 0: No CRC error occurred 1: A CRC error occurred... - Page 813 GD32F20x User Manual Bits Fields Descriptions DINTC Disable interrupt on completion bit 0: RS bit in ENET_DMA_STAT register will be set after receiving the completed, then if enabled the corresponding interrupt, the interrupt will trigger. 1: RS bit in ENET_DMA_STAT register will not be set after receiving the completed, so the corresponding interrupt will not be triggered.
- Page 814 GD32F20x User Manual These bits are designed for two different functions: buffer address pointer (RB1AP) or timestamp low 32-bit value (RTSL). RB1AP: Before fetching this descriptor by RxDMA controller, these bits are configured to the buffer 1 address by application. This buffer 1 address pointer is used for RxDMA controller to store the received frame if RB1S is not 0.
- Page 815 GD32F20x User Manual Program the RCU module to enable the HCLK and Ethernet Tx/Rx clock. Setup the communication interface. Configure AFIO_PCF0 to define which interface mode is selected (MII or RMII). Configure GPIO module to make selected PADs to alternate function.
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Page 816: Figure 27-11. Mac Interrupt Scheme
GD32F20x User Manual ENET_DMA_RDTADDR register). 2) If DAV bit in RDES0 is reset, then the descriptor is used and receive buffer space has stored the receive frame. 3) Handling this receive frame data. 4) Set DAV bit of this descriptor to release this descriptor for new frame receiving. -
Page 817: Figure 27-12. Ethernet Interrupt Scheme
GD32F20x User Manual DMA controller interrupts The DMA controller has two types of event: Normal and Abnormal. No matter what type the event is, it has an enable bit (just like mask bit) to control the generating interrupt or not. Each event can be cleared by writing 1 to it. When all of the events are cleared or all of the event enable bits are cleared, the corresponding summary interrupt bit is cleared. - Page 818 GD32F20x User Manual 27.4. Register definition ENET base address: 0x4002 8000 MAC configuration register (ENET_MAC_CFG) 27.4.1. Address offset: 0x0000 Reset value: 0x0000 8000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit). This register configures the operation mode of the MAC. It also configures the MAC receiver and MAC transmitter operating mode.
- Page 819 GD32F20x User Manual 0x6: 48 bit times(For Half-duplex, must be reserved) 0x7: 40 bit times(For Half-duplex, must be reserved) Carrier sense disable bit 0: The MAC transmitter generates carrier sense error and aborts the transmission 1: The MAC transmitter ignores the MII CRS signal during frame transmission in Half-duplex mode.
- Page 820 GD32F20x User Manual 1 slot time is equal to 512 bit times. This delay time (dt) is a random integer number calculated by following formula : 0≤dt <2 0x0: k = min (n, 10) 0x1: k = min (n, 8)
- Page 821 GD32F20x User Manual This bit controls the receive filter function. 0: Only the frame passed the filter can be forwarded to application. 1: All received frame are forwarded to application. But filter result will also be updated to receive descriptor status.
- Page 822 GD32F20x User Manual 1: Inverse DA filtering result Hash multicast filter bit 0: The filter uses perfect mode for filtering multicast frame. 1: The filter uses hash mode for filtering multicast frame Hash unicast filter bit 0: The filter uses perfect mode for filtering unicast frame...
- Page 823 GD32F20x User Manual Bits Fields Descriptions 31:0 HLL[31:0] Hash list low bits These bits take the low 32-bit value of hash list MAC PHY control register (ENET_MAC_PHY_CTL) 27.4.5. Address offset: 0x0010 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit).
- Page 824 GD32F20x User Manual PHY busy bit This bit indicates the running state of operation on PHY. Application sets this bit to 1 and should wait it cleared by hardware. Application must make sure this bit is zero before writing data to ENET_MAC_PHY_CTL register and reading/writing data...
- Page 825 GD32F20x User Manual These bits configured the pause time filed value in transmit pause control frame. 15:8 Reserved Must be kept at reset value. DZQP Disable Zero-quanta pause bit 0: Enable automatic zero-quanta generation function for pause control frame. 1: Disable the automatic zero-quanta generation function for pause control frame Reserved Must be kept at reset value.
- Page 826 GD32F20x User Manual For Full-duplex mode, application must make sure this bit is 0 before writing ENET_MAC_FCTL register. After set by application, MAC sends a pause frame to interface and this bit will keep set until the pause frame has completed transmitting.
- Page 827 GD32F20x User Manual 0x3: 1024 bytes 0x4: 1280 bytes 0x5: 1536 bytes 0x6,0x7: 1792 bytes MAC VLAN tag register (ENET_MAC_VLT) 27.4.9. Address offset: 0x001C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit). This register configures the IEEE 802.1Q VLAN Tag to identify the VLAN frames. The MAC...
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Page 828: Figure 27-13. Wakeup Frame Filter Register
GD32F20x User Manual MAC remote wakeup frame filter register (ENET_MAC_RWFF) 27.4.10. Address offset: 0x0028 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit). The MAC remote wakeup frame filter register is actually a pointer to eight (with same address offset) such wakeup frame filter registers. - Page 829 GD32F20x User Manual 0: No effect 1: Reset the ENET_MAC_RWFF register inner pointer 30:10 Reserved Must be kept at reset value. Global unicast bit 0: Not all of received unicast frame is considered to be a wakeup frame. 1: Any received unicast frame passed address filtering is considered to be a wakeup frame.
- Page 830 GD32F20x User Manual rc_r Bits Fields Descriptions 31:10 Reserved Must be kept at reset value. TMST Time stamp trigger status bit This bit is cleared when ENET_PTP_TSF register is read. 0: The system time value is less than the value specified in the target time registers.
- Page 831 GD32F20x User Manual 31:10 Reserved Must be kept at reset value. TMSTIM Timestamp trigger interrupt mask bit 0:Unmask the timestamp interrupt generation 1:Mask the timestamp interrupt generation Reserved Must be kept at reset value. WUMIM WUM interrupt mask bit 0: Unmask the interrupt generation due to the WUM bit in ENET_MAC_INTF register.
- Page 832 GD32F20x User Manual ADDR0L[15:0] Bits Fields Descriptions 31:0 ADDR0L[31:0] MAC addresss0 low 32-bit These bits contain the low 32-bit (bit 31 to 0) of the 6-byte MAC address0. These bits are used for address filtering in frame reception and address inserting in pause frame transmitting during transmit flow control.
- Page 833 GD32F20x User Manual MB[0]: ENET_MAC_ADDR1L [7:0] 23:16 Reserved Must be kept at reset value 15:0 ADDR1H[15:0] MAC address1 high [47:32] bits This field contains the high 16-bit (bit 47 to 32) of the 6-byte MAC address1 MAC address 1 low register (ENET_MAC_ADDR1L) 27.4.17.
- Page 834 GD32F20x User Manual 0:The MAC address2[47:0] is used to comparing with the DA fields of the received frame 1:The MAC address2[47:0] is used to comparing with the SA fields of the received frame 29:24 MB[5:0] Mask byte bits When they are set high, the MAC does not compare the corresponding byte of received DA/SA with the contents of the MAC address2 registers.
- Page 835 GD32F20x User Manual This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit). MB[5:0] Reserved ADDR3H[15:0] Bits Fields Descriptions Address filter enable bit 0:The address filter ignores the MAC address3 for filtering 1:The address filter use the MAC address3 for perfect filtering...
- Page 836 GD32F20x User Manual ADDR3L[15:0] Bits Fields Descriptions 31:0 ADDR3L[31:0] MAC address3 low 32-bit This field contains the low 32-bit of the 6-byte MAC address3 MSC control register (ENET_MSC_CTL) 27.4.22. Address offset: 0x0100 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit).
- Page 837 GD32F20x User Manual Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit). Reserved RGUF Reserved rc_r Reserved RFAE RFCE Reserved rc_r rc_r Bits Fields Descriptions 31:18 Reserved Must be kept at reset value. RGUF Received good unicast frames bit...
- Page 838 GD32F20x User Manual 0: Good frame transmitted counter is less than half of the maximum value 1: Good frame transmitted counter reaches half of the maximum value 20:16 Reserved Must be kept at reset value. TGFMSC Transmitted good frames more single collision bit...
- Page 839 GD32F20x User Manual RFCEIM Received frame CRC error interrupt mask bit 0: Unmask the interrupt when RFCE bit is set 1: Mask the interrupt when the RFCE bit is set Reserved Must be kept at reset value. MSC transmit interrupt mask register (ENET_MSC_TINTMSK) 27.4.26.
- Page 840 GD32F20x User Manual This register counts the number of successfully transmitted frames after a single collision in Half-duplex mode. SCC[31:16] SCC[15:0] Bits Fields Descriptions 31:0 SCC[31:0] Transmitted good frames single collision counter bits These bits count the number of a transmitted good frames after only a single...
- Page 841 GD32F20x User Manual TGF[31:16] TGF[15:0] Bits Fields Descriptions 31:0 TGF[31:0] Transmitted good frames counter bits These bits count the number of transmitted good frames received frames with error counter register 27.4.30. (ENET_MSC_RFCECNT) Address offset: 0x0194 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit).
- Page 842 GD32F20x User Manual RFAER[15:0] Bits Fields Descriptions 31:0 RFAER[31:0] Received frames alignment error counter bits These bits count the number of receive frames with alignment error received good unicast frames counter register 27.4.32. (ENET_MSC_RGUFCNT) Address offset: 0x01C4 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit).
- Page 843 GD32F20x User Manual 31:6 Reserved Must be kept at reset value. TMSARU Time stamp addend register update bit This bit is cleared when the update is completed. This register bit must be read as zero before application set it. 0: The timestamp addend register’s contents are not updated to the PTP block for fine correction 1: The timestamp addend register’s contents are updated to the PTP block for fine...
- Page 844 GD32F20x User Manual is added to the system time when the accumulator reaches overflow Reserved Reserved STMSSI[7:0] Bits Fields Descriptions 31:8 Reserved Must be kept at reset value. STMSSI[7:0] System time subsecond increment bits In every update operation, these bits are added to the subsecond value of system time.
- Page 845 GD32F20x User Manual Bits Fields Descriptions System time sign bit 0: Time value is positive 1: Time value is negative 30:0 STMSS[30:0] System time subseconds bits These bits show the current subsecond of the system time with 0.46 ns accuracy if required accuracy is 20 ns.
- Page 846 GD32F20x User Manual TMSUSS[15:0] Bits Fields Descriptions TMSUPNS Timestamp update positive or negative sign bit When TMSSTI is set, this bit must be 0. 0: Timestamp update value is added to system time 1: Timestamp update value is subtracted from system time...
- Page 847 GD32F20x User Manual ETSH[15:0] Bits Fields Descriptions 31:0 ETSH[31:0] Expected time high bits These bits store the expected target second time. PTP expected time low register (ENET_PTP_ETL) 27.4.41. Address offset: 0x0720 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit).
- Page 848 GD32F20x User Manual 0: Disable address-aligned 1: Enabled address-aligned. If the FB=1, all AHB interface address is aligned to the start address LS bits (bit 1 to 0). If the FB=0, the AHB interface first access address (accessing the data buffer’s start address) is not aligned, but subsequent burst...
- Page 849 GD32F20x User Manual 0x02: max beat number is 2 0x04: max beat number is 4 0x08: max beat number is 8 0x10: max beat number is 16 0x20: max beat number is 32 Other: Reserved Reserved Must be kept at reset value.
- Page 850 GD32F20x User Manual 31:0 TPE[31:0] Transmit poll enable bits Writing to this register with any value makes DMA read the current descriptor address which is indicated in ENET_DMA_CTDADDR register. If the fetched current descriptor is available (DAV=1), DMA exits suspend state and resumes working. If the fetched current descriptor is unavailable (DAV=0), the DMA returns to suspend state again and the TBU bit in ENET_DMA_STAT register will be set.
- Page 851 GD32F20x User Manual SRT[15:0] Bits Fields Descriptions 31:0 SRT[31:0] Start address of receive table bits These bits indicate the start address of the receive descriptor table. SRT[1:0] are internally taken as zero so SRT[1:0] are read only. DMA transmit descriptor table address register (ENET_DMA_TDTADDR) 27.4.46.
- Page 852 GD32F20x User Manual Reserved rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 rc_w1 Bits Fields Descriptions 31:30 Reserved Must be kept at reset value. Timestamp trigger status bit This bit indicates a timestamp event occurred. It is cleared by application through clearing TMST bit.
- Page 853 GD32F20x User Manual 0x4, 0x5: Reserved 0x6: Suspended; Transmit descriptor unavailable or transmit buffer underflow 0x7: Running; Closing transmit descriptor 19:17 RP[2:0] Receive process state bit These bits decode the RxDMA state. 0x0: Stopped: Reset or Stop Receive Command issued...
- Page 854 GD32F20x User Manual Fatal bus error status bit This bit indicates a response error on AHB interface is occurred and the error type can be decoded by EB[2:0] bits. 0: Bus error has not occurred 1: A bus error occurred and the corresponding DMA stops all operations...
- Page 855 GD32F20x User Manual 1: The DAV bit in fetched next transmit descriptor is reset and TxDMA enters suspend state. Transmit process stopped status bit 0: The transmission is not in stop state 1: The transmission is in stop state Transmit status bit This bit can only be set when both LSG and INTC are set in TDES0.
- Page 856 GD32F20x User Manual TSFD Transmit Store-and-Forward bit TxFIFO operates Cut-Through mode. TTHC bits ENET_DMA_CTL register defines the start popping time from TxFIFO 1: The TxFIFO operates in Store-and-Forward mode. Transmission on interface starts after the full frame has been pushed into the TxFIFO. The TTHC bits are ignored in this mode.
- Page 857 GD32F20x User Manual popping RxFIFO data to memory, RxFIFO drops this error frame. But if frame error is detected after popping RxFIFO data to memory, RxFIFO will not drop this frame data. When RxFIFO is in Store-and-Forward mode, once frame error is detected during reception the RxFIFO drops this frame.
- Page 858 GD32F20x User Manual Reserved Must be kept at reset value. DMA interrupt enable register (ENET_DMA_INTEN) 27.4.49. Address offset: 0x101C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit). This register configures the interrupts which are reflected in ENET_DMA_STAT register.
- Page 859 GD32F20x User Manual 1: The early receive interrupt is enabled FBEIE Fatal bus error interrupt enable bit 0: The fatal bus error enable interrupt is disabled 1: The fatal bus error enable interrupt is enabled 12:11 Reserved Must be kept at reset value.
- Page 860 GD32F20x User Manual 1: The transmit interrupt is enabled missed frame buffer overflow counter register 27.4.50. (ENET_DMA_MFBOCNT) Address offset: 0x1020 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit). There are two counters designed in DMA controller for tracking the number of missed frames during receiving.
- Page 861 GD32F20x User Manual TDAP[31:16] TDAP[15:0] Bits Fields Descriptions 31:0 TDAP[31:0] Transmit descriptor address pointer bits These bits are automatically updated by TxDMA controller during operation. current receive descriptor address register 27.4.52. (ENET_DMA_CRDADDR) Address offset: 0x104C Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit).
- Page 862 GD32F20x User Manual TBAP[15:0] Bits Fields Descriptions 31:0 TBAP[31:0] Transmit buffer address pointer bits These bits are automatically updated by TxDMA controller during operation. DMA current receive buffer address register (ENET_DMA_CRBADDR) 27.4.54. Address offset: 0x1054 Reset value: 0x0000 0000 This register can be accessed by byte(8-bit),half-word(16-bit) and word(32-bit).
- Page 863 GD32F20x User Manual Universal serial bus full-speed interface (USBFS) The USBFS is available on GD32F205xx and GD32F207xx series. 28.1. Overview USB Full-Speed (USBFS) controller provides a USB-connection solution for portable devices. USBFS supports host and device modes, as well as OTG mode with HNP (Host Negotiation Protocol) and SRP (Session Request Protocol).
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Page 864: Figure 28-1. Usbfs Block Diagram
GD32F20x User Manual 28.3. Block diagram Figure 28-1. USBFS block diagram interrupts Register AHB Slave Device bus Host Port control Control Data UTMI FIFO Transcation USB FS Scheduler Control VBUS USB Clock USB Clock Domain 48MHz 28.4. Signal description Table 28-1. USBFS signal description... -
Page 865: Figure 28-2. Connection With Host Or Device Mode
GD32F20x User Manual or OTG mode) and connection status. A typical connection is shown in Figure 28-2. Connection with host or device mode. Figure 28-2. Connection with host or device mode USBFS 5V Power Supply GPIO (needed in host mode) -
Page 866: Figure 28-3. Connection With Otg Mode
GD32F20x User Manual Figure 28-3. Connection with OTG mode USBFS 5V Power GPIO Supply VBus VBUS USB host function 28.5.2. USB Host Port State Host application may control state of the USB port via USBFS_HPCS register. After system initialization, the USB port stays at power-off state. After PP bit is set by software, the internal USB PHY is powered on, and the USB port changes into disconnected state. - Page 867 GD32F20x User Manual detected and will trigger a disconnection flag after a disconnection event. PRST bit is used for USB reset sequence. Application may set this bit to start a USB reset and clear this bit to finish the USB reset. This bit only takes effect when port is at connected or enabled state.
- Page 868 GD32F20x User Manual queues: periodic request queue and non-periodic request queue, to perform efficient transaction schedule. A request entry in a request queue described above may represent a USB transaction request or a channel operation request. Application needs to write packet into data FIFO via AHB register interface if it wants to start an OUT transaction on USB bus.
- Page 869 GD32F20x User Manual A USB device will enter into suspend state if the USB bus stays at IDLE state and there is no change on data lines for 3ms. When USB device is in suspend state, most of its clock are closed to save power.
- Page 870 GD32F20x User Manual only be implemented through the Micro-AB receptacle on a device. Since On-The-Go devices have a Micro-AB receptacle, an On-The-Go device can default to being either a host or a device, depending that which type of plug (Micro-A plug for host, Micro-B plug for device) is inserted.
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Page 871: Figure 28-5. Host Mode Fifo Space In Sram
GD32F20x User Manual SRAM describes the structure of these FIFOs in SRAM. The values in the figure are in term of 32-bit words. Figure 28-5. HOST mode FIFO space in SRAM USBFS provides a special register area for the internal data FIFO reading and writing. The addresses in the figure are addressed in bytes. -
Page 872: Figure 28-7. Device Mode Fifo Space In Sram
GD32F20x User Manual 1000h-1FFFh CH0 FIFO Write/Read 2000h-2FFFh CH1 FIFO Write/Read CH7 FIFO Write/Read 8000h-8FFFh Device mode In device mode, the data FIFO is divided into several parts: 1 Rx FIFO, and 4 Tx FIFOs (one for each IN endpoint). All the OUT endpoints share the Rx FIFO for receiving packets. The size and start offset of these data FIFOs should be configured by using USBFS_GRFLEN and USBFS_DIEPxTFLEN (x=0…3) registers. -
Page 873: Figure 28-8. Device Mode Fifo Access Register Mappimg
GD32F20x User Manual endpoint has its own FIFO access register space. Rx FIFO is also able to be accessed by using USBFS_GRSTATR/USBFS_GRSTATP register. Figure 28-8. Device mode FIFO access register mappimg 1000h-1FFFh IEP0 FIFO Write 2000h-2FFFh IEP1 FIFO Write 4000h-4FFFh... - Page 874 GD32F20x User Manual Program USBFS_HCHxINTEN register. Set the desired interrupt enable bits. Program USBFS_HCHxLEN register. PCNT is the number of packets in a transfer and TLEN is the total bytes number of all the transmitted or received packets in a transfer.
- Page 875 GD32F20x User Manual Disable the channel. Now the channel is in IDLE state and is ready for other transfers. OUT transfers operation sequence Initialize USBFS global registers. Initialize and enable the channel. Write a packet into the channel’s Tx FIFO (Periodic Tx FIFO or non-periodic Tx FIFO).
- Page 876 GD32F20x User Manual Program USBFS_DIEPxCTL or USBFS_DOEPxCTL register with desired transfer type, packet size, etc. Program USBFS_DIEPINTEN or USBFS_DOEPINTEN register. Set the desired interrupt enable bits. Program USBFS_DIEPxLEN or USBFS_DOEPxLEN register. PCNT is the number of packets in a transfer and TLEN is the total bytes number of all the transmitted or received packets in a transfer.
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Page 877: Table 28-2. Usbfs Global Interrupt
GD32F20x User Manual the status flags report the transaction result. After all the data packets in a transfer are successfully received on USB bus, USBFS pushes a TF status entry into the Rx FIFO on top of the last packet data. Thus, after reading and poping all the received data packet, the TF status entry is read. - Page 878 GD32F20x User Manual Wake up interrupt can be triggered when USBFS is in suspend state, even if when the USBFS’s clocks are stopped. The source of the wake up interrupt is WKUPIF bit in USBFS_GINTF register.
- Page 879 GD32F20x User Manual 28.7. Register definition USBFS base address: 0x5000 0000 Global control and status registers 28.7.1. Global OTG control and status register (USBFS_GOTGCS) Address offset: 0x0000 Reset value: 0x0000 0800 This register has to be accessed by word (32-bit)
- Page 880 GD32F20x User Manual protocol. Note: Only accessible in host mode. IDPS ID pin status Voltage level of connector ID pin 0: USBFS is in A-Device mode 1: USBFS is in B-Device mode Note: Accessible in both device and host modes.
- Page 881 GD32F20x User Manual Note: Only accessible in device mode. SRPS SRP success This bit is set by the core when SRP succeeds, and this bit is cleared when SRPREQ bit is set. 0: SRP fails 1: SRP successes Note: Only accessible in device mode.
- Page 882 GD32F20x User Manual to get the result of HNP. Note: Accessible in both device and host modes. SRPEND SRPEND Set by the core when a SRP ends. Read the SRPS in USBFS_GOTGCS register to get the result of SRP. Note: Accessible in both device and host modes.
- Page 883 GD32F20x User Manual 0: NPTXFEIF will be triggered when the non-periodic Tx FIFO is half empty 1: NPTXFEIF will be triggered when the non-periodic Tx FIFO is completely empty 6：1 Reserved Must be kept at reset value. GINTEN Global interrupt enable 0: Global interrupt is not enabled.
- Page 884 GD32F20x User Manual The application must wait at least 25 ms for the change taking effect after setting the force bit. Note: Accessible in both device and host modes. 28:14 Reserved Must be kept at reset value. 13:10 UTT[3:0] USB turnaround time Turnaround time in PHY clocks.
- Page 885 GD32F20x User Manual Bits Fields Descriptions AHBMIDL AHB master idle, this bit is always 1 for both device and host mode. 30:11 Reserved Must be kept at reset value. 10:6 TXFNUM[4:0] Tx FIFO number Indicates which Tx FIFO will be flushed when TXFF bit in the same register is set.
- Page 886 GD32F20x User Manual Note: Only accessible in host mode. HCSRST HCLK soft reset Set by the application to reset AHB clock domain circuit. Hardware automatically clears this bit after the reset process completes. After setting this bit, application should wait until this bit is cleared before any other operation on USBFS.
- Page 887 GD32F20x User Manual Set by the core when ID status changes. Note: Accessible in both device and host modes. Reserved Must be kept at reset value. PTXFEIF Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the periodic Tx FIFO is either half or completely empty.
- Page 888 GD32F20x User Manual after the respective endpoint’s flags which cause this interrupt are cleared. Note: Only accessible in device mode. IEPIF IN endpoint interrupt flag Set by USBFS when one of the IN endpoints in device mode has raised an interrupt.
- Page 889 GD32F20x User Manual Write 1 to SGINAK bit in the USBFS_DCTL register and USBFS will set GNPINAK flag after the SGINAK takes effect. Note: Only accessible in device mode. NPTXFEIF Non-Periodic Tx FIFO empty interrupt flag This interrupt is triggered when the non-periodic transmit FIFO is either half or completely empty.
- Page 890 GD32F20x User Manual application. When an interrupt enable bit is disabled, the interrupt associated with that bit is not generated. However, the global Interrupt flag register bit corresponding to that interrupt is still set. This register has to be accessed by word (32-bit)
- Page 891 GD32F20x User Manual 0: Disable host channels interrupt 1: Enable host channels interrupt Note: Only accessible in host mode. HPIE Host port interrupt enable 0: Disable host port interrupt 1: Enable host port interrupt Note: Only accessible in host mode.
- Page 892 GD32F20x User Manual 0: Disable enumeration finish interrupt 1: Enable enumeration finish interrupt Note: Only accessible in device mode. RSTIE USB reset interrupt enable 0: Disable USB reset interrupt 1: Enable USB reset interrupt Note: Only accessible in device mode.
- Page 893 GD32F20x User Manual Note: Accessible in both device and host modes. MFIE Mode fault interrupt enable 0: Disable mode fault interrupt 1: Enable mode fault interrupt Note: Accessible in both device and host modes. Reserved Must be kept at reset value.
- Page 894 GD32F20x User Manual Others: Reserved 16:15 DPID[1:0] Data PID The Data PID of the received packet 00: DATA0 10: DATA1 Others: Reserved 14:4 BCOUNT[10:0] Byte count The byte count of the received IN data packet. CNUM[3:0] Channel number The channel number to which the current received packet belongs.
- Page 895 GD32F20x User Manual The byte count of the received data packet. EPNUM[3:0] Endpoint number The endpoint number to which the current received packet belongs. Global receive FIFO length register (USBFS_GRFLEN) Address offset: 0x024 Reset value: 0x0000 0200 This register has to be accessed by word (32-bit)
- Page 896 GD32F20x User Manual r/rw Host Mode: Bits Fields Descriptions 31:16 HNPTXFD[15:0] Host Non-periodic Tx FIFO depth In terms of 32-bit words. 1≤HNPTXFD≤1024 15:0 HNPTXRSAR[15:0] Host Non-periodic Tx RAM start address The start address for non-periodic Tx FIFO RAM is in term of 32-bit words.
- Page 897 GD32F20x User Manual Bits Fields Descriptions Reserved Must be kept at reset value. 30:24 NPTXRQTOP[6:0] Top entry of the non-periodic Tx request queue Entry in the non-periodic transmit request queue. Bits 30:27: Channel number Bits 26:25: 00: IN/OUT token 01: Zero-length OUT packet 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel.
- Page 898 GD32F20x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. VBUSIG VBUS ignored When this bit is set, USBFS doesn’t monitor the voltage on VBUS pin and always consider V voltage as valid both in host mode and in device mode, then free the V pin for other usage.
- Page 899 GD32F20x User Manual Core ID register (USBFS_CID) Address offset: 0x003C Reset value: 0x0000 1000 This register contains the Product ID. This register has to be accessed by word (32-bit) Bits Fields Descriptions 31:0 CID[31:0] Core ID Software can write or read this field and uses this field as a unique ID for its...
- Page 900 GD32F20x User Manual 31:16 HPTXFD[15:0] Host Periodic Tx FIFO depth In terms of 32-bit words. 1 ≤ HPTXFD ≤ 1024 15:0 HPTXFSAR[15:0] Host periodic Tx FIFO RAM start address The start address for host periodic Tx FIFO RAM is in term of 32-bit words.
- Page 901 GD32F20x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. CLKSEL[1:0] Clock select for usbclock 01: 48MHz clock others: reserved Host frame interval register (USBFS_HFT) Address offset: 0x0404 Reset value: 0x0000 BB80 This register sets the frame interval for the current enumerating speed when USBFS controller is enumerating.
- Page 902 GD32F20x User Manual is enabled after a port reset, USBFS use a proper value according to the current speed, and software can write to this field to change the value. This value should be calculated using the frequency described below:...
- Page 903 GD32F20x User Manual Bits Fields Descriptions 31:24 PTXREQT[7:0] Top entry of the periodic Tx request queue Entry in the periodic transmit request queue. Bits 30:27: Channel Number Bits 26:25: 00: IN/OUT token 01: Zero-length OUT packet 11: Channel halt request Bit 24: Terminate Flag, indicating last entry for selected channel.
- Page 904 GD32F20x User Manual When a channel interrupt is triggered, USBFS set a corresponding bit in this register and software should read this register to know which channel is asserting interrupts. This register has to be accessed by word (32-bit) Bits...
- Page 905 GD32F20x User Manual 31:8 Reserved Must be kept at reset value. CINTEN[7:0] Channel interrupt enable 0: Disable channel n interrupt 1: Enable channel n interrupt Each bit represents a channel: Bit 0 for channel 0, bit 7 for channel 7.
- Page 906 GD32F20x User Manual 1: Port is powered on 11:10 PLST[1:0] Port line status Report the current state of USB data lines 10: State of DP line 11: State of DM line Reserved Must be kept at reset value. PRST Port reset Application sets this bit to start a reset signal on USB port.
- Page 907 GD32F20x User Manual writing 1 to this bit. PCST Port connect status 0: Device is not connected to the port 1: Device is connected to the port Host channel-x control register (USBFS_HCHxCTL) (x = 0..7 where x = channel_number) Address offset: 0x0500 + (channel_number × 0x20)
- Page 908 GD32F20x User Manual 21:20 Reserved Must be kept at reset value. 19:18 EPTYPE[1:0] Endpoint type The transfer type of the endpoint that this channel wants to communicate with. 00: Control 01: Isochronous 10: Bulk 11: Interrupt Low-Speed device The device that this channel wants to communicate with is a Low-Speed Device.
- Page 909 GD32F20x User Manual Bits Fields Descriptions 31:11 Reserved Must be kept at reset value. DTER Data toggle error The IN transaction gets a data packet but the PID of this packet doesn’t match DPID bits in USBFS_HCHxLEN register. REQOVR Request queue overrun The periodic request queue is full when software starts new transfers.
- Page 910 GD32F20x User Manual Host channel-x interrupt enable register (USBFS_HCHxINTEN) (x = 0..7, where x = channel number) Address offset: 0x050C + (channel_number × 0x20) Reset value: 0x0000 0000 This register contains the interrupt enable bits for the flags in USBFS_HCHxINTF register. If a bit in this register is set by software, the corresponding bit in USBFS_HCHxINTF register is able to trigger a channel interrupt.
- Page 911 GD32F20x User Manual 1: Enable ACK interrupt NAKIE NAK interrupt enable 0: Disable NAK interrupt 1: Enable NAK interrupt STALLIE STALL interrupt enable 0: Disable STALL interrupt 1: Enable STALL interrupt Reserved Must be kept at reset value. CHIE Channel halted interrupt enable...
- Page 912 GD32F20x User Manual triggered if the Data PID doesn’t match. After the transfer starts, USBFS changes and toggles this field automatically following the USB protocol. 00: DATA0 10: DATA1 11: SETUP (For control transfer only) 01: Reserved 28:19 PCNT[9:0] Packet count The number of data packets desired to be transmitted (OUT) or received (IN) in a transfer.
- Page 913 GD32F20x User Manual Bits Fields Descriptions 31:13 Reserved Must be kept at reset value. 12:11 EOPFT[1:0] End of periodic frame time This field defines the percentage time point in a frame that the end of periodic frame (EOPF) flag should be triggered.
- Page 914 GD32F20x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. POIF Power-on initialization finished Software should set this bit to notify USBFS that the registers are initialized after waking up from power down state. CGONAK Clear global OUT NAK Software sets this bit to clear GONS bit in this register.
- Page 915 GD32F20x User Manual cause the host to detect a device disconnect. 0: No soft disconnect generated. 1: Generate a soft disconnection. RWKUP Remote wakeup In suspend state, software can use this bit to generate a Remote wake up signal to inform host that it should resume the USB bus.
- Page 916 GD32F20x User Manual Bits Fields Descriptions 31:22 Reserved Must be kept at reset value. 21:8 FNRSOF[13:0] The frame number of the received SOF. USBFS always update this field after receiving a SOF token Reserved Must be kept at reset value.
- Page 917 GD32F20x User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. IEPNEEN IN endpoint NAK effective interrupt enable bit 0: Disable IN endpoint NAK effective interrupt 1: Enable IN endpoint NAK effective interrupt Reserved Must be kept at reset value.
- Page 918 GD32F20x User Manual Bits Fields Descriptions 31:7 Reserved Must be kept at reset value. BTBSTPEN Back-to-back SETUP packets (Only for control OUT endpoint) interrupt enable bit 0: Disable back-to-back SETUP packets interrupt 1: Enable back-to-back SETUP packets interrupt Reserved Must be kept at reset value.
- Page 919 GD32F20x User Manual Bits Fields Descriptions 31:20 Reserved Must be kept at reset value. 19:16 OEPITB[3:0] Device all OUT endpoint interrupt bits Each bit represents an OUT endpoint: Bit 16 for OUT endpoint 0, bit 19 for OUT endpoint 3.
- Page 920 GD32F20x User Manual 15:4 Reserved Must be kept at reset value. IEPIE[3:0] IN endpoint interrupt enable bits 0: Disable IN endpoint n interrupt 1: Enable IN endpoint n interrupt Each bit represents an IN endpoint: Bit 0 for IN endpoint 0, bit 3 for IN endpoint 3.
- Page 921 GD32F20x User Manual Bits Fields Descriptions 31:12 Reserved Must be kept at reset value. 11:0 DVBUSPT[11:0] Device V pulsing time This field defines the pulsing time for V The true pulsing time is BUS. 1024*DVBUSPT[11:0] *T , where T is the period time of USB...
- Page 922 GD32F20x User Manual Bits Fields Descriptions 31:4 Reserved Must be kept at reset value. IEPTXFEIE[3:0] IN endpoint Tx FIFO empty interrupt enable bits This field controls whether the TXFE bits in USBFS_DIEPxINTF registers are able to generate an endpoint interrupt bit in USBFS_DAEPINT register.
- Page 923 GD32F20x User Manual 25:22 TXFNUM[3:0] Tx FIFO number Define the Tx FIFO number of IN endpoint 0. STALL STALL handshake Software can set this bit to send STALL handshake when receiving IN token. USBFS will clear this bit after a SETUP token is received on the corresponding OUT endpoint 0.
- Page 924 GD32F20x User Manual rw/rs Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint. Software should follow the operation guide to disable or enable an endpoint.
- Page 925 GD32F20x User Manual For control IN endpoint: Only USBFS can clear this bit when a SETUP token is received on the corresponding OUT endpoint. Software is not able to clear it. For interrupt or bulk IN endpoint: Only software can clear this bit Reserved Must be kept at reset value.
- Page 926 GD32F20x User Manual Device OUT endpoint 0 control register (USBFS_DOEP0CTL) Address offset: 0x0B00 Reset value: 0x0000 8000 This register has to be accessed by word (32-bit) Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS.
- Page 927 GD32F20x User Manual 0:Snoop mode disabled 1:Snoop mode enabled 19:18 EPTYPE[1:0] Endpoint type This field is fixed to ‘00’ for control endpoint. NAKS NAK status This bit controls the NAK status of USBFS when both STALL bit in this register...
- Page 928 GD32F20x User Manual rw/rs Bits Fields Descriptions EPEN Endpoint enable Set by the application and cleared by USBFS. 0: Endpoint disabled 1: Endpoint enabled Software should follow the operation guide to disable or enable an endpoint. Endpoint disable Software can set this bit to disable the endpoint. Software should follow the operation guide to disable or enable an endpoint.
- Page 929 GD32F20x User Manual takes effect. For control OUT endpoint: Only USBFS can clear this bit when a SETUP token is received on the corresponding OUT endpoint. Software is not able to clear it. For interrupt or bulk OUT endpoint: Only software can clear this bit.
- Page 930 GD32F20x User Manual 14:11 Reserved Must be kept at reset value. 10:0 MPL[10:0] This field defines the maximum packet length in bytes. Device IN endpoint x interrupt flag register (USBFS_DIEPxINTF) (x = 0..3, where x = endpoint_number) Address offset: 0x0908 + (endpoint_number × 0x20)
- Page 931 GD32F20x User Manual This flag is triggered if the device waiting for a handshake is timeout in a control IN transaction. Reserved Must be kept at reset value. EPDIS Endpoint disabled This flag is triggered when an endpoint is disabled by the software’s request.
- Page 932 GD32F20x User Manual data packet and sends a NAK handshake in this case. STPF SETUP phase finished (Only for control OUT endpoint) This flag is triggered when a setup phase finished, i.e. USBFS receives an IN or OUT token after a setup token.
- Page 933 GD32F20x User Manual the packet. Device OUT endpoint 0 transfer length register (USBFS_DOEP0LEN) Address offset: 0x0B10 Reset value: 0x0000 0000 This register has to be accessed by word (32-bit) Bits Fields Descriptions Reserved Must be kept at reset value. 30:29...
- Page 934 GD32F20x User Manual OUT transfer. Program this field before the endpoint is enabled. Each time software reads out a packet from the Rx FIFO, this field is decreased by the byte size of the packet. Device IN endpoint-x transfer length register (USBFS_DIEPxLEN) (x = 1..3, where x = endpoint_number) Address offset: 0x910 + (endpoint_number ×...
- Page 935 GD32F20x User Manual r/rw Bits Fields Descriptions Reserved Must be kept at reset value. 30:29 RXDPID[1:0] Received Data PID (for isochronous OUT endpoints) This field saves the PID of the latest received data packet on this endpoint. 00: DATA0 10: DATA1...
- Page 936 GD32F20x User Manual Device IN endpoint-x transmit FIFO status register (USBFS_DIEPxTFSTAT) (x = 0..3, where x = endpoint_number) Address offset: 0x0918 + (endpoint_number × 0x20) Reset value: 0x0000 0200 This register contains the information of each endpoint’s Tx FIFO. This register has to be accessed by word (32-bit)
- Page 937 GD32F20x User Manual Bits Fields Descriptions 31:2 Reserved Must be kept at reset value. SHCLK Stop HCLK Stop the HCLK to save power. 0: HCLK is not stopped 1: HCLK is stopped SUCLK Stop the USB clock Stop the USB clock to save power.
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Page 938: Table 29-1. Revision History
GD32F20x User Manual Revision history Table 29-1. Revision history Revision No. Description Date Initial Release Jul.1, 2015 Adapt To New Name Convention Jun.5, 2017 Adapt To New Document Specification Oct.25, 2018 Modify the ENET RxDMA descriptor word 0 (RDES0) Bit15 Oct.8, 2019... - Page 939 Important Notice This document is the property of GigaDevice Semiconductor Inc. and its subsidiaries (the "Company"). This document, including any product of the Company described in this document (the “Product”), is owned by the Company under the intellectual property laws and treaties of the People’s Republic of China and other jurisdictions worldwide.
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