Cypress CY8CKIT-064B0S2-4343W Manual page 21

3.
3.1
CY8CKIT-064B0S2-4343W PSoC 64 "Secure Boot" Wi-Fi BT Pioneer Kit Guide, Document Number: 002-29286 Rev. *E
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Kit Operation
This chapter introduces you to various features of the PSoC 64 "Secure Boot" Wi-Fi BT Pioneer
Board, including the theory of operation and the onboard KitProg3 programming and debugging
functionality, USB-UART and USB-I2C bridges.
Theory of Operation
The PSoC 64 "Secure Boot" Wi-Fi BT Pioneer Board is built around a PSoC 64 chip.
shows the block diagram of the PSoC 64 device used on the board. For details of device features,
see the device datasheet.
Figure 3-1. PSoC 64 Block Diagram
PSoC 64 "Secure Boot" MCU
Color Key:
CYB0644xxZI-S2D44
Power Modes and Domains
System LP/ULP Mode
System Resources
CPUs Active/Sleep
Power
OVP LVD
System
POR BOD
DeepSleep Mode
Buck Regulator
XRES Reset
System
Hibernate Mode
Backup Regs
Backup
Domain
CPU Subsystem
Cortex M4F CPU
150/50 MHz, 1.1/0.9 V
SWJ, ETM, ITM, CTI
Cortex M0+ CPU
100/25 MHz, 1.1/0.9 V
SWJ, MTB, CTI
Crypto
DES/TDES, AES, SHA, CRC,
TRNG, RSA/ECC
Accelerator
Flash
2048 KB + 32 KB + 32 KB
8 KB cache for each CPU
Programmable Analog
SAR ADC 12 bit
Clocks
Temperature Sensor
IMO ECO
FLL 2x PLL
2x MCWDT
ILO WDT
RTC WCO
PMIC Control
SCB
Audio Subsystem
3x DMA
Controller
SRAM0
512 KB
SRAM1
256 KB
SRAM2
256 KB
ROM
64 KB
USB
PHY
Figure 3-1
20