Jtag Reset - Microchip Technology MEC172 Series Layout Manual

The 20 pin connector is a Samtec FTSH-110-01 with pin 7 removed.
FIGURE 3-3: 20-PIN CORTEX DEBUG WITH TRACE SUPPORT (0.05") CONNECTOR
3.4 JTAG Internal Pull-Up
The firmware can select which debug pins to enable the internal pull-high. Default is disabled. Please see the MEC1721/
MEC1723 Data Sheet DEBUG ENABLE REGISTER (4000_FC20h) at section 47.8.5 for more information.
3.5

JTAG Reset

When the JTAG_RST# pin is not asserted (logic'1'), the JTAG_TDI, JTAG_TDO, JTAG_TCK, JTAG_TMS signal func-
tions in the JTAG interface are unconditionally routed to the JTAG interface; the Pin Control register for these pins has
no effect. When the JTAG_RST# pin is asserted (logic'0'), the JTAG_TDI, JTAG_TDO, JTAG_TCK, JTAG_TMS signal
functions in the JTAG interface are not routed to the interface and the Pin Control Register for these pins controls the
muxing. The pin control registers cannot route the JTAG interface to the pins. The system board designer should termi-
nate this pin in all functional states using jumpers, pullup or pulldown resistors, and so forth.
JTAG registers are set to their initial values by the assertion of the JTAG_RST# pin. The JTAG_RST# pin must be held
low while the MEC1721/MEC1723 devices are powering up so the registers can be set to their proper default values. If
JTAG_RST# is high during power up, the JTAG registers may be set to unpredictable values. This can trigger unwanted
test modes and the system may not run correctly. As a result, the JTAG_RST# pin must be held low for at least 5.00
msec when applying VTR power.
Note: For more details on the JTAG_RST# pin, in particular JTAG_RST# functionality with respect to VTR power
up events, as well as RESETI# reset input pin transitions, see the JTAG section in the MEC1721/MEC1723
Data Sheet.
The minimum required JTAG signals as shown in
options to handle the absence of this pin as followed:
• Production Mode with JTAG Port Disable:
- Hold the JTAG_RST# pin low with pulldown resistor to disable the JTAG port. Add a pullup resistor option (do
not populate) for potential failure analysis to allow use of the JTAG interface. In this case, the JTAG_RST# pin
must be manually held low at least 5.00 msec on power up.
• Production Mode with JTAG Port Enable:
- Add a jumper to hold the JTAG_RST# line low during power up, then remove the jumper in order to ensure
that it meets the 5.00 msec timing requirement.
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Table 3-1 does not include the JTAG_RST# signal. There are several
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