Microchip Technology MEC172 Series Layout Manual page 18

AN3759
TABLE 2-5: MEC1721/MEC1723 NON-SHARED DUAL SPI FLASH DEVICE SPECIFICATIONS
L0 Connection between MEC1721/MEC1723, 2 SPI flash devices and ter-
mination resistors.
L1 PCB trace from the MEC1721/MEC1723 termination resistor to the PCB
trace connection from 2 SPI flash devices.
L2 PCB trace from the first SPI Flash termination resistor to the PCB trace
connection from the second SPI flash and MEC1721/MEC1723.
L3 PCB trace from the second SPI flash termination resistor to the PCB
trace connection from the MEC1721/MEC1723 and the first SPI flash.
L4 PCB trace from MEC1721/MEC1723 to the dual SPI flash for chip select. L4 = L1 + L3 + (2 x L0) or
R1 These resistors are between the PCB trace and the MEC1721/
MEC1723.
R2 These resistors are between the PCB trace and the first SPI flash.
R3 These resistors are between the PCB trace and the second SPI flash.
R4/R5 This is a Pull-High resistor (to +3.3V) for SPI CS connections. This pull-
high must connect to the same power rail of the SPI flash.
R6 Pull-high resistor to +3.3V for SPI IO0/IO1/IO2/IO3 data bus connec-
tions, between the MEC1721/MEC1723 or Host/PCH and the SPI flash
devices, and close to connection of L1, L2 & L3 traces. This pull-high
must connect to the same power rail of the SPI flash.
Note 2-7 The final value of the series resistors should be chosen based on performing electrical analysis to
ensure the electrical timings and min/max voltage specifications are met for each device (SPI, EC,
PCH or other Host SPI controller) including the undershoot/ overshoot specifications for the
MEC1721/MEC1723 (-0.3V min. to V
2.7.5 SPI FLASH IMPLEMENTATION RECOMMENDATIONS
The following recommendations are for both Shared and Non-Shared SPI Flash Implementations.
• The MEC1721/MEC1723 SPI memory interface has serial flash device compatibility requirements that are defined
in the MEC1721/MEC1723 Data Sheet. Please make sure the selected SPI flash meets these requirements.
• SPI_CLK must be 20mils spacing from any other high frequency (>1GHz) signal.
• The SPI flash parts should support operating at 12MHz for the ROM code loader, and up to 48MHz clock speed in
RAM code loading.
• The designer should follow the SPI interface host design guidelines.
• IBIS models are available to aid in simulating the SPI system topology.
• The chip select CS# signals should have weak pullup resistors to the same power rail as the SPI flash. The pullup
resistor value should meet the rise time requirements of the SPI flash.
• EC firmware must configure the MEC1721/MEC1723 SPI memory interface to disable mode, which will tri-state
the SPI memory interface from MEC1721/MEC1723 to the SPI flash, before releasing the RSMRST# signal.
• This configuration requires that the PCH tri-state its SPI flash pins when RSMRST# is asserted.
• The characteristic impedance of the PCB trace should be 50 ohms +/-15% at 50MHz operating frequency.
• Within the SPI flash device, Schmitt trigger inputs are assumed on both the clock line and IO data lines.
• Within the Intel PCH, a Schmitt trigger input is assumed on the IO data lines.
• The output drivers for the SPI flash chip select pins should be programmed as open-drain using the GPIO Pin
Control registers.
DS00003759B-page 18
Description
+0.3V max).
CC1
 2021 Microchip Technology Inc. and its subsidiaries
Spec
0.1-inch to 0.5-inch
L1 = L2 = L3 within +/- 10%
These trace connections can
equal 1-inch up to 5-inches.
See Note 2-5.
L4 = L2 + L3 + (2 x L0)
+/- 0.100 inches.
3.3V - 35 ohm 1.8V - 20 ohm
See Note 2-7.
3.3V - 10 ohm; 1.8V - 2.5
ohm
See Note 2-7.
3.3V - 2.5 ohm; 1.8V - 0 ohm
See Note 2-7
2.2K ohm
4.7K ohm