Microchip Technology dsPIC30F Introduction Manual
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Microchip Technology dsPIC30F Introduction Manual

Microchip Technology dsPIC30F Introduction Manual

Dspic digital signal controller
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Microchip Technology Inc.
DS
Digital Signal Controller
Introduction to the dsPIC30F
Architecture (Part 1 of 2)
© 2004 Microchip Technology Incorporated. All Rights Reserved.
Introduction to the dsPIC30F Architecture (Part 2)
1
Welcome to the second dsPIC30F web seminar: Introduction to the
dsPIC30F Architecture, Part 1. The focus in today's seminar will be on
the basics of the Central Processing Unit, or CPU, architecture, and the
DSP elements of the dsPIC30F architecture.
Page 1

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Summary of Contents for Microchip Technology dsPIC30F

  • Page 1 Introduction to the dsPIC30F Architecture (Part 2) Welcome to the second dsPIC30F web seminar: Introduction to the dsPIC30F Architecture, Part 1. The focus in today’s seminar will be on the basics of the Central Processing Unit, or CPU, architecture, and the DSP elements of the dsPIC30F architecture.
  • Page 2 CPU Architecture Overview © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) Let us begin by taking a closer look at the dsPIC30F CPU architecture. Page 2...

  • Page 3: Architecture Highlights

    16-bit MCU and DSP. Single instruction thread execution simplifies application debug and ensures deterministic operation. The dsPIC30F architecture is a modified Harvard Bus Architecture. This means that the program and data memories are accessed by separate buses. However, there are mechanisms to store and access constant data from the program memory space.
  • Page 4 © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) The basic programmer’s model of the dsPIC30F is shown here. The dsPIC30F contains sixteen 16-bit general purpose working registers W0 through W15, which are collectively known as W registers.

  • Page 5: Program Memory Organization

    © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) The Program Memory map of the dsPIC30F includes the reset vector, interrupt vector table, an alternate vector table, user Program Flash memory, Data EEPROM and configuration memory space.

  • Page 6: Data Memory Organization

    Function Registers and Data RAM. However, unlike the PIC18F family which featured a banked data memory using a register to select the required bank, the dsPIC30F family has a linear data memory space. It is both word and byte addressable by most instructions, although the native data width is 16-bits.
  • Page 7 The physical end address of RAM is hex27FF for this device. The memory is depicted here with each word containing 16 bits. As mentioned earlier, each byte in the dsPIC30F data space has a unique address. Hence, two addresses are shown for each word - the even address for the least significant byte and the odd address for the most significant byte.
  • Page 8 PSV mechanism 0xFFFF 0xFFFE © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) There are some key differences between the addressing modes supported by MAC-class instructions and those supported by all other instructions.

  • Page 9: Instruction Set Overview

    Boosts code efficiency (assembly or C) © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) Let us now discuss the instruction set supported by the dsPIC30F architecture. The dsPIC30F CPU consists of 84 different instructions. If one considers the various addressing modes possible, there are nearly 250 possible opcodes.

  • Page 10: Instruction Groups

    SHADOW / STACK instructions CONTROL instructions DSC instructions © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) The instruction set may be divided into different classes: In general, Move instructions transfer data between Data RAM, special function registers or SFR’s, and the W registers.

  • Page 11: Addressing Modes

    Bit-Reversed (for FFT) © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) The dsPIC30F addressing modes provide a high level of flexibility and orthogonality to make application code easy to develop and efficient to execute.

  • Page 12: Dsp Features

    © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) Now that we have studied some fundamental facts about the dsPIC30F architecture, let us explore the Digital Signal Processing functionality of the dsPIC30F. These include several features that are fairly typical of Digital Signal Processors, but are virtually non-existent in the Microcontroller arena.
  • Page 13 The dsPIC30F architecture provides a cost-effective solution for these DSP-oriented requirements. Most instructions execute in a single cycle on the dsPIC30F. This is also true for fundamental DSP operations like Multiply-Accumulate, or MAC. Moreover, the dual...
  • Page 14 © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) But that’s not all! The dsPIC30F provides more features to ensure efficient DSP algorithm performance. It contains a 40-bit barrel shifter, which can shift data in the accumulator, W register or RAM up to 16-bits left or right, in a single instruction cycle.
  • Page 15 Introduction to the dsPIC30F Architecture (Part 2) This high level block diagram depicts the core elements of the dsPIC30F architecture. Notice the distinct Program Memory and Data Memory blocks, consistent with a Harvard Architecture. However, by using the Table instructions or PSV, constant data coefficients may be stored and accessed from Program Memory.
  • Page 16 © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) For more information, here are references to some important documents that contain a wealth of information about the dsPIC30F family of devices. The Family Reference Manual contains detailed information about the architecture and peripherals, whereas the Programmer’s Reference...
  • Page 17 Data Sheet DS70117 Microchip Web Site: www.microchip.com © 2004 Microchip Technology Incorporated. All Rights Reserved. Introduction to the dsPIC30F Architecture (Part 2) For device-specific information such as pinout diagrams, packaging and electrical characteristics, the device datasheets listed here are the best source of information.

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