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Microchip Technology dsPIC30F Family Reference Manual

High performance digital signal controllers

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dsPIC30F

Family Reference Manual

High Performance

Digital Signal Controllers

© 2004 Microchip Technology Inc.

DS70046C

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Page 1 Family Reference Manual High Performance Digital Signal Controllers © 2004 Microchip Technology Inc. DS70046C...
Page 2 PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies.
Page 3: Table Of Contents
Introduction ..............................5-2 Table Instruction Operation ..........................5-2 Control Registers ............................. 5-5 Run-Time Self-Programming (RTSP) ....................... 5-9 Data EEPROM Programming ........................5-14 Design Tips ..............................5-20 Related Application Notes ..........................5-21 Revision History ............................. 5-22  2004 Microchip Technology Inc. DS70046C-page iii...
Page 4 Using the RCON Status Bits .......................... 8-10 Device Reset Times ............................8-11 Device Start-up Time Lines ..........................8-13 Special Function Register Reset States ......................8-16 Design Tips ..............................8-17 Related Application Notes ..........................8-18 Revision History ............................. 8-19  2004 Microchip Technology Inc. DS70046C-page iv...
Page 5 Reading and Writing into 32-bit Timers ......................12-21 Timer Operation in Power Saving States ..................... 12-21 Peripherals Using Timer Modules ........................ 12-22 Design Tips ..............................12-24 Related Application Notes ..........................12-25 Revision History ............................12-26  2004 Microchip Technology Inc. DS70046C-page v...
Page 6 PWM Update Lockout ..........................15-35 PWM Special Event Trigger ......................... 15-35 Operation in Device Power Saving Modes ....................15-36 Special Features for Device Emulation ......................15-37 Related Application Notes ..........................15-40 Revision History ............................15-41  2004 Microchip Technology Inc. DS70046C-page vi...
Page 7 Operation During Sleep and Idle Modes ...................... 17-49 Effects of a Reset ............................17-49 Special Function Registers Associated with the 10-bit A/D Converter ............17-50 Design Tips ..............................17-51 Related Application Notes ..........................17-52 Revision History ............................17-53  2004 Microchip Technology Inc. DS70046C-page vii...
Page 8 Other Features of the UART ........................19-21 UART Operation During CPU Sleep and Idle Modes ................... 19-21 Registers Associated with UART Module ..................... 19-22 Design Tips ..............................19-23 Related Application Notes ..........................19-24 Revision History ............................19-25  2004 Microchip Technology Inc. DS70046C-page viii...
Page 9 DCI Operation .............................. 22-10 Using the DCI Module ..........................22-17 Operation in Power Saving Modes ....................... 22-28 Registers Associated with DCI ........................22-28 Design Tips ..............................22-30 Related Application Notes ..........................22-31 Revision History ............................22-32  2004 Microchip Technology Inc. DS70046C-page ix...
Page 10 25-1 Introduction ..............................25-2 Microchip Hardware and Language Tools ...................... 25-2 Third Party Hardware/Software Tools and Application Libraries ..............25-6 dsPIC30F Hardware Development Boards ....................25-11 Related Application Notes ..........................25-15 Revision History ............................25-16 SECTION 26. APPENDIX Appendix A: I2C™ Overview........................... 26-2 Appendix B: CAN Overview ..........................
Page 11: Section 1. Introduction
This section of the manual contains the following topics: Introduction ........................1-2 Manual Objective ......................1-2 Device Structure......................1-3 Development Support ....................1-4 Style and Symbol Conventions ..................1-4 Related Documents ....................... 1-6 Revision History ......................1-7 © 2004 Microchip Technology Inc. DS70048C-page 1-1...
Page 12: Introduction
This literature can be obtained from your local sales office, or downloaded from the Microchip web site (www.microchip.com). Manual Objective PICmicro and dsPIC30F devices are grouped by the size of their Instruction Word and Data Path. The current device families are: Base-Line:...
Page 13: Device Structure
Watchdog Timer and Power Saving Modes Flash and EEPROM Programming Device Configuration 1.3.3 Peripherals The dsPIC30F has many peripherals that allow the device to be interfaced to the external world. The peripherals discussed in this manual include: I/O Ports Timers Input Capture Module...
Page 14: Development Support
Family Reference Manual Development Support Microchip offers a wide range of development tools that allow users to efficiently develop and debug application code. Microchip’s development tools can be broken down into four categories: Code generation Hardware/Software debug Device programmer Product evaluation boards A full description of each of Microchip’s development tools is discussed in Section...
Page 15 A Note is always in a shaded box (as below), unless used in a table, where it is at the bottom of the table (as in this table). Note: This is a Note in a shaded note box. © 2004 Microchip Technology Inc. DS70048C-page 1-5...
Page 16: Related Documents
(www.microchip.com) for the latest published technical documentation. 1.6.1 Microchip Documentation The following dsPIC30F documentation is available from Microchip at the time of this writing. Many of these documents provide application specific information that gives actual examples of using, programming and designing with dsPIC30F MCUs.
Page 17: Revision History
Revision B throughout the manual. Revision C There were no technical content revisions to this section of the manual, however, this section was updated to reflect Revision C throughout the manual. © 2004 Microchip Technology Inc. DS70048C-page 1-7...
Page 18 Family Reference Manual NOTES: DS70048C-page 1-8 © 2004 Microchip Technology Inc.
Page 19 DSP Engine ......................... 2-18 Divide Support ......................2-27 Instruction Flow Types ....................2-27 Loop Constructs......................2-30 2.10 Address Register Dependencies ................. 2-35 2.11 Register Maps......................2-38 2.12 Related Application Notes.................... 2-40 2.13 Revision History ......................2-41 © 2004 Microchip Technology Inc. DS70049C-page 2-1...
Page 20: Introduction
(W15) operates as a software stack pointer for interrupts and calls. The dsPIC30F instruction set has two classes of instructions: the MCU class of instructions and the DSP class of instructions. These two instruction classes are seamlessly integrated into the architecture and execute from a single execution unit.
Page 21: Section 2. Cpu
Section 2. CPU Figure 2-1: dsPIC30F CPU Core Block Diagram X Address Bus Y Data Bus X Data Bus Data Latch Data Latch Interrupt PSV & Table Controller Y Data X Data Data Access Control Block (4 Kbytes) (4 Kbytes)
Page 22: Programmer's Model
Family Reference Manual Programmer’s Model The programmer’s model for the dsPIC30F is shown in Figure 2-2. All registers in the program- mer’s model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1.
Page 23 DOEND DO Loop End Address OAB SAB DA DC IPL<2:0> Status Register CORCON Core Control Register Note: DCOUNT, DOSTART and DOEND have one level of shadow registers (not shown) for nested DO loops. © 2004 Microchip Technology Inc. DS70049C-page 2-5...
Page 24 0x0004 in memory. W2 is also mapped to this address in memory. Even though this is an unlikely event, it is impossible to detect until run-time. The dsPIC30F ensures that the data write will dominate, resulting in W2 = 0x1234 in the example above.
Page 25 An attempt to use an uninitialized register as an address pointer will reset the device. A word write must be performed to initialize a W register. A byte write will not affect the initialization detection logic. © 2004 Microchip Technology Inc. DS70049C-page 2-7...
Page 26: Software Stack Pointer
W15 is initialized to 0x0800 during all Resets. This address ensures that the stack pointer (SP) will point to valid RAM in all dsPIC30F devices and permits stack availability for non-maskable trap exceptions, which may occur before the SP is initialized by the user software. The user may reprogram the SP during initialization to any location within data space.
Page 27 W15 = 0x0802 W0 = 0x5A5A W1 = 0x3636 Figure 2-6: Stack Pointer After the Second PUSH Instruction 0x0000 PUSH 0x5A5A 0x0800 0x0802 0x3636 0x0804 0xFFFE W15 = 0x0804 W0 = 0x5A5A W1 = 0x3636 © 2004 Microchip Technology Inc. DS70049C-page 2-9...
Page 28 ULNK (unlink) instructions. W14 can be used in a normal working register by instructions when it is not used as a frame pointer. Refer to the “dsPIC30F Programmer’s Reference Manual” (DS70030) for software examples that use W14 as a stack frame pointer.
Page 29: Cpu Register Descriptions
2.4.1 SR: CPU Status Register The dsPIC30F CPU has a 16-bit status register (SR), the LSByte of which is referred to as the lower status register (SRL). The upper byte of SR is referred to as SRH. A detailed description of SR is shown in Register 2-1.
Page 30 Family Reference Manual Register 2-1: SR: CPU Status Register Upper Byte: R/C-0 R/C-0 R/C-0 R -0 R/W-0 bit 15 bit 8 Lower Byte: (SRL) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL<2:0> bit 7 bit 0 bit 15 OA: Accumulator A Overflow Status bit...
Page 31 U = Unimplemented bit, read as ‘0’ C = Clear only bit S = Set only bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70049C-page 2-13...
Page 32 Family Reference Manual Register 2-2: CORCON: Core Control Register Upper Byte: R/W-0 R/W-0 — — — DL<2:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-1 R/W-0 R/C-0 R/W-0 R/W-0 R/W-0 SATA SATB SATDW ACCSAT IPL3 bit 7 bit 0 bit 15-13 Unimplemented: Read as '0’...
Page 33 U = Unimplemented bit, read as ‘0’ C = Bit can be cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70049C-page 2-15...
Page 34 Family Reference Manual 2.4.3 Other dsPIC30F CPU Control Registers The registers listed below are associated with the dsPIC30F CPU core, but are described in further detail in other sections of this manual. 2.4.3.1 TBLPAG: Table Page Register The TBLPAG register is used to hold the upper 8 bits of a program memory address during table read and write operations.
Page 35: Arithmetic Logic Unit (Alu)
Section 2. CPU Arithmetic Logic Unit (ALU) The dsPIC30F ALU is 16-bits wide and is capable of addition, subtraction, single bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) status bits in the SR register.
Page 36: Dsp Engine
X memory data bus is used for data reads and writes in these operations. A block diagram of the DSP engine is shown in Figure 2-8. Note: For detailed code examples and instruction syntax related to this section, refer to the dsPIC30F Programmer’s Reference Manual (DS70030). DS70049C-page 2-18 © 2004 Microchip Technology Inc.
Page 37 Section 2. CPU Figure 2-8: DSP Engine Block Diagram 40-bit Accumulator A 40-bit Accumulator B Saturate Adder Negate Barrel Shifter Sign-Extend Zero Backfill 17-bit x 17-bit Multiplier/Scaler 16-bit to 17-bit Conversion To/From W Array © 2004 Microchip Technology Inc. DS70049C-page 2-19...
Page 38 2.6.2 Multiplier The dsPIC30F features a 17-bit x 17-bit multiplier which is shared by both the MCU ALU and the DSP engine. The multiplier is capable of signed or unsigned operation and can support either 1.31 fractional (Q.31) or 32-bit integer results.
Page 39 ..0xC002 = -2 = -32768 + 16384 + 2 = -16382 1.15 Fractional: . . . Implied Radix Point 0xC002 = -2 = -1 + 0.5 + 0.000061035 = -0.499938965 © 2004 Microchip Technology Inc. DS70049C-page 2-21...
Page 40 Family Reference Manual Table 2-2: dsPIC30F Data Ranges Register Fraction Integer Range Fraction Range Size Resolution 16-bit -32768 to -1.0 to (1.0 – 2 3.052 x 10 32767 (Q.15 Format) 32-bit -2,147,483,648 to -1.0 to (1.0 – 2 4.657 x 10 2,147,483,647 (Q.31 Format)
Page 41 Note: The user must remember that SA, SB and SAB status bits can have different meanings depending on whether accumulator saturation is enabled. The Accumulator Saturation mode is controlled via the CORCON register. © 2004 Microchip Technology Inc. DS70049C-page 2-23...
Page 42 Family Reference Manual 2.6.3.2 Saturation and Overflow Modes The device supports three Saturation and Overflow modes. Accumulator 39-bit Saturation: In this mode, the saturation logic loads the maximally positive 9.31 value (0x7FFFFFFFFF), or maximally negative 9.31 value (0x8000000000), into the target accumulator.
Page 43 1000 0000 0000 0000 0XXX XXXX XXXX XXXX Round Down (add nothing) when: Round Down (add nothing) when: 1. LSWord = 0x8000 and bit 16 = 0 LSWord < 0x8000 2. LSWord < 0x8000 © 2004 Microchip Technology Inc. DS70049C-page 2-25...
Page 44 Family Reference Manual 2.6.5 Barrel Shifter The barrel shifter is capable of performing up to a 16-bit arithmetic right shift, or up to a 16-bit left shift, in a single cycle. The barrel shifter can be used by DSP instructions or MCU instructions for multi-bit shifts.
Page 45: Divide Support
Instruction Flow Types Most instructions in the dsPIC30F architecture occupy a single word of program memory and execute in a single cycle. An instruction pre-fetch mechanism facilitates single cycle (1 T execution. However, some instructions take 2 or 3 instruction cycles to execute. Consequently, ®...
Page 46 Family Reference Manual 1 Instruction Word, 2 or 3 Instruction Cycle Program Flow Changes: These instructions include relative call and branch instructions, and skip instructions. When an instruction changes the PC (other than to increment it), the program memory pre-fetch data must be discarded.
Page 47 Instruction Pipeline Flow – 1-Word, 1-Cycle (With Instruction Stall) Fetch 1 Execute 1 1. MOV W0,W1 Fetch 2 Execute 1 2. MOV [W1],[W4] Stall Execute 2 Fetch 3 Execute 3 3. MOV W2,W1 © 2004 Microchip Technology Inc. DS70049C-page 2-29...
Page 48: Loop Constructs
Family Reference Manual Loop Constructs The dsPIC30F supports both REPEAT and DO instruction constructs to provide unconditional automatic program loop control. The REPEAT instruction is used to implement a single instruction program loop. The DO instruction is used to implement a multiple instruction program loop. Both instructions use control bits within the CPU Status register, SR, to temporarily modify CPU operation.
Page 49 Another REPEAT or DO instruction. DISI, ULNK, LNK, PWRSAV, RESET. MOV.D instruction. Note: There are some instructions and/or Instruction Addressing modes that can be executed within a Repeat loop, but make little sense when repeated. © 2004 Microchip Technology Inc. DS70049C-page 2-31...
Page 50 ‘do-while’ construct in the C programming language because the instructions in the loop will always be executed at least once. The dsPIC30F has three registers associated with DO loops: DOSTART, DOEND and DCOUNT. These registers are memory mapped and automatically loaded by the hardware when the DO instruction is executed.
Page 51 This is not a recommended method for terminating a DO loop. Note: Exiting a DO loop without using EDT is not recommended because the hardware will continue to check for DOEND addresses. © 2004 Microchip Technology Inc. DS70049C-page 2-33...
Page 52 Family Reference Manual 2.9.2.5 DO Loop Restrictions DO loops have the following restrictions imposed: • choice of last instruction in the loop • the loop length (offset from the first instruction) • reading of the DOEND register All DO loops must contain at least 2 instructions because the loop termination tests are performed in the penultimate instruction.
Page 53: Address Register Dependencies
2.10 Address Register Dependencies The dsPIC30F architecture supports a data space read (source) and a data space write (destination) for most MCU class instructions. The effective address (EA) calculation by the AGU and subsequent data space read or write, each take a period of 1 instruction cycle to complete.
Page 54 If the source read (pre-fetched instruction) does not calculate an EA using Wn, no stalls will occur. During each instruction cycle, the dsPIC30F hardware automatically checks to see if a RAW data dependency is about to occur. If the conditions specified above are not satisfied, the CPU will automatically add a one instruction cycle delay before executing the pre-fetched instruction.
Page 55 Section 2. CPU If a RAW data dependency is detected, the dsPIC30F will begin an instruction stall. During an instruction stall, the following events occur: The write operation underway (for the previous instruction) is allowed to complete as normal. Data space is not addressed until after the instruction stall.
Page 56 Family Reference Manual DS70049C-page 2-38 © 2004 Microchip Technology Inc.
Page 57 Section 2. CPU © 2004 Microchip Technology Inc. DS70049C-page 2-39...
Page 58: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 59: Revision History
Revision A This is the initial released revision of this document. Revision B This revision incorporates additional technical content for the dsPIC30F CPU module. Revision C This revision incorporates all known errata at the time of this document update. © 2004 Microchip Technology Inc.
Page 60 Family Reference Manual NOTES: DS70049C-page 2-42 © 2004 Microchip Technology Inc.
Page 61 This section of the manual contains the following topics: Introduction ........................3-2 Data Space Address Generator Units (AGUs) ............... 3-5 Modulo Addressing ......................3-7 Bit-Reversed Addressing ..................... 3-14 Control Register Descriptions ..................3-18 Related Application Notes.................... 3-23 Revision History ......................3-24 © 2004 Microchip Technology Inc. DS70050C-page 3-1...
Page 62: Introduction
Family Reference Manual Introduction The dsPIC30F data width is 16-bits. All internal registers and data space memory are organized as 16-bits wide. The dsPIC30F features two data spaces. The data spaces can be accessed separately (for some DSP instructions) or together as one 64-Kbyte linear address range (for MCU instructions).
Page 63: Section 3. Data Memory
3: All data memory can be accessed indirectly via W registers or directly using the MOV instruction. 4: Upper half of data memory map can be mapped into a segment of program memory space for program space visibility. © 2004 Microchip Technology Inc. DS70050C-page 3-3...
Page 64 The memory regions included in the near data region will depend on the amount of data memory implemented for each dsPIC30F device variant. At a minimum, the near data region will include all of the SFRs and some of the X data memory. For devices that have smaller amounts of data memory, the near data region may include all of X memory space and possibly some or all of Y memory space.
Page 65: Data Space Address Generator Units (Agus)
Section 3. Data Memory Data Space Address Generator Units (AGUs) The dsPIC30F contains an X AGU and a Y AGU for generating data memory addresses. Both X and Y AGUs can generate any effective address (EA) within a 64-Kbyte range. However, EAs that are outside the physical memory provided will return all zeros for data reads and data writes to those locations will have no effect.
Page 66 The Y AGU only supports Post-modification Addressing modes associated with the DSP class of instructions. For more information on Addressing modes, please refer to the dsPIC30F Program- mer’s Reference Manual. The Y AGU also supports modulo addressing for automated circular buffers.
Page 67: Modulo Addressing
(since the data pointer mechanism is essentially the same for both). One circular buffer can be supported in each of the X (which also provides the pointers into Program space) and Y data spaces.
Page 68 Family Reference Manual 3.3.1 Modulo Start and End Address Selection Four address registers are available for specifying the modulo buffer start and end addresses: • XMODSRT: X AGU Modulo Start Address Register • XMODEND: X AGU Modulo End Address Register •...
Page 69 NOP after initializing MODCON, as shown in Example 3-2. Example 3-2: Correct MODCON Initialization #0x8FF4, w0 ;Initialize MODCON w0, MODCON ;See Note below [w1], w2 ;Correct EA generated here © 2004 Microchip Technology Inc. DS70050C-page 3-9...
Page 70 Family Reference Manual An additional condition exists for indirect read operations performed immediately after writing to the modulo address SFRs: • XMODSRT • XMODEND • YMODSRT • YMODEND If modulo addressing has already been enabled in MODCON, then a write to the X (or Y) modulo address SFRs should not be immediately followed by an indirect read, using the W register designated for modulo buffer access from X-data space (or Y-data space).
Page 71 Register Indexed and Literal Offset Addressing modes do not change the value held in the W register. Only the indirect with Pre- and Post-modification Addressing modes ([Wn++], [Wn--], [++Wn], [--Wn]) will modify the W register address value. © 2004 Microchip Technology Inc. DS70050C-page 3-11...
Page 72 Family Reference Manual 3.3.4 Modulo Addressing Initialization for Incrementing Modulo Buffer The following steps describe the setup procedure for an incrementing circular buffer. The steps are similar whether the X AGU or Y AGU is used. Determine the buffer length in 16-bit data words. Multiply this value by 2 to get the length of the buffer in bytes.
Page 73 ;fill the 16 buffer locations W0,[W1--] ;fill the next location FILL: W0,W0 ;decrement the fill value 0x11FF ; W1 = 0x11FE when DO loop completes Start Addr = 0x11E0 End Addr = 0x11FF Length = 16 Words © 2004 Microchip Technology Inc. DS70050C-page 3-13...
Page 74: Bit-Reversed Addressing
Family Reference Manual Bit-Reversed Addressing 3.4.1 Introduction to Bit-Reversed Addressing Bit-reversed addressing simplifies data re-ordering for radix-2 FFT algorithms. It is supported through the X WAGU only. Bit-reversed addressing is accomplished by effectively creating a ‘mirror image’ of an address pointer by swapping the bit locations around the center point of the binary value, as shown in Figure 3-7.
Page 75 If bit-reversed addressing has already been enabled by setting the BREN (XBREV<15>) bit, then a write to the XBREV register should not be followed by an indirect read operation using the W register, designated as the bit reversed address pointer. © 2004 Microchip Technology Inc. DS70050C-page 3-15...
Page 76 Family Reference Manual 3.4.3 Bit-Reverse Modifier Value The value loaded into the XBREV register is a constant that indirectly defines the size of the bit-reversed data buffer. The XB modifier values used with common bit-reversed buffers are summarized in Table 3-2.
Page 77 Figure 3-8: Bit-Reversed Address Modification for 16-Word Buffer 14 13 12 11 XB<14:0> = 0x0008 Bits 1-4 of address are modified. 14 13 12 11 Bit-Reversed Result Pivot Point © 2004 Microchip Technology Inc. DS70050C-page 3-17...
Page 78: Control Register Descriptions
Family Reference Manual 3.4.4 Bit-Reversed Addressing Code Example The following code example reads a series of 16 data words and writes the data to a new location in bit-reversed order. W0 is the read address pointer and W1 is the write address pointer subject to bit-reverse modification.
Page 79 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70050C-page 3-19...
Page 80 Family Reference Manual Register 3-2: XMODSRT: X AGU Modulo Addressing Start Register Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 XS<15:8> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 XS<7:1> bit 7...
Page 81 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70050C-page 3-21...
Page 82 Family Reference Manual Register 3-6: XBREV: X Write AGU Bit-Reversal Addressing Control Register Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BREN XB<14:8> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 XB<7:0>...
Page 83: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 84: Revision History
Revision A This is the initial released revision of this document. Revision B This revision incorporates additional technical content for the dsPIC30F Data Memory module. Revision C This revision incorporates all known errata at the time of this document update.
Page 85: Section 4. Program Memory
Program Memory Address Map ..................4-2 Program Counter ......................4-4 Data Access from Program Memory ................4-4 Program Space Visibility from Data Space..............4-8 Program Memory Writes ....................4-10 Related Application Notes.................... 4-11 Revision History ......................4-12 © 2004 Microchip Technology Inc. DS70051C-page 4-1...
Page 86: Program Memory Address Map
Family Reference Manual Program Memory Address Map The dsPIC30F devices have a 4M x 24-bit program memory address space, shown in Figure 4-1. There are three available methods for accessing program space. Via the 23-bit PC. Via table read (TBLRD) and table write (TBLWT) instructions.
Page 87 DEVID (2) FFFFFE Note: The address boundaries for user Flash program memory and data EEPROM memory will depend on the dsPIC30F device variant that is selected. Refer to the appropriate device data sheet for further details. © 2004 Microchip Technology Inc.
Page 88: Program Counter
Family Reference Manual Program Counter The PC increments by 2 with the LSb set to ‘0’ to provide compatibility with data space addressing. Sequential instruction words are addressed in the 4M program memory space by PC<22:1>. Each instruction word is 24-bits wide.
Page 89 High and Low Address Regions for Table Operations PC Address 0x000100 00000000 0x000102 00000000 00000000 0x000104 00000000 0x000106 ‘HIGH’ Table Address Range ‘LOW’ Table Address Range Program Memory ‘Phantom’ Byte (Read as ‘0’) © 2004 Microchip Technology Inc. DS70051C-page 4-5...
Page 90 Family Reference Manual 4.3.2 Table Address Generation For all table instructions, a W register address value is concatenated with the 8-bit Data Table Page register, TBLPAG, to form a 23-bit effective program space address plus a byte select bit, as shown in Figure 4-4.
Page 91 NOP, or as an illegal opcode value, to protect the device from accidental execution of stored data. The TBLRDH and TBLWTH instructions are primarily provided for array program/verification purposes and for those applications that require compressed data storage. © 2004 Microchip Technology Inc. DS70051C-page 4-7...
Page 92: Program Space Visibility From Data Space
PSV Mapping with X and Y Data Spaces The Y data space is located outside of the upper half of data space for most dsPIC30F variants, such that the PSV area will map into X data space. The X and Y mapping will have an effect on how PSV is used in algorithms.
Page 93 Memory Data cannot be read using Program Space Visibility. Data Read Figure 4-8: Program Space Visibility Address Generation 23 bits Select PSVPAG Reg 8 bits 15 bits Wn<0> is Byte Select 23-bit EA © 2004 Microchip Technology Inc. DS70051C-page 4-9...
Page 94: Program Memory Writes
Refer to Section 2. “CPU” for more information about instruction stalls using PSV. Program Memory Writes The dsPIC30F family of devices contains internal program Flash memory for executing user code. There are two methods by which the user can program this memory: Run-Time Self Programming (RTSP) In-Circuit Serial Programming™...
Page 95: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 96: Revision History
Family Reference Manual Revision History Revision A This is the initial released revision of this document. Revision B There were no technical content or editorial revisions to this section of the manual, however, this section was updated to reflect Revision B throughout the manual.
Page 97 Introduction ........................5-2 Table Instruction Operation .................... 5-2 Control Registers ......................5-5 Run-Time Self-Programming (RTSP) ................5-9 Data EEPROM Programming ..................5-14 Design Tips ........................5-20 Related Application Notes.................... 5-21 Revision History ......................5-22 © 2004 Microchip Technology Inc. DS70052C-page 5-1...
Page 98: Introduction
The table instructions provide one method of transferring data between the program memory space and the data memory space of dsPIC30F devices. A summary of the table instructions is provided here since they are used during programming of the Flash program memory and data EEPROM.
Page 99: Section 5. Flash And Eeprom Programming
Note: The tblpage() and tbloffset() directives are provided by the Microchip assembler for the dsPIC30F. These directives select the appropriate TBLPAG and W register values for the table instruction from a program memory address value. Refer to the Microchip software tools documentation for further details.
Page 100 Family Reference Manual 5.2.2 Using Table Write Instructions The effect of a table write instruction will depend on the type of memory technology that is present in the device program memory address space. The program memory address space could contain volatile or non-volatile program memory, non-volatile data memory, and an External Bus Interface (EBI).
Page 101: Control Registers
1 data word 0x4004 Program 16 data words 0x4005 Configuration Register 1 config. register 0x4008 Write Note 1: The Device Configuration registers may be written to a new value without performing an erase cycle. © 2004 Microchip Technology Inc. DS70052C-page 5-5...
Page 102 Family Reference Manual 5.3.2 NVM Address Register There are two NVM Address Registers - NVMADRU and NVMADR. These two registers when concatenated form the 24-bit effective address (EA) of the selected row or word for programming operations. The NVMADRU register is used to hold the upper 8 bits of the EA, while the NVMADR register is used to hold the lower 16 bits of the EA.
Page 103 W = Writable bit U = Unimplemented bit, read as ‘0’ S = Settable bit -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70052C-page 5-7...
Page 104 Family Reference Manual Register 5-2: NVMADR: Non-Volatile Memory Address Register Upper Byte: R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<15:8> bit 15 bit 8 Lower Byte: R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x NVMADR<7:0> bit 7 bit 0 bit 15-0 NVMADR<15:0>: NV Memory Write Address bits...
Page 105: Run-Time Self-Programming (Rtsp)
The dsPIC30F Flash program memory is organized into rows and panels. Each row consists of 32 instructions or 96 bytes. The panel size may vary depending on the dsPIC30F device variant. Refer to the device data sheet for further information. Typically, each panel consists of 128 rows, or 4K x 24 instructions.
Page 106 Family Reference Manual 5.4.2.1 Flash Program Memory Programming Algorithm The user can erase and program Flash Program Memory by rows (32 instruction words). The general process is as follows: Read one row of program Flash (32 instruction words) and store into data RAM as a data “image”.
Page 107 NVMADRU and NVMADR registers. The above code example could be modified to perform a ‘dummy’ table write operation to capture the program memory erase address. © 2004 Microchip Technology Inc. DS70052C-page 5-11...
Page 108 Family Reference Manual 5.4.2.3 Loading Write Latches The following is a sequence of instructions that can be used to load the 768-bits of write latches (32 instruction words). 32 TBLWTL and 32 TBLWTH instructions are needed to load the write latches selected by the table pointer.
Page 109 Configure NVMCON for a Configuration register write (NVMCON = 0x4008). Disable interrupts, if enabled. Write the key sequence to NVMKEY. Start the write sequence by setting WR (NVMCON<15>). CPU execution will resume when the write is finished. Re-enable interrupts, if needed. © 2004 Microchip Technology Inc. DS70052C-page 5-13...
Page 110: Data Eeprom Programming
Family Reference Manual 5.4.3.2 Configuration Register Write Code Example The following code sequence can be used to modify a Device Configuration register: ; Set up a pointer to the location to be written. #tblpage(CONFIG_ADDR),W0 TBLPAG #tbloffset(CONFIG_ADDR),W0 ; Get the new data to write to the configuration register #ConfigValue,W1 ;...
Page 111 • Clear NVMIF status bit and enable NVM interrupt (optional). • Write the key sequence to NVMKEY. • Set the WR bit. This will begin the program cycle. • Either poll the WR bit or wait for the NVM interrupt. © 2004 Microchip Technology Inc. DS70052C-page 5-15...
Page 112 Family Reference Manual 5.5.3 Erasing One Word of Data EEPROM Memory The TBLPAG and NVMADR registers must be loaded with the data EEPROM address to be erased. Since one word of the EEPROM is accessed, the LSB of the NVMADR has no effect on the erase operation.
Page 113 #0x4004,W0 NVMCON ; Disable interrupts while the KEY sequence is written PUSH #0x00E0,W0 ; Write the key sequence #0x55,W0 W0,NVMKEY #0xAA,W0 W0,NVMKEY ; Start the write cycle BSET NVMCON,#WR ;Re-enable interrupts, if needed © 2004 Microchip Technology Inc. DS70052C-page 5-17...
Page 114 Family Reference Manual 5.5.5 Erasing One Row of Data EEPROM The NVMCON register is configured to erase one row of EEPROM memory. The TABPAG and NVMADR registers must point to the row to be erased. The data EEPROM must be erased at even address boundaries.
Page 115 Sixteen table write instructions have been used in this code segment to provide clarity in the example. The code segment could be simplified by using a single table write instruction in a REPEAT loop. © 2004 Microchip Technology Inc. DS70052C-page 5-19...
Page 116: Design Tips
Family Reference Manual 5.5.7 Reading the Data EEPROM Memory A TBLRD instruction reads a word at the current program word address. This example uses W0 as a pointer to data Flash. The result is placed into register W4. ; Setup pointer to EEPROM memory...
Page 117: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 118: Revision History
Revision A This is the initial released revision of this document. Revision B This revision incorporates technical content changes for the dsPIC30F Flash and EEPROM Programming module. Revision C This revision incorporates all known errata at the time of this document update.
Page 119: Section 6. Reset Interrupts
Introduction ........................6-2 Non-Maskable Traps...................... 6-6 Interrupt Processing Timing ..................6-11 Interrupt Control and Status Registers................. 6-14 Interrupt Setup Procedures..................6-42 Design Tips ........................6-44 Related Application Notes.................... 6-45 Revision History ......................6-46 © 2004 Microchip Technology Inc. DS70053C-page 6-1...
Page 120: Introduction
A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The dsPIC30F device clears its registers in response to a Reset which forces the PC to zero. The processor then begins program execution at location 0x000000. The user programs a GOTO instruction at the Reset address which redirects program execution to the appropriate start-up routine.
Page 121 AIVT Address Trap Source Number Reserved 0x000004 0x000084 Oscillator Failure 0x000006 0x000086 Address Error 0x000008 0x000088 Stack Error 0x00000A 0x00008A Arithmetic Error 0x00000C 0x00008C Reserved 0x00000E 0x00008E Reserved 0x000010 0x000090 Reserved 0x000012 0x000092 © 2004 Microchip Technology Inc. DS70053C-page 6-3...
Page 122 Family Reference Manual Table 6-2: Interrupt Vector Details Vector IVT Address AIVT Address Interrupt Source Number INT0 – External Interrupt 0 0x000014 0x000094 IC1 – Input Compare 1 0x000016 0x000096 OC1 – Output Compare 1 0x000018 0x000098 T1 – Timer 1...
Page 123 Note: The peripherals and sources of interrupt available in the IVT will vary depending on the specific dsPIC30F device. The sources of interrupt shown in this document represent a comprehensive listing of all interrupt sources found on dsPIC30F devices. Refer to the specific device data sheet for further details.
Page 124: Non-Maskable Traps
Otherwise, the trap vector is programmed with the address of a service routine that will correct the trap condition. The dsPIC30F has four implemented sources of non-maskable traps: • Oscillator Failure Trap • Stack Error Trap •...
Page 125 Acknowledged until processing for the higher priority trap completes. The device is automatically reset in a hard trap conflict condition. The TRAPR status bit (RCON<15> ) is set when the Reset occurs, so that the condition may be detected in software. © 2004 Microchip Technology Inc. DS70053C-page 6-7...
Page 126 A misaligned data word fetch is attempted. This condition occurs when an instruction performs a word access with the LSb of the effective address set to ‘1’. The dsPIC30F CPU requires all word accesses to be aligned to an even address boundary.
Page 127 The RETFIE (Return from Interrupt) instruction will unstack the PC return address, IPL3 status bit, and SRL register to return the processor to the state and priority level prior to the interrupt sequence. © 2004 Microchip Technology Inc. DS70053C-page 6-9...
Page 128 IEC Control registers, a wake-up signal is sent to the dsPIC30F CPU. When the device wakes from Sleep or Idle mode, one of two actions may occur: If the interrupt priority level for that source is greater than the current CPU priority level, then the processor will process the interrupt and branch to the ISR for the interrupt source.
Page 129: Interrupt Processing Timing
PUSH SRL and High 8 bits of PC temporary (from temporary buffer). buffer. PUSH Low 16 bits of PC (from temporary buffer). Peripheral interrupt event occurs at or before midpoint of this cycle. © 2004 Microchip Technology Inc. DS70053C-page 6-11...
Page 130 Family Reference Manual 6.3.2 Interrupt Latency for Two-Cycle Instructions The interrupt latency during a two-cycle instruction is the same as during a one-cycle instruction. The first and second cycle of the interrupt process allow the two-cycle instruction to complete execution.
Page 131 6.3.4 Special Conditions for Interrupt Latency The dsPIC30F allows the current instruction to complete when a peripheral interrupt source becomes pending. The interrupt latency is the same for both one and two-cycle instructions. However, there are certain conditions that can increase interrupt latency by one cycle, depending on when the interrupt occurs.
Page 132: Interrupt Control And Status Registers
Family Reference Manual Interrupt Control and Status Registers The following registers are associated with the interrupt controller: • INTCON1, INTCON2 Registers Global interrupt control functions are derived from these two registers. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources.
Page 133 U = Unimplemented bit, read as ‘0’ C = Bit can be cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-15...
Page 134 Family Reference Manual Register 6-3: INTCON1: Interrupt Control Register 1 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 NSTDIS — — — — OVATE OVBTE COVTE bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 — — — MATHERR ADDRERR...
Page 135 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-17...
Page 136 Family Reference Manual Register 6-5: IFS0: Interrupt Flag Status Register 0 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNIF MI2CIF SI2CIF NVMIF ADIF U1TXIF U1RXIF SPI1IF bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0...
Page 137 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-19...
Page 138 Family Reference Manual Register 6-6: IFS1: Interrupt Flag Status Register 1 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC6IF IC5IF IC4IF IC3IF C1IF SPI2IF U2TXIF U2RXIF bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0...
Page 139 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-21...
Page 140 Family Reference Manual Register 6-7: IFS2: Interrupt Flag Status Register 2 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FLTBIF FLTAIF LVDIF DCIIF QEIIF bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...
Page 141 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-23...
Page 142 Family Reference Manual Register 6-8: IEC0: Interrupt Enable Control Register 0 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNIE MI2CIE SI2CIE NVMIE ADIE U1TXIE U1RXIE SPI1IE bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0...
Page 143 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-25...
Page 144 Family Reference Manual Register 6-9: IEC1: Interrupt Enable Control Register 1 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IC6IE IC5IE IC4IE IC3IE C1IE SPI2IE U2TXIE U2RXIE bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0...
Page 145 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-27...
Page 146 Family Reference Manual Register 6-10: IEC2: Interrupt Enable Control Register 2 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — FLTBIE FLTAIE LVDIE DCIIE QEIIE bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...
Page 147 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-29...
Page 148 Family Reference Manual Register 6-11: IPC0: Interrupt Priority Control Register 0 Upper Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — T1IP<2:0> — OC1IP<2:0> bit 15 bit 8 Lower Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — IC1IP<2:0> — INT0IP<2:0>...
Page 149 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-31...
Page 150 Family Reference Manual Register 6-13: IPC2: Interrupt Priority Control Register 2 Upper Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — ADIP<2:0> — U1TXIP<2:0> bit 15 bit 8 Lower Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — U1RXIP<2:0> — SPI1IP<2:0>...
Page 151 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-33...
Page 152 Family Reference Manual Register 6-15: IPC4: Interrupt Priority Control Register 4 Upper Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — OC3IP<2:0> — IC8IP<2:0> bit 15 bit 8 Lower Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — IC7IP<2:0> — INT1IP<2:0>...
Page 153 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-35...
Page 154 Family Reference Manual Register 6-17: IPC6: Interrupt Priority Control Register 6 Upper Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — C1IP<2:0> — SPI2IP<2:0> bit 15 bit 8 Lower Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — U2TXIP<2:0> — U2RXIP<2:0>...
Page 155 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-37...
Page 156 Family Reference Manual Register 6-19: IPC8: Interrupt Priority Control Register 8 Upper Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — OC8IP<2:0> — OC7IP<2:0> bit 15 bit 8 Lower Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — OC6IP<2:0> — OC5IP<2:0>...
Page 157 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-39...
Page 158 Family Reference Manual Register 6-21: IPC10: Interrupt Priority Control Register 10 Upper Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — FLTAIP<2:0> — LVDIP<2:0> bit 15 bit 8 Lower Byte: R/W-1 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 — DCIIP<2:0> — QEIIP<2:0>...
Page 159 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70053C-page 6-41...
Page 160: Interrupt Setup Procedures
Family Reference Manual Interrupt Setup Procedures 6.5.1 Initialization The following steps describe how to configure a source of interrupt: Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. Select the user assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx Control register.
Page 161 Section 6. Interrupts © 2004 Microchip Technology Inc. DS70053C-page 6-43...
Page 162: Design Tips
Family Reference Manual Design Tips Question 1: What happens when two sources of interrupt become pending at the same time and have the same user assigned priority level? Answer: The interrupt source with the highest natural order priority will take precedence. The natural order priority is determined by the Interrupt Vector Table (IVT) address for that source.
Page 163: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 164: Revision History
Revision A This is the initial released revision of this document. Revision B This revision incorporates additional technical content for the dsPIC30F Interrupts module. Revision C This revision incorporates all known errata at the time of this document update. DS70053C-page 6-46...
Page 165 7.14 Internal Low Power RC (LPRC) Oscillator ..............7-20 7.15 Fail-Safe Clock Monitor (FSCM) .................. 7-20 7.16 Programmable Oscillator Postscaler................7-21 7.17 Clock Switching Operation................... 7-22 7.18 Design Tips ........................7-26 7.19 Related Application Notes.................... 7-27 7.20 Revision History ......................7-28 © 2004 Microchip Technology Inc. DS70054C-page 7-1...
Page 166: Introduction
Family Reference Manual Introduction This section describes the dsPIC30F oscillator system and its operation. The dsPIC30F oscillator system has the following modules and features: • Various external and internal oscillator options as clock sources • An on-chip PLL to boost internal operating frequency •...
Page 167: Section 7. Oscillator
, is divided by 4 to get the instruction cycle clock. 2: Some devices allow the internal FRC oscillator to be connected to the PLL. See the specific device data sheet for further details. © 2004 Microchip Technology Inc. DS70054C-page 7-3...
Page 168: Cpu Clocking Scheme
Family Reference Manual CPU Clocking Scheme Referring to Figure 7-1, the system clock source can be provided by one of four sources. These sources are the Primary oscillator, Secondary oscillator, Internal Fast RC (FRC) oscillator or the Low Power RC (LPRC) oscillator. The Primary oscillator source has the option of using the internal PLL.
Page 169: Oscillator Configuration
Some dsPIC devices have additional oscillator configuration bits that allow FRC + PLL, HS/2 + PLL and HS/3 + PLL oscillator configurations. These selections provide a greater variety of clock choices for the PLL. Please refer to the specific device data sheet for available oscillator configurations. © 2004 Microchip Technology Inc. DS70054C-page 7-5...
Page 170: Oscillator Control Register (Osccon)
Family Reference Manual 7.3.1 Clock Switching Mode Configuration Bits The FCKSM<1:0> configuration bits (F <15:14>) are used to enable/disable device clock switching and the Fail-Safe Clock Monitor (FSCM). When these bits are unprogrammed (default), clock switching and the FSCM are disabled.
Page 171: 11 = Primary Oscillator
Unimplemented: Read as ‘0’ bit 3 CF: Clock Fail Status bit 1 = FSCM has detected a clock failure 0 = FSCM has not detected a clock failure bit 2 Unimplemented: Read as ‘0’ © 2004 Microchip Technology Inc. DS70054C-page 7-7...
Page 172 Family Reference Manual Register 7-1: OSCCON: Oscillator Control Register (Continued) bit 1 LPOSCEN: 32 kHz LP Oscillator Enable bit 1 = LP oscillator is enabled 0 = LP oscillator is disabled bit 0 OSWEN: Oscillator Switch Enable bit 1 = Request oscillator switch to selection specified by NOSC<1:0> bits...
Page 173: Primary Oscillator
Section 7. Oscillator Primary Oscillator The Primary oscillator is available on the OSC1 and OSC2 pins of the dsPIC30F device family. The Primary oscillator has 13 Operation modes summarized in Table 7-2. In general, the Primary oscil- lator can be configured for an external clock input, external RC network, or an external crystal.
Page 174: Crystal Oscillators/Ceramic Resonators
In XT, XTL and HS modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation (Figure 7-3). The dsPIC30F oscillator design requires the use of a parallel cut crystal. Using a series cut crystal may give a frequency out of the crystal manufacturer’s specifications.
Page 175 • operating in a shielded box (away from the noisy RF area) • low voltage • high temperature • wake-up from Sleep mode Noise actually helps lower the oscillator start-up time since it provides a “kick start” to the oscillator. © 2004 Microchip Technology Inc. DS70054C-page 7-11...
Page 176: Determining Best Values For Crystals, Clock Mode, C1, C2 And Rs
The dsPIC30F internal oscillator circuit is a parallel oscillator circuit, which requires that a parallel resonant crystal be selected. The load capacitance is usually specified in the 22 pF to 33 pF range.
Page 177: External Clock Input
OSC1 pin is hi-impedance and the OSC2 pin becomes a general purpose I/O pin. The feedback device between OSC1 and OSC2 is turned off to save current. Figure 7-6: External Clock Input Operation (ECIO Oscillator Configuration) OSC1 Clock from Ext. System dsPIC30F I/O (OSC2) © 2004 Microchip Technology Inc. DS70054C-page 7-13...
Page 178: External Rc Oscillator
Family Reference Manual External RC Oscillator For timing insensitive applications, the ERC and ERCIO modes of the Primary oscillator offer additional cost savings. The RC oscillator frequency is a function of the: • Supply voltage • External resistor (R ) values •...
Page 179 The following graphs should be used only as approximate guidelines for RC component selection. The actual frequency will vary based on the system temperature and device. Please refer to the specific device data sheet for further RC oscillator characteristic data. © 2004 Microchip Technology Inc. DS70054C-page 7-15...
Page 180 Family Reference Manual Figure 7-9: Typical External RC Oscillator Frequency vs = 20 pF Operation above 4 MHz is not recommended. = 10k = 100k Figure 7-10: Typical External RC Oscillator Frequency vs. V = 100 pF Operation above 4 MHz is not recommended.
Page 181 Section 7. Oscillator Figure 7-11: Typical External RC Oscillator Frequency vs. V = 300 pF = 3.3k = 5.1k = 10k = 100k © 2004 Microchip Technology Inc. DS70054C-page 7-17...
Page 182: Phase Locked Loop (Pll)
Table 7-3. Note: Some PLL output frequency ranges can be achieved that exceed the maximum operating frequency of the dsPIC30F device. Refer to the “Electrical Specifications” in the specific device data sheet for further details. Table 7-3: PLL Frequency Range...
Page 183: Low Power 32 Khz Crystal Oscillator
The FRC oscillator is a fast (8 MHz nominal) internal RC oscillator. This oscillator is intended to provide reasonable device operating speeds without the use of an external crystal, ceramic resonator or RC network. The dsPIC30F operates from the FRC oscillator whenever COSC<1:0> = 01. © 2004 Microchip Technology Inc. DS70054C-page 7-19...
Page 184: Internal Low Power Rc (Lprc) Oscillator
Family Reference Manual 7.14 Internal Low Power RC (LPRC) Oscillator The LPRC oscillator is a component of the Watchdog Timer (WDT) and oscillates at a nominal frequency of 512 kHz. The LPRC oscillator is the clock source for the Power-up Timer (PWRT) circuit, WDT and clock monitor circuits.
Page 185: Programmable Oscillator Postscaler
Clock Input (from Clock Switch div. by 4 and Control Logic) Postscaled Counter div. by 16 System Clock div. by 64 POST1 POST0 Note: The system clock input can be any available source © 2004 Microchip Technology Inc. DS70054C-page 7-21...
Page 186: Clock Switching Operation
Family Reference Manual Figure 7-13: Postscaler Update Timing System Clock Divide by 4 Divide by 16 Divide by 64 POST<1:0> Postscaled System Clock 1:16 1:64 Note: This diagram demonstrates the clock postscaler function only. The divide ratios shown in the timing diagram are not correct.
Page 187 1 2 3 4 5 6 7 8 9 10 New Clock Source System Clock OSWEN Both Oscillators Active Note: The system clock can be any selected source – Primary, Secondary, FRC or LPRC. © 2004 Microchip Technology Inc. DS70054C-page 7-23...
Page 188 Family Reference Manual 7.17.3 Clock Switching Tips • If the destination clock source is a crystal oscillator, the clock switch time will be dominated by the oscillator start-up time. • If the new clock source does not start, or is not present, then the clock switching hardware will simply wait for the 10 synchronization cycles to occur.
Page 189 #0x46,W2 ; first unlock code MOV.B #0x57,W3 ; second unlock code MOV.B W2, [W1] ; write first unlock code MOV.B W3, [W1] ; write second unlock code BCLR OSCCON,#OSWEN ; ABORT the switch © 2004 Microchip Technology Inc. DS70054C-page 7-25...
Page 190: Design Tips
Family Reference Manual 7.18 Design Tips Question 1: When looking at the OSC2 pin after power-up with an oscilloscope, there is no clock. What can cause this? Answer: Entering Sleep mode with no source for wake-up (such as, WDT, MCLR, or an interrupt).
Page 191: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 192: Revision History
Revision A This is the initial released revision of this document. Revision B This revision incorporates technical content changes for the dsPIC30F Oscillator module. Revision C This revision incorporates all known errata at the time of this document update. DS70054C-page 7-28...
Page 193: Section 8. Reset
Device Reset Times ..................... 8-11 8.10 Device Start-up Time Lines ..................8-13 8.11 Special Function Register Reset States............... 8-16 8.12 Design Tips ........................8-17 8.13 Related Application Notes.................... 8-18 8.14 Revision History ......................8-19 © 2004 Microchip Technology Inc. DS70055C-page 8-1...
Page 194: Introduction
Family Reference Manual Introduction The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: • POR: Power-on Reset • EXTR: Pin Reset (MCLR) • SWR: RESET Instruction •...
Page 195 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode bit 2 IDLE: Wake-up From Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode © 2004 Microchip Technology Inc. DS70055C-page 8-3...
Page 196 Family Reference Manual Register 8-1: RCON: Reset Control Register (Continued) bit 1 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred. Note that BOR is also set after Power-on Reset. 0 = A Brown-out Reset has not occurred...
Page 197 . The POR delay time is inserted when V crosses the POR circuit threshold voltage. Finally, the PWRT delay time, T PWRT , is inserted before SYSRST is released. The power-on event will set the POR and BOR status bits (RCON<1:0>). © 2004 Microchip Technology Inc. DS70055C-page 8-5...
Page 198 Family Reference Manual Figure 8-2: POR Module Timing Diagram for Rising V POR Circuit Threshold Voltage Time Internal Power-on Reset pulse occurs at V and begins POR delay time, T POR circuit is initialized at V Time System Reset is released after Power-up Timer expires.
Page 199: External Reset (Extr)
Note that a WDT time-out during Sleep or Idle mode will wake-up the processor, but NOT reset the processor. For more information, refer to Section 10. “Watchdog Timer and Power Saving Modes”. © 2004 Microchip Technology Inc. DS70055C-page 8-7...
Page 200: Brown-Out Reset (Bor)
Family Reference Manual Brown-out Reset (BOR) The BOR (Brown-out Reset) module is based on an internal voltage reference circuit. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (i.e., missing waveform portions of the AC cycles due to bad power transmission lines), or voltage sags due to excessive current draw when a large load is energized.
Page 201 A device Reset will occur whenever multiple hard trap sources become pending at the same time. The TRAPR status bit (RCON<15>) will be set. Refer to Section 6. “Reset Interrupts” for more information on Trap Conflict Resets. © 2004 Microchip Technology Inc. DS70055C-page 8-9...
Page 202: Using The Rcon Status Bits
Family Reference Manual Using the RCON Status Bits The user can read the RCON register after any device Reset to determine the cause of the Reset. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful.
Page 203: Device Reset Times
= Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. = PLL lock time (20 µs nominal). 4: T LOCK = Fail-Safe Clock Monitor delay (100 µs nominal). FSCM 5: T © 2004 Microchip Technology Inc. DS70055C-page 8-11...
Page 204 Family Reference Manual 8.9.1 POR and Long Oscillator Start-up Times The oscillator start-up circuitry and its associated delay timers is not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low frequency crystals) will have a relatively long start-up time.
Page 205: Device Start-Up Time Lines
FSCM FSCM Note 1: Delay times shown are not drawn to scale. 2: FSCM, if enabled, monitors system clock at expiration of T FSCM 3: T LOCK not inserted when PLL is disabled. © 2004 Microchip Technology Inc. DS70055C-page 8-13...
Page 206 Family Reference Manual The Reset time line shown in Figure 8-6 is similar to that shown in Figure 8-5, except that the PWRT has been enabled to increase the amount of delay time before SYSRST is released. FSCM The FSCM, if enabled, will begin to monitor the system clock after T expires.
Page 207 Note 1: Delay times shown are not drawn to scale. 2: FSCM, if enabled, monitors system clock at expiration of T PWRT FSCM LOCK 3: T not inserted when PLL is is disabled. © 2004 Microchip Technology Inc. DS70055C-page 8-15...
Page 208: Special Function Register Reset States
8.11 Special Function Register Reset States Most of the special function registers (SFRs) associated with the dsPIC30F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual.
Page 209: Design Tips
Two byte moves to a W register, even if successive, will not work, resulting in a device Reset if the W register is used as an address pointer in an operation. © 2004 Microchip Technology Inc. DS70055C-page 8-17...
Page 210: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 211: Revision History
Revision B throughout the manual. Revision C There were no technical content revisions to this section of the manual, however, this section was updated to reflect Revision C throughout the manual. © 2004 Microchip Technology Inc. DS70055C-page 8-19...
Page 212 Family Reference Manual NOTES: DS70055C-page 8-20 © 2004 Microchip Technology Inc.
Page 213 Section 9. Low Voltage Detect (LVD) HIGHLIGHTS This section of the manual contains the following topics: Introduction ........................9-2 LVD Operation ....................... 9-5 Design Tips ........................9-6 Related Application Notes....................9-7 Revision History ......................9-8 © 2004 Microchip Technology Inc. DS70056C-page 9-1...
Page 214: Introduction
Family Reference Manual Introduction The LVD module is applicable to battery operated applications. As the battery drains its energy, the battery voltage slowly drops. The battery source impedance also increases as it loses energy. The LVD module is used to detect when the battery voltage (and therefore, the V of the device) drops below a threshold, which is considered near the end of battery life for the application.
Page 215: Section 9. Low Voltage Detect (Lvd)
Section 9.2 “LVD Operation”. The bandgap voltage reference circuit can also be used by other peripherals on the device so it may already be active (and stabilized) prior to enabling the LVD module. © 2004 Microchip Technology Inc. DS70056C-page 9-3...
Page 216 Family Reference Manual Register 9-1: RCON: Reset Control Register Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1 TRAPR IOPUWR BGST LVDEN LVDL<3:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 EXTR SWDTEN...
Page 217: Lvd Operation
• If the assigned priority level for the LVD interrupt is greater than the current CPU priority, the device will wake-up and the CPU exception process will begin. Code execution will continue from the first instruction of the LVD ISR. © 2004 Microchip Technology Inc. DS70056C-page 9-5...
Page 218: Design Tips
Family Reference Manual Design Tips Question 1: The LVD circuitry seems to be generating random interrupts? Answer: Ensure that the internal voltage reference is stable before enabling the LVD interrupt. This is done by polling the BGST status bit (RCON<13>) after the LVD module is enabled. After this time delay, the LVDIF bit should be cleared and then, the LVDIE bit may be set.
Page 219: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 220: Revision History
Family Reference Manual Revision History Revision A This is the initial released revision of this document. Revision B There were no technical content or editorial revisions to this section of the manual, however, this section was updated to reflect Revision B throughout the manual.
Page 221: Section 10. Watchdog Timer And Power Saving Modes
10.3 Sleep Mode........................10-2 10.4 Idle Mode ........................10-4 10.5 Interrupts Coincident with Power Save Instructions............. 10-5 10.6 Watchdog Timer......................10-6 10.7 Design Tips ........................10-9 10.8 Related Application Notes..................10-10 10.9 Revision History ......................10-11 © 2004 Microchip Technology Inc. DS70057C-page 10-1...
Page 222: Introduction
10.2 Power Saving Modes The dsPIC30F device family has two special Power Saving modes, Sleep mode and Idle mode, that can be entered through the execution of a special PWRSAV instruction. The assembly syntax of the PWRSAV instruction is as follows: PWRSAV #SLEEP_MODE ;...
Page 223 = PLL lock time (20 µs nominal). LOCK 3: T = Fail-Safe Clock Monitor delay (100 µs nominal). FSCM 4: T Note: Please refer to the “Electrical Specifications” section of the dsPIC30F device data FSCM LOCK sheet for T and T specification values. 10.3.3...
Page 224: Idle Mode
Family Reference Manual 10.3.6 Wake-up from Sleep on Interrupt User interrupt sources that are assigned to CPU priority level 0 cannot wake the CPU from Sleep mode, because the interrupt source is effectively disabled. To use an interrupt as a wake-up source, the CPU priority level for the interrupt must be assigned to CPU priority level 1 or greater.
Page 225: Interrupts Coincident With Power Save Instructions
Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode. © 2004 Microchip Technology Inc. DS70057C-page 10-5...
Page 226: Watchdog Timer
Family Reference Manual 10.6 Watchdog Timer The primary function of the Watchdog Timer (WDT) is to reset the processor in the event of a software malfunction. The WDT is a free running timer, which runs on the internal LPRC oscillator requiring no external components.
Page 227 The WDT time-out period is directly related to the frequency of the LPRC oscillator. The frequency of the LPRC oscillator will vary as a function of device operating voltage and temperature. Please refer to the specific dsPIC30F device data sheet for LPRC clock frequency specifications.
Page 228 Family Reference Manual Table 10-2 shows time-out periods for various prescaler selections: Table 10-2: WDT Time-out Period vs. Prescale A and Prescale B Settings Prescaler A Value Prescaler B Value 1024 2048 3072 4096 5120 6144 7168 1024 8192...
Page 229: Design Tips
Question 3: How do I tell which peripheral woke the device from Sleep or Idle mode? Answer: You can poll the IF bits for each enabled interrupt source to determine the source of wake-up. © 2004 Microchip Technology Inc. DS70057C-page 10-9...
Page 230: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 231: Revision History
There were no technical content or editorial revisions to this section of the manual, however, this section was updated to reflect Revision B throughout the manual. Revision C This revision incorporates all known errata at the time of this document update. © 2004 Microchip Technology Inc. DS70057C-page 10-11...
Page 232 Family Reference Manual NOTES: DS70057C-page 10-12 © 2004 Microchip Technology Inc.
Page 233: Section 11. I/O Ports
11.3 Peripheral Multiplexing....................11-4 11.4 Port Descriptions......................11-5 11.5 Change Notification (CN) Pins ..................11-5 11.6 CN Operation in Sleep and Idle Modes ............... 11-6 11.7 Related Application Notes.................... 11-9 11.8 Revision History ......................11-10 © 2004 Microchip Technology Inc. DS70058C-page 11-1...
Page 234: Introduction
Family Reference Manual 11.1 Introduction This section provides information on the I/O ports for the dsPIC30F family of devices. All of the device pins (except V , MCLR, and OSC1/CLKI) are shared between the peripherals and the general purpose I/O ports.
Page 235: I/O Port Control Registers
Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers, and the port pin, will read as zeros. © 2004 Microchip Technology Inc. DS70058C-page 11-3...
Page 236: Peripheral Multiplexing
11.3.1 I/O Multiplexing with Multiple Peripherals For some dsPIC30F devices, especially those with a small number of I/O pins, multiple peripheral functions may be multiplexed on each I/O pin. Figure 11-2 shows an example of two peripherals multiplexed to the same I/O pin.
Page 237: Port Descriptions
(enabled) for generating CN interrupts. The total number of available CN inputs is dependent on the selected dsPIC30F device. Refer to the device data sheet for further details. Figure 11-3 shows the basic function of the CN hardware.
Page 238: Cn Operation In Sleep And Idle Modes
Family Reference Manual 11.5.1 CN Control Registers There are four control registers associated with the CN module. The CNEN1 and CNEN2 registers contain the CNxIE control bits, where ‘x’ denotes the number of the CN input pin. The CNxIE bit must be set for a CN input pin to interrupt the CPU.
Page 239 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70058C-page 11-7...
Page 240 Family Reference Manual Register 11-3: CNPU1: Input Change Notification Pull-up Enable Register1 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0...
Page 241: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 242: Revision History
This is the initial released revision of this document. Revision B This revision incorporates additional technical content for the dsPIC30F I/O Ports module. Revision C There were no technical content revisions to this section of the manual, however, this section was updated to reflect Revision C throughout the manual.
Page 243: Section 12. Timers
12.11 Reading and Writing into 32-bit Timers..............12-21 12.12 Timer Operation in Power Saving States ..............12-21 12.13 Peripherals Using Timer Modules ................12-22 12.14 Design Tips ........................ 12-24 12.15 Related Application Notes..................12-25 12.16 Revision History ......................12-26 © 2004 Microchip Technology Inc. DS70059C-page 12-1...
Page 244: Introduction
Family Reference Manual 12.1 Introduction Depending on the specific variant, the dsPIC30F device family offers several 16-bit timers. These timers are designated as Timer1, Timer2, Timer3, ..., etc. Each timer module is a 16-bit timer/counter consisting of the following readable/writable registers: •...
Page 245: Timer Variants
12.2.1 Type A Timer At least one Type A timer is available on most dsPIC30F devices. For most dsPIC30F devices, Timer1 is a Type A timer. A Type A timer has the following unique features over other types: • can be operated from the device Low Power 32 kHz Oscillator •...
Page 246 12.2.2 Type B Timer Timer2 and Timer4, if present, are Type B timers on most dsPIC30F devices. A Type B timer has the following unique features over other types of timers: • A Type B timer can be concatenated with a Type C timer to form a 32-bit timer. The TxCON register for a Type B timer has the T32 control bits to enable the 32-bit timer function.
Page 247 1, 8, 64, 256 Note: In certain variants of the dsPIC30F family, the TxCK pin may not be available. Refer to the device data sheet for the I/O pin details. In such cases, the timer must use the system clock (F /4) as its input clock, unless it is configured for 32-bit operation.
Page 248: Control Registers
Family Reference Manual 12.3 Control Registers Register 12-1: TxCON: Type A Time Base Register Upper Byte: R/W-0 R/W-0 — TSIDL — — — — — bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — TGATE TCKPS<1:0>...
Page 249 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70059C-page 12-7...
Page 250 Family Reference Manual Register 12-3: TxCON: Type C Time Base Register Upper Byte: R/W-0 R/W-0 — TSIDL — — — — — bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 — TGATE TCKPS<1:0> — — — bit 7...
Page 251: Modes Of Operation
; at 1:1 and clock source set to ; the internal instruction cycle ; Example code for Timer1 ISR __T1Interrupt: BCLR IFS0, #T1IF ; Reset Timer1 interrupt flag ; User code goes here. RETFIE ; Return from ISR © 2004 Microchip Technology Inc. DS70059C-page 12-9...
Page 252 Family Reference Manual 12.4.2 Synchronous Counter Mode Using External Clock Input When the TCS control bit (TxCON<1>) is set, the clock source for the timer is provided externally and the selected timer increments on every rising edge of clock input on the TxCK pin.
Page 253 T1CON ; clock in the asynchronous mode ; Example code for Timer1 ISR __T1Interrupt: BCLR IFS0, #T1IF ; Reset Timer1 interrupt flag ; User code goes here. RETFIE ; Return from ISR © 2004 Microchip Technology Inc. DS70059C-page 12-11...
Page 254 Family Reference Manual 12.4.4 Timer Operation with Fast External Clock Source In some applications, it may be desirable to use one of the timers to count clock edges from a relatively high frequency external clock source. In these situations, Type A and Type B time...
Page 255 ; Time Accumulation mode BSET T2CON, #TON ; Start Timer2 Example code for Timer2 ISR __T2Interrupt: BCLR IFS0, #T2IF ; Reset Timer2 interrupt flag ; User code goes here. RETFIE ; Return from ISR © 2004 Microchip Technology Inc. DS70059C-page 12-13...
Page 256: Timer Prescalers
Family Reference Manual 12.5 Timer Prescalers The input clock (F /4 or external clock) to all 16-bit timers has prescale options of 1:1, 1:8, 1:64 and 1:256. The clock prescaler is selected using the TCKPS<1:0> control bits (TxCON<5:4>). The prescaler counter is cleared when any of the following occurs: •...
Page 257: Reading And Writing 16-Bit Timer Module Registers
• The LP Oscillator is enabled by setting the LPOSCEN control bit in the OSCCON register. • The 32 kHz crystal is connected to the SOSCO/SOSCI device pins. Refer to Section 7. “Oscillator” for further details. © 2004 Microchip Technology Inc. DS70059C-page 12-15...
Page 258: 32-Bit Timer Configuration
Family Reference Manual 12.9 32-bit Timer Configuration A 32-bit timer module can be formed by combining a Type B and a Type C 16-bit timer module. The Type C time base becomes the MSWord of the combined timer and the Type B time base is the LSWord.
Page 259 Note 1: This block diagram assumes Timer3 is a Type C time base, Timer2 is a Type B time base. 2: Timer configuration bit, T32 (T2CON<3>), must be set to ‘1’ for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. © 2004 Microchip Technology Inc. DS70059C-page 12-17...
Page 260: 32-Bit Timer Modes Of Operation
Family Reference Manual 12.10 32-bit Timer Modes of Operation 12.10.1 Timer Mode Example 12-5 shows how to configure a 32-bit timer in Timer mode. This example assumes Timer2 is a Type B time base and Timer3 is a Type C time base. For 32-bit timer operation, the T32 control bit must be set in the T2CON register (Type B time base).
Page 261 ; 1:8 and clock source set to external clock Example code for Timer3 ISR __T3Interrupt: BCLR IFS0, #T3IF ; Reset Timer3 interrupt flag ; User code goes here. RETFIE ; Return from ISR © 2004 Microchip Technology Inc. DS70059C-page 12-19...
Page 262 Family Reference Manual 12.10.3 Asynchronous Counter Mode Type B and Type C time bases do not support the Asynchronous External Clock mode. Therefore, no 32-bit Asynchronous Counter mode is supported. 12.10.4 Gated Time Accumulation Mode The 32-bit timer operates similarly to a 16-bit timer in Gated Time Accumulation mode.
Page 263: Reading And Writing Into 32-Bit Timers
The TSIDL bit (TxCON<13>) selects if the timer module will stop in Idle mode, or continue to operate normally. If TSIDL = 0, the module will continue operation in Idle mode. If TSIDL = 1, the module will stop in Idle mode. © 2004 Microchip Technology Inc. DS70059C-page 12-21...
Page 264: Peripherals Using Timer Modules
Family Reference Manual 12.13 Peripherals Using Timer Modules 12.13.1 Time Base for Input Capture/Output Compare The Input Capture and Output Compare peripherals can select one of two timer modules as their time base. Refer to Section 13. “Input Capture”, Section 14. “Output Compare”, and the device data sheet for further details.
Page 265 Section 12. Timers © 2004 Microchip Technology Inc. DS70059C-page 12-23...
Page 266: Design Tips
Family Reference Manual 12.14 Design Tips Question 1: Can a timer module be used to wake the device from Sleep mode? Answer: Yes, but only Timer1 has the ability to wake the device from Sleep mode. This is because Timer1 allows the TMR1 register to increment from an external, unsynchronized clock source.
Page 267: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 268: Revision History
This is the initial released revision of this document. Revision B This revision incorporates technical content changes for the dsPIC30F Timers module. Revision C There were no technical content revisions to this section of the manual, however, this section was updated to reflect Revision C throughout the manual.
Page 269: Section 13. Input Capture
13.8 Input Capture Operation in Power Saving States ............13-10 13.9 I/O Pin Control ......................13-10 13.10 Special Function Registers Associated with the Input Capture Module..... 13-11 13.11 Design Tips ........................ 13-12 13.12 Related Application Notes..................13-13 13.13 Revision History ......................13-14 © 2004 Microchip Technology Inc. DS70060C-page 13-1...
Page 270: Introduction
Family Reference Manual 13.1 Introduction This section describes the Input Capture module and its associated Operational modes. The Input Capture module is used to capture a timer value from one of two selectable time bases, upon an event on an input pin. The Input Capture features are quite useful in applications requiring frequency (Time Period) and pulse measurement.
Page 271: Input Capture Registers
Section 13. Input Capture 13.2 Input Capture Registers Each capture channel available on the dsPIC30F devices has the following registers, where ‘x’ denotes the number of the capture channel: • ICxCON: Input Capture Control Register • ICxBUF: Input Capture Buffer Register...
Page 272: Timer Selection
13.3 Timer Selection Each dsPIC30F device may have one or more input capture channels. Each channel can select between one of two 16-bit timers for the time base. Refer to the device data sheet for the specific timers that can be selected.
Page 273 Note 1: A capture signal edge that occurs in this region will result in a capture buffer entry value of 1 or 2 timer counts from the capture signal edge. Figure 13-3: Simple Capture Event Timing Diagram, Time Base Prescaler = 1:4 ICxIF Set TMRy ICx pin Capture Data © 2004 Microchip Technology Inc. DS70060C-page 13-5...
Page 274 Family Reference Manual 13.4.2 Prescaler Capture Events The capture module has two Prescaled Capture modes. The Prescale modes are selected by setting the ICM<2:0> (ICxCON<2:0>) bits to ‘100’ or ‘101’, respectively. In these modes, the capture module counts four or sixteen rising edge pin events before a capture event occurs.
Page 275 Capture mode, the prescaler counter is not cleared. Therefore, it is possible that the first capture event and its associated interrupt is generated due to a non-zero prescaler counter (at the time of switching modes). © 2004 Microchip Technology Inc. DS70060C-page 13-7...
Page 276: Capture Buffer Operation
Family Reference Manual 13.4.3 Edge Detection Mode The capture module can capture a time base count value on every rising and falling edge of the input signal applied to the ICx pin. The Edge Detection mode is selected by setting the ICM<2:0>...
Page 277: Input Capture Interrupts
The input capture module assignment for each UART will depend on the dsPIC30F device variant that is selected. Refer to the device data sheet for further details on the autobaud support.
Page 278: Input Capture Operation In Power Saving States
In the event the capture module has been configured for a mode other than ICM<2:0> = ‘111’ and the dsPIC30F does enter the Sleep mode, no external pin stimulus, rising or falling, will generate a wake-up condition from Sleep.
Page 279 Section 13. Input Capture © 2004 Microchip Technology Inc. DS70060C-page 13-11...
Page 280: Design Tips
Family Reference Manual 13.11 Design Tips Question 1: Can the Input Capture module be used to wake the device from Sleep mode? Answer: Yes. When the Input Capture module is configured to ICM<2:0> = ‘111’ and the respective channel interrupt enable bit is asserted, ICxIE = 1, a rising edge on the capture pin will wake-up the device from Sleep (see Section 13.8 “Input Capture Operation in Power...
Page 281: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 282: Revision History
Family Reference Manual 13.13 Revision History Revision A This is the initial released revision of this document. Revision B There were no technical content or editorial revisions to this section of the manual, however, this section was updated to reflect Revision B throughout the manual.
Page 283: Section 14. Output Compare
14.3 Modes of Operation ..................... 14-4 14.4 Output Compare Operation in Power Saving States..........14-23 14.5 I/O Pin Control ......................14-23 14.6 Design Tips ........................ 14-26 14.7 Related Application Notes..................14-27 14.8 Revision History ......................14-28 © 2004 Microchip Technology Inc. DS70061C-page 14-1...
Page 284: Introduction
Like most dsPIC peripherals, it also has the ability to generate interrupts-on- compare match events. The dsPIC30F device may have up to eight output compare channels, designated OC1, OC2, OC3, etc. Refer to the specific device data sheet for the number of channels available in a particular device.
Page 285: Output Compare Registers
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70061C-page 14-3...
Page 286: Modes Of Operation
Family Reference Manual 14.3 Modes of Operation Each output compare module has the following modes of operation: • Single Compare Match mode • Dual Compare Match mode generating - Single Output Pulse - Continuous Output Pulses • Simple Pulse Width Modulation mode...
Page 287 4000 0000 0001 TMRy 3FFF TMRy Resets Here 4000 OCxR 3002 Cleared by User OCx pin OCxIF Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. © 2004 Microchip Technology Inc. DS70061C-page 14-5...
Page 288 Family Reference Manual 14.3.1.2 Compare Mode Output Driven Low To configure the output compare module for this mode, set control bits OCM<2:0> = ‘010’. The compare time base must also be enabled. Once this Compare mode has been enabled, the output pin, OCx, will be initially driven high and remain high until a match occurs between the Timer and OCxR registers.
Page 289 TMRy Resets Here TMRy Resets Here 0500 OCxR 0500 OCx pin OCxIF Cleared by User Cleared by User Note: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number. © 2004 Microchip Technology Inc. DS70061C-page 14-7...
Page 290 Family Reference Manual Example 14-1: Compare Mode Toggle Mode Pin State Setup The following code example illustrates how to define the initial OC1 pin state for the output compare toggle mode of operation. Toggle mode with initial OC1 pin state set low 0x0001, w0 ;...
Page 291 Figure 14-6 depicts the General Dual Compare mode generating a single output pulse. Figure 14-7 depicts another timing example where OCxRS > PRy. In this example, no falling edge of the pulse is generated since the compare time base resets before counting up to 0x4100. © 2004 Microchip Technology Inc. DS70061C-page 14-9...
Page 292 Family Reference Manual Figure 14-6: Dual Compare Mode 1 Instruction Clock Period 4000 0000 3000 3001 3002 3003 3004 3005 3006 TMRy TMRy Resets Here 4000 OCxR 3000 OCxRS 3003 OCx pin OCxIF Cleared by User Note 1: An ‘x’ represents the output compare channel number. A ‘y’ represents the time base number.
Page 293 The output compare module does not have to be disabled after the falling edge of the output pulse. Another pulse can be initiated by rewriting the value of the OCxCON register. © 2004 Microchip Technology Inc. DS70061C-page 14-11...
Page 294 Family Reference Manual Example 14-3 shows example code for configuration of the single output pulse event. Example 14-3: Single Output Pulse Setup and Interrupt Servicing The following code example will set the Output Compare 1 module for interrupts on the single pulse event and select Timer 2 as the clock source for the compare time base.
Page 295 Note 1: In all the cases considered herein, the TMRy register is assumed to be initialized to 0x0000. 2: OCxR = Compare Register, OCxRS = Secondary Compare Register, TMRy = Timery Count, PRy = Timery Period Register. © 2004 Microchip Technology Inc. DS70061C-page 14-13...
Page 296 Family Reference Manual 14.3.2.4 Dual Compare Mode: Continuous Output Pulses To configure the output compare module for this mode, set control bits OCM<2:0> = ‘101’. In addition, the compare time base must be selected and enabled. Once this mode has been enabled, the output pin, OCx, will be driven low and remain low until a match occurs between the compare time base and OCxR register.
Page 297 TMRy register resets to 0x0000 and resumes counting. 12. Steps 8 through 11 are repeated and a continuous stream of pulses is generated, indefinitely. The OCxIF flag is set on each OCxRS-TMRy compare match event. © 2004 Microchip Technology Inc. DS70061C-page 14-15...
Page 298 Family Reference Manual Example 14-4 shows example code for configuration of the continuous output pulse event. Example 14-4: Continuous Output Pulse Setup and Interrupt Servicing The following code example will set the Output Compare 1 module for interrupts on the continuous pulse event and select Timer 2 as the clock source for the compare time-base.
Page 299 Note 1: In all the cases considered herein, the TMRy register is assumed to be initialized to 0x0000. 2: OCxR = Compare Register, OCxRS = Secondary Compare Register, TMRy = Timery Count, PRy = Timery Period Register. © 2004 Microchip Technology Inc. DS70061C-page 14-17...
Page 300 Family Reference Manual 14.3.3 Pulse Width Modulation Mode When control bits OCM<2:0> (OCxCON<2:0>) are set to ‘110’ or ‘111’, the selected output compare channel is configured for the PWM (Pulse Width Modulation) mode of operation. The following two PWM modes are available: •...
Page 301 A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example: a value of 7 written into the PRy register will yield a period consisting of 8 time base cycles. © 2004 Microchip Technology Inc. DS70061C-page 14-19...
Page 302 Family Reference Manual 14.3.3.3 PWM Duty Cycle The PWM duty cycle is specified by writing to the OCxRS register. The OCxRS register can be written to at any time, but the duty cycle value is not latched into OCxR until a match between PRy and TMRy occurs (i.e., the period is complete).
Page 303 = 120 MHz) PWM Frequency 57 Hz 458 Hz 916 Hz 7.32 kHz 29.3 kHz 234 kHz 938 kHz Timer Prescaler Ratio Period Register Value 0xFFFF 0xFFFF 0x7FFF 0x0FFF 0x03FF 0x007F 0x001F Resolution (bits) © 2004 Microchip Technology Inc. DS70061C-page 14-21...
Page 304 Family Reference Manual Example 14-6 shows configuration and interrupt service code for the PWM mode of operation. Example 14-6: PWM Mode Pulse Setup and Interrupt Servicing The following code example will set the Output Compare 1 module for PWM mode w/o FAULT pin enabled, a 50% duty cycle and a PWM frequency of 52.08 kHz at Fosc = 40 MHz.
Page 305: Output Compare Operation In Power Saving States
PWM Fault Protection A Input (For Channels 1-4) OCFB PWM Fault Protection B Input (For Channels 5 -8) Legend: ST = Schmitt Trigger input with CMOS levels, I = Input, O = Output © 2004 Microchip Technology Inc. DS70061C-page 14-23...
Page 306 Family Reference Manual DS70061C-page 14-24 © 2004 Microchip Technology Inc.
Page 307 Section 14. Output Compare © 2004 Microchip Technology Inc. DS70061C-page 14-25...
Page 308: Design Tips
Family Reference Manual 14.6 Design Tips Question 1: The Output Compare pin stops functioning even when the OCSIDL bit is not set. Why? Answer: This is most likely to occur when the TSIDL bit (TxCON<13>) of the associated timer source is set.
Page 309: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 310: Revision History
Family Reference Manual 14.8 Revision History Revision A This is the initial released revision of this document. Revision B There were no technical content or editorial revisions to this section of the manual, however, this section was updated to reflect Revision B throughout the manual.
Page 311 15.12 PWM Special Event Trigger ..................15-35 15.13 Operation in Device Power Saving Modes ..............15-36 15.14 Special Features for Device Emulation ..............15-37 15.15 Related Application Notes..................15-40 15.16 Revision History ......................15-41 © 2004 Microchip Technology Inc. DS70062C-page 15-1...
Page 312: Introduction
A 6-output MCPWM module is also available and is typically found on smaller devices that have less than 64 pins. A given dsPIC30F device may have more than one MCPWM module. Please refer to the specific device data sheet for further details.
Page 313: Section 15. Motor Control Pwm
Special Event Comparator Special Event Trigger for A/D converter Postscaler SEVTCMP Note Details of PWM Generator #2, #3 and #4 not shown for clarity. Logic within dashed lines not present on 6-output MCPWM module. © 2004 Microchip Technology Inc. DS70062C-page 15-3...
Page 314: Control Registers
Family Reference Manual 15.2 Control Registers The following registers control the operation of the MCPWM module: • PTCON: PWM Time Base Control register • PTMR: PWM Time Base register • PTPER: PWM Time Base Period register • SEVTCMP: PWM Special Event Compare register •...
Page 315 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70062C-page 15-5...
Page 316 Family Reference Manual Register 15-2: PTMR: PWM Time Base Register Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTDIR PTMR <14:8> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTMR <7:0> bit 7...
Page 317 R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70062C-page 15-7...
Page 318 Family Reference Manual Register 15-6: PWMCON2: PWM Control Register 2 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 — — — — SEVOPS<3:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 — — — — — — OSYNC UDIS bit 7 bit 0 bit 15-12 Unimplemented: Read as ‘0’...
Page 319 R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70062C-page 15-9...
Page 320 Family Reference Manual Register 15-8: DTCON2: Dead Time Control Register 2 Upper Byte: — — — — — — — — bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DTS4A DTS4I DTS3A DTS3I...
Page 321 R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70062C-page 15-11...
Page 322 Family Reference Manual Register 15-10: FLTBCON: Fault B Control Register Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FBOV4H FBOV4L FBOV3H FBOV3L FBOV2H FBOV2L FBOV1H FBOV1L bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 FLTBM —...
Page 323 R = Readable bit W = Writable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70062C-page 15-13...
Page 324 Family Reference Manual Register 15-13: PDC2: PWM Duty Cycle Register 2 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PWM Duty Cycle #2 bits 15-8 bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...
Page 325 W = Writable bit U = Unimplemented, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown P = Programmable configuration bit © 2004 Microchip Technology Inc. DS70062C-page 15-15...
Page 326: Pwm Time Base
Family Reference Manual 15.3 PWM Time Base The PWM time base is provided by a 15-bit timer with a prescaler and postscaler (see Figure 15-2). The 15 bits of the time base are accessible via the PTMR register. PTMR<15> is a read-only status bit, PTDIR, that indicates the present count direction of the PWM time base.
Page 327 The postscaler counter is cleared when any of the following occurs: • A write to the PTMR register • A write to the PTCON register • Any device reset The PTMR register is not cleared when PTCON is written. © 2004 Microchip Technology Inc. DS70062C-page 15-17...
Page 328 Family Reference Manual 15.3.6 PWM Time Base Interrupts The interrupt signals generated by the PWM time base depend on the mode selection bits, PTMOD<1:0> (PTCON<1:0>), and the time base postscaler bits, PTOPS<3:0> (PTCON<7:4>). • Free Running Mode When the PWM time base is in the Free Running mode (PTMOD<1:0> = 00), an interrupt is generated when the PTMR register is reset to ‘0’, due to a match with the PTPER register.
Page 329 = 1000 -1 = 999 Note: If the PWM time base is configured for one of the two up/down count modes, the PWM period will be twice the value provided by Equation 15-1. © 2004 Microchip Technology Inc. DS70062C-page 15-19...
Page 330: Pwm Duty Cycle Comparison Units
Family Reference Manual 15.4 PWM Duty Cycle Comparison Units The MCPWM module has four PWM generators. There are four 16-bit special function registers used to specify duty cycle values for the PWM generators: • PDC1 • PDC2 • PDC3 •...
Page 331 PWM period if the value in the PDCx register is greater than the value held in the PTPER register. Figure 15-6: Edge-Aligned PWM New duty cycle loaded from PDCx PTPER PTMR value PDC1 PDC2 PWM1H Duty Cycle PWM2H Period © 2004 Microchip Technology Inc. DS70062C-page 15-21...
Page 332 Family Reference Manual 15.4.3 Single Event PWM Operation The PWM module will produce single pulse outputs when the PWM time base is configured for the single event mode (PTMOD<1:0> = 01). This mode of operation is useful for driving certain types of electronically commutated motors.
Page 333 PTMR register matches the value in the PTPER register. Figure 15-10 indicates the times when the duty cycle updates occur for this mode of the PWM time base. © 2004 Microchip Technology Inc. DS70062C-page 15-23...
Page 334: Complementary Pwm Output Mode
Family Reference Manual Figure 15-9: Duty Cycle Update Times in Up/Down Count Mode Duty cycle value loaded from PDCx register, CPU interrupted PWM output PTMR Value PTIF New value written to PDCx register Figure 15-10: Duty Cycle Update Times in Up/Down Count Mode with Double Updates...
Page 335: Dead Time Control
PWM outputs is shown in Figure 15-14. The use of two different dead times for the rising and falling edge events has been exaggerated in the figure for clarity. © 2004 Microchip Technology Inc. DS70062C-page 15-25...
Page 336 Family Reference Manual Figure 15-13: Dead Time Unit Block Diagram for One Output Pin Pair Zero Compare Prescaler Clock Control 6-Bit Down Counter High-side PWM signal to output pin Low-Side PWM signal to output pin Dead Time Select Logic...
Page 337 • 2 T • 4 T • 8 T Equation 15-3: Dead Time Calculation Dead Time DT = Prescale Value • T Note: DT (Dead Time) is the DTA<5:0> or DTB<5:0> register value. © 2004 Microchip Technology Inc. DS70062C-page 15-27...
Page 338: Independent Pwm Output Mode
Family Reference Manual Table 15-4 shows example dead time ranges as a function of the input clock prescaler selected and the device operating frequency. Table 15-4: Example Dead Time Ranges Prescaler Selection Resolution Dead Time Range 33 ns (30 MHz)
Page 339: Pwm Output Override
OVDCON register controls the commutation. Such an example is shown in Figure 15-18. The OVDCON register values used to generate the signals in Figure 15-18 are given in Table 15-6. © 2004 Microchip Technology Inc. DS70062C-page 15-29...
Page 340 Family Reference Manual Table 15-5: PWM Output Override Example #1 State OVDCON<15:8> OVDCON<7:0> 00000000b 00100100b 00000000b 00100001b 00000000b 00001001b 00000000b 00011000b 00000000b 00010010b 00000000b 00000110b Figure 15-17: PWM Output Override Example #1 STATE PWM3H PWM3L PWM2H PWM2L PWM1H PWM1L Note: Switching times between states 1-6 are controlled by user software.
Page 341 Note: Switching times between states 1-4 are controlled by user software. The state switch is controlled by writing a new value to OVDCON. The PWM outputs are operated in the independent mode for this example. © 2004 Microchip Technology Inc. DS70062C-page 15-31...
Page 342: Pwm Output And Polarity Control
Family Reference Manual 15.9 PWM Output and Polarity Control The PENxx control bits in PWMCON1 enable each PWM output pin for use by the module. When a pin is enabled for PWM output, the PORT and TRIS registers controlling the pin are disabled.
Page 343 When the FLTA pin is programmed for Latched mode, the PWM outputs will not return to the Fault B states or normal operation until the Fault A interrupt flag has been cleared and the FLTA pin is de-asserted. © 2004 Microchip Technology Inc. DS70062C-page 15-33...
Page 344 Family Reference Manual 15.10.5 Fault Pin Software Control Each of the fault pins can be controlled manually in software. Since each fault input is shared with a PORT I/O pin, the PORT pin can be configured as an output by clearing the corresponding TRIS bit.
Page 345: Pwm Update Lockout
PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode. © 2004 Microchip Technology Inc. DS70062C-page 15-35...
Page 346: Operation In Device Power Saving Modes
Family Reference Manual 15.12.1 Special Event Trigger Enable The PWM module will always produce the special event trigger signal. This signal may optionally be used by the A/D module. Refer to Section Section 17. “10-bit A/D Converter” for more information on using the special event trigger.
Page 347: Special Features For Device Emulation
(see Section 15.9 “PWM Output and Polarity Control”). The hardware debugger or emulation tool provides a method to change the values of these configuration bits. Please refer to the tool’s user’s manual for more information. © 2004 Microchip Technology Inc. DS70062C-page 15-37...
Page 348 Family Reference Manual DS70062C-page 15-38 © 2004 Microchip Technology Inc.
Page 349 Section 15. Motor Control PWM © 2004 Microchip Technology Inc. DS70062C-page 15-39...
Page 350: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent, and could be used with modification and possible limitations. The current...
Page 351: Revision History
Revision A This is the initial released revision of this document. Revision B This revision provides expanded information for the dsPIC30F MCPWM module. Revision C This revision incorporates all known errata at the time of this document update. © 2004 Microchip Technology Inc.
Page 352 Family Reference Manual NOTES: DS70062C-page 15-42 © 2004 Microchip Technology Inc.
Page 353: Section 16. Quadrature Encoder Interface (Qei)
16.8 I/O Pin Control ......................16-18 16.9 QEI Operation During Power Saving Modes ............. 16-19 16.10 Effects of a Reset....................... 16-19 16.11 Design Tips ........................ 16-21 16.12 Related Application Notes..................16-22 16.13 Revision History ......................16-23 © 2004 Microchip Technology Inc. DS70063C-page 16-1...
Page 354: Module Introduction
Family Reference Manual 16.1 Module Introduction 16.1.1 Features Overview Quadrature encoders (a.k.a. Incremental encoders or Optical encoders) are used in position and speed detection of rotating motion systems. Quadrature encoders enable closed loop control of many motor control applications, such as Switched Reluctance (SR) motor and AC Induction Motor (ACIM).
Page 355 Quadrature Encoder Interface Module Simplified Block Diagram Clock Divider Digital Filter CLOCK Quadrature 16-Bit Up/Down Reset Digital Decoder Counter Filter Logic (POSCNT) Comparator/ EQUAL Digital Zero Detect INDX Filter Max Count Register (MAXCNT) UPDN © 2004 Microchip Technology Inc. DS70063C-page 16-3...
Page 356: Control And Status Registers
Family Reference Manual 16.2 Control and Status Registers The QEI module has four user-accessible registers. The registers are accessible in either byte or word mode. The registers are shown in Figure 16-3 and listed below: • Control/Status Register (QEICON) – This register allows control of the QEI operation and status flags indicating the module state.
Page 357 TQCKPS<1:0>: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value (Prescaler utilized for 16-bit timer mode only) © 2004 Microchip Technology Inc. DS70063C-page 16-5...
Page 358 Family Reference Manual Register 16-1: QEICON: QEI Control Register (Continued) bit 2 POSRES: Position Counter Reset Enable bit 1 = Index Pulse resets Position Counter 0 = Index Pulse does not reset Position Counter (Bit only applies when QEIM<2:0> = 100 or 110)
Page 359 001 = 1:2 Clock Divide 000 = 1:1 Clock Divide Note: The available control bits in the DFLTCON Register may vary depending on the dsPIC30F device that is used. Refer to Register 16-2 and Register 16-3 for details. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’...
Page 360 000 = 1:1 Clock Divide bit 3-0 Unimplemented: Read as ‘0’ Note: The available control bits in the DFLTCON Register may vary depending on the dsPIC30F device that is used. Refer to Register 16-2 and Register 16-3 for details. Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’...
Page 361: Programmable Digital Noise Filters
Simplified Digital Noise Filter Block Diagram Non-filtered Filter Output Filtered QEOUT Clock Divider Circuit QECK<2:0> Note: ‘n’ denotes the phase input, A or B. Figure 16-5: Signal Propagation Through Filter, 1:1 Filter Clock Divide QEn Pin QEn Filter © 2004 Microchip Technology Inc. DS70063C-page 16-9...
Page 362: Quadrature Decoder
Family Reference Manual 16.4 Quadrature Decoder Position measurement modes are selected when QEIM2 = 1 (QEICON<10>). When QEIM1 = 1 (QEICON<9>), the ‘x4’ measurement mode is selected and the QEI logic clocks the position counter on both edges of the Phase A and Phase B input signals.
Page 363 Phase B signal to be fed to the A input of the quadrature counter. Therefore, if the Phase A signal leads the Phase B signal at the dsPIC30F device pins, the Phase A input to the quadrature counter will now lag the Phase B input. This is recognized as rotation in the reverse direction and the counter will be decremented on each quadrature pulse.
Page 364: 16-Bit Up/Down Position Counter
Family Reference Manual 16.4.4 Quadrature Rate The RPM of the position control system will vary. The RPMs along with the quadrature encoder line count determine the frequency of the QEA and QEB input signals. The quadrature encoder signals can be decoded such that a count pulse is generated for every quadrature signal edge.
Page 365 0003 0002 0001 0000 0006 0005 0004 0003 0002 0001 UPDN 0006 MAXCNT POSCNT = MAXCNT POSCNT = 0000 Generate QEI Interrupt Generate QEI Interrupt POSCNT set to 0000 POSCNT set to MAXCNT © 2004 Microchip Technology Inc. DS70063C-page 16-13...
Page 366 Family Reference Manual 16.5.3 Using Index to Reset Position Counter When QEIM<0> = 0, the index pulse is utilized for resetting the position counter. For this mode the position counter reset mechanism operates as follows: (See Figure 16-9 for related timing details).
Page 367 The position counter will continue counting up or down and be reset on the rollover or underflow condition. The QEI continues to generate interrupts on the detection of the index pulse. © 2004 Microchip Technology Inc. DS70063C-page 16-15...
Page 368: Using Qei As An Alternate 16-Bit Timer/Counter
16-bit timer/counter. The setup and control for the auxiliary timer is accomplished through the QEICON register. The QEI timer functions similar to the other dsPIC30F timers. Refer to Section 12. “Timers” for a general discussion of timers.
Page 369: Quadrature Encoder Interface Interrupts
When a QEI interrupt event occurs, the QEIIF bit (IFS2<8>) is asserted and an interrupt will be generated if enabled. The QEIIF bit must be cleared in software. Enabling the QEI interrupt is accomplished via the respective enable bit, QEIIE (IEC2<8>). © 2004 Microchip Technology Inc. DS70063C-page 16-17...
Page 370: I/O Pin Control
Family Reference Manual 16.8 I/O Pin Control Enabling the QEI module causes the associated I/O pins to come under the control of the QEI and prevents lower priority I/O functions such as Ports from affecting the I/O pin. Depending on the mode specified by QEIM<2:0> and other control bits, the I/O pins may assume differing functions, as shown in Table 16-2 and Table 16-3.
Page 371: Qei Operation During Power Saving Modes
Reset forces module registers to their initial reset state. See Register 16-1 for all initialization and reset conditions for QEI module related registers. The quadrature decoder and the POSCNT counter are reset to an initial state. © 2004 Microchip Technology Inc. DS70063C-page 16-19...
Page 372 Family Reference Manual DS70063C-page 16-20 © 2004 Microchip Technology Inc.
Page 373: Design Tips
POSCNT 00E4 0000 0001 0002 0003 0002 0001 0000 00E4 00E3 00E2 UPDN Generate QEI Interrupt Generate QEI Interrupt POSCNT set to 0000 POSCNT set to MAXCNT Recognize Index Recognize Index Wheel Reverses © 2004 Microchip Technology Inc. DS70063C-page 16-21...
Page 374: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 375: Revision History
Revision A This is the initial released revision of this document. Revision B This revision provides expanded information for the dsPIC30F Quadrature Encoder Interface (QEI) module. Revision C This revision incorporates all known errata at the time of this document update.
Page 376 Family Reference Manual NOTES: DS70063C-page 16-24 © 2004 Microchip Technology Inc.
Page 377: Section 17. 10-Bit A/D Converter
17.22 Operation During Sleep and Idle Modes..............17-49 17.23 Effects of a Reset....................... 17-49 17.24 Special Function Registers Associated with the 10-bit A/D Converter....... 17-50 17.25 Design Tips ........................ 17-51 17.26 Related Application Notes..................17-52 17.27 Revision History ......................17-53 © 2004 Microchip Technology Inc. DS70064C-page 17-1...
Page 378: Introduction
These voltage reference inputs may be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific dsPIC30F device. Refer to the device data sheet for further details.
Page 379 1000 1001 1010 AN10 1011 AN11 1100 AN12 1101 AN13 1110 AN14 1111 AN15 Note: V +, V - inputs may be shared with other analog inputs. See device data sheet for details. © 2004 Microchip Technology Inc. DS70064C-page 17-3...
Page 380: Control Registers
Family Reference Manual 17.2 Control Registers The A/D module has six Control and Status registers. These registers are: • ADCON1: A/D Control Register 1 • ADCON2: A/D Control Register 2 • ADCON3: A/D Control Register 3 • ADCHS: A/D Input Channel Select Register •...
Page 381 0 = Samples multiple channels individually in sequence bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes. SAMP bit is auto set. 0 = Sampling begins when SAMP bit set © 2004 Microchip Technology Inc. DS70064C-page 17-5...
Page 382 Family Reference Manual Register 17-1: ADCON1: A/D Control Register 1 (Continued) bit 1 SAMP: A/D Sample Enable bit 1 = At least one A/D sample/hold amplifier is sampling 0 = A/D sample/hold amplifiers are holding When ASAM = 0, writing ‘1’ to this bit will start sampling.
Page 383 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70064C-page 17-7...
Page 384 Family Reference Manual Register 17-3: ADCON3: A/D Control Register 3 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — SAMC<4:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC — ADCS<5:0> bit 7 bit 0 bit 15-13 Unimplemented: Read as ‘0’...
Page 385 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70064C-page 17-9...
Page 386 Family Reference Manual Register 17-5: ADPCFG: A/D Port Configuration Register Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0...
Page 387: A/D Terminology And Conversion Sequence
S/H amplifiers to perform two conversions in a sample/convert sequence or four S/H amplifiers with four conversions. The number of S/H amplifiers, or channels per sample, used in the sample/convert sequence, is determined by the CHPS control bits. © 2004 Microchip Technology Inc. DS70064C-page 17-11...
Page 388 Family Reference Manual A sample/convert sequence that uses multiple S/H channels can be simultaneously sampled or sequentially sampled, as controlled by the SIMSAM bit (ADCON1<3>). Simultaneously sampling multiple signals ensures that the snapshot of the analog inputs occurs at precisely the same time for all inputs.
Page 389: A/D Module Configuration
The internal RC clock source should be used when A/D conversions are performed while the dsPIC30F is in Sleep mode. The internal RC oscillator is selected by setting the ADRC bit (ADCON3<7>). When the ADRC bit is set, the ADCS<5:0> bits have no effect on the A/D operation.
Page 390: Selecting Analog Inputs For Sampling
Family Reference Manual 17.8 Selecting Analog Inputs for Sampling All Sample-and-Hold Amplifiers have analog multiplexers (see Figure 17-1) on both their non-inverting and inverting inputs to select which analog input(s) are sampled. Once the sample/convert sequence is specified, the ADCHS bits determine which analog inputs are selected for each sample.
Page 391 0 input will alternate between a set of scanning inputs specified by the ADCSSL register and a fixed input specified by the CH0SB bits. © 2004 Microchip Technology Inc. DS70064C-page 17-15...
Page 392: Enabling The Module
Family Reference Manual 17.8.3 Channel 1, 2 and 3 Input Selection Channel 1, 2 and 3 can sample a subset of the analog input pins. Channel 1, 2 and 3 may select one of two groups of 3 inputs.
Page 393: How To Start Sampling
If the SIMSAM bit specifies simultaneous sampling, sampling on a channel resumes after the conversion of all channels completes. For an example, see Figure 17-5. © 2004 Microchip Technology Inc. DS70064C-page 17-17...
Page 394: How To Stop Sampling And Start Conversions
The SSRC<2:0> bits (ADCON1<7:5>) select the source of the conversion trigger. Note: The available conversion trigger sources may vary depending on the dsPIC30F device variant. Please refer to the specific device data sheet for the available conversion trigger sources.
Page 395 (1) // repeat continuously DelayNmSec(100); // sample for 100 mS ADCON1bits.SAMP = 0; // start Converting while (!ADCON1bits.DONE); // conversion done? ADCValue = ADCBUF0; // yes then get ADC value // repeat © 2004 Microchip Technology Inc. DS70064C-page 17-19...
Page 396 Family Reference Manual 17.12.2 Clocked Conversion Trigger When SSRC<2:0> = 111, the conversion trigger is under A/D clock control. The SAMC bits (ADCON3<12:8>) select the number of T clock cycles between the start of sampling and the start of conversion. This trigger option provides the fastest conversion rates on multiple channels.
Page 397 ADCON1bits.ASAM = 0; // yes then stop sample/convert for (count = 0; count < 2; count++) // average the 2 ADC value ADCValue = ADCValue + *ADC16Ptr++; ADCValue = ADCValue >> 1; // repeat © 2004 Microchip Technology Inc. DS70064C-page 17-21...
Page 398 Family Reference Manual 17.12.2.2 Multiple Channels with Simultaneous Sampling As shown in Figure 17-8 when using simultaneous sampling, the SAMC value specifies the sampling time. In the example, SAMC specifies a sample time of 3 T . Because automatic sample start is active, sampling will start on all channels after the last conversion ends and will continue for 3 A/D clocks.
Page 399 Channels per Sample (CH/S) * ((SAMC<4:0> * T ) + Conversion Time (T CONV – T CONV Note 1: CH/S specified by CHPS<1:0> bits. 2: T is the total time for the sample/convert sequence. © 2004 Microchip Technology Inc. DS70064C-page 17-23...
Page 400 Family Reference Manual 17.12.3 Event Trigger Conversion Start It is often desirable to synchronize the end of sampling and the start of conversion with some other time event. The A/D module may use one of three sources as a conversion trigger.
Page 401 // start auto sampling every 125 mSecs while (1) // repeat continuously while (!IFS0bits.ADIF); // conversion done? ADCValue = ADCBUF0; // yes then get first ADC value IFS0bits.ADIF = 0; // clear ADIF // repeat © 2004 Microchip Technology Inc. DS70064C-page 17-25...
Page 402 Family Reference Manual 17.12.3.5 Multiple Channels with Simultaneous Sampling As shown in Figure 17-12 when using simultaneous sampling, the sampling will start on all channels after setting the ASAM bit or when the last conversion ends. Sampling will stop and conversions will start when the conversion trigger occurs.
Page 403 Figure 17-13: Converting 4 Channels, Auto-Sample Start, Trigger Conversion Start, Sequential Sampling Conversion Trigger ADCLK CONV CONV CONV CONV ch0_samp SAMP SAMP ch1_samp SAMP ch2_samp SAMP ch3_samp SAMP ADCBUF0 ADCBUF1 ADCBUF2 ADCBUF3 Cleared in software DONE SAMP © 2004 Microchip Technology Inc. DS70064C-page 17-27...
Page 404 Family Reference Manual 17.12.3.7 Sample Time Considerations for Automatic Sampling/Conversion Sequences Different sample/conversion sequences provide different available sampling times for the S/H channel to acquire the analog signal. The user must ensure the sampling time exceeds the sampling requirements, as outlined in Section 17.16 “A/D Sampling Requirements”.
Page 405: Controlling Sample/Conversion Operation
NOT be updated with the partially completed A/D conversion sample. That is, the corresponding ADCBUF buffer location will continue to contain the value of the last completed conversion (or the last value written to the buffer). © 2004 Microchip Technology Inc. DS70064C-page 17-29...
Page 406: Specifying How Conversion Results Are Written Into The Buffer
Family Reference Manual 17.14 Specifying How Conversion Results are Written Into the Buffer As conversions are completed, the module writes the results of the conversions into the A/D result buffer. This buffer is a RAM array of sixteen 10-bit words. The buffer is accessed through 16 address locations within the SFR space named ADCBUF0...ADCBUFF.
Page 407: Conversion Sequence Examples
Figure 17-14: Converting One Channel 16 Times/Interrupt Conversion Trigger SAMP SAMP SAMP SAMP ADCLK CONV CONV CONV CONV Input to CH0 ASAM SAMP DONE ADCBUF0 ADCBUF1 ADCBUFE ADCBUFF ADIF Instruction Execution BSF ADCON1,ASAM © 2004 Microchip Technology Inc. DS70064C-page 17-31...
Page 408 Family Reference Manual Table 17-2: Converting One Channel 16 Times/Interrupt CONTROL BITS OPERATION SEQUENCE Sequence Select Sample MUX A Inputs: AN0 -> CH0 SMPI<2:0> = 1111 Convert CH0, Write Buffer 0x0 Interrupt on 16th sample Sample MUX A Inputs: AN0 -> CH0 CHPS<1:0>...
Page 409 Figure 17-15: Scanning Through 16 Inputs/Interrupt Conversion Trigger SAMP SAMP SAMP SAMP ADCLK CONV CONV CONV CONV Input to CH0 AN14 AN15 ASAM SAMP DONE ADCBUF0 ADCBUF1 ADCBUFE ADCBUFF ADIF Instruction Execution BSET ADCON1,#ASAM © 2004 Microchip Technology Inc. DS70064C-page 17-33...
Page 410 Family Reference Manual Table 17-3: Scanning Through 16 Inputs/Interrupt CONTROL BITS OPERATION SEQUENCE Sequence Select Sample MUX A Inputs: AN0 -> CH0 SMPI<2:0> = 1111 Convert CH0, Write Buffer 0x0 Interrupt on 16th sample Sample MUX A Inputs: AN1 -> CH0 CHPS<1:0>...
Page 411 CONV CONV CONV CONV CONV CONV CONV CONV CONV Input to CH0 Input to CH1 Input to CH2 Input to CH3 ASAM SAMP DONE ADCBUF0 ADCBUF1 ADCBUF2 ADCBUF3 ADCBUFC ADCBUFD ADCBUFE ADCBUFF ADIF © 2004 Microchip Technology Inc. DS70064C-page 17-35...
Page 412 Family Reference Manual Table 17-4: Converting Three Inputs, Four Times and Four Inputs, One Time/Interrupt CONTROL BITS OPERATION SEQUENCE Sequence Select Sample MUX A Inputs: SMPI<3:0> = 0011 AN4 -> CH0, AN0 -> CH1, AN1 -> CH2, AN2 -> CH3...
Page 413 CONV CONV Input to CH0 Input to CH1 Input to CH2 Input to CH3 SAMP BUFS ADCBUF0 ADCBUF1 ADCBUF2 ADCBUF3 ADCBUF8 ADCBUF9 ADCBUFA ADCBUFB ADIF BSET ADCON1,#ASAM BCLR IFS0,#ADIF BCLR IFS0,#ADIF Instruction Execution © 2004 Microchip Technology Inc. DS70064C-page 17-37...
Page 414 Family Reference Manual Table 17-5: Converting Four Inputs, One Time/Interrupt Using Dual 8-Word Buffers CONTROL BITS OPERATION SEQUENCE Sequence Select Sample MUX A Inputs: SMPI<2:0> = 0000 AN3 -> CH0, AN0 -> CH1, AN1 -> CH2, AN2 -> CH3...
Page 415 Input to AN15 AN15 AN15 Input to AN3-AN9 AN3-AN9 AN3-AN9 ASAM SAMP Cleared in software DONE BUFS ADCBUF0 ADCBUF1 ADCBUF2 ADCBUF3 ADCBUF4 ADCBUF5 ADCBUF6 ADCBUF7 ADCBUF8 ADCBUF9 ADCBUFA ADCBUFB ADIF Cleared by Software © 2004 Microchip Technology Inc. DS70064C-page 17-39...
Page 416 Family Reference Manual Table 17-6: Converting Two Sets of Two Inputs Using Alternating Input Selections CONTROL BITS OPERATION SEQUENCE Sequence Select Sample MUX A Inputs: AN1 -> CH0, AN0 -> CH1 SMPI<2:0> = 0011 Convert CH0, Write Buffer 0x0...
Page 417 Input to CH0 AN13-AN1 AN14 AN14 AN13-AN1 Input to CH1 AN3-AN6 AN3-AN6 Input to CH2 AN4-AN7 AN4-AN7 Input to CH3 AN5-AN8 AN5-AN8 ASAM SAMP DONE ADCBUF0 ADCBUF1 ADCBUF2 ADCBUF3 ADCBUFC ADCBUFD ADCBUFE ADCBUFF ADIF © 2004 Microchip Technology Inc. DS70064C-page 17-41...
Page 418 Family Reference Manual Table 17-7: Sampling Eight Inputs Using Simultaneous Sampling CONTROL BITS OPERATION SEQUENCE Sequence Select Sample MUX A Inputs: SMPI<2:0> = 0011 (AN13-AN1) -> CH0, AN0 -> CH1, AN1 -> CH2, AN2 -> CH3 Interrupt on 4th sample Convert CH0, Write Buffer 0x0 CHPS<1:0>...
Page 419 AN13-AN1 AN14 AN13-AN1 Input to CH0 AN3-AN6 AN3-AN6 Input to CH1 Input to CH2 AN4-AN7 AN4-AN7 AN5-AN8 Input to CH3 AN5-AN8 ASAM SAMP DONE ADCBUF0 ADCBUF1 ADCBUF2 ADCBUF3 ADCBUFC ADCBUFD ADCBUFE ADCBUFF ADIF © 2004 Microchip Technology Inc. DS70064C-page 17-43...
Page 420 Family Reference Manual Table 17-8: Sampling Eight Inputs Using Sequential Sampling CONTROL BITS OPERATION SEQUENCE Sequence Select Sample: (AN13-AN1) -> CH0 SMPI<2:0> = 1111 Convert CH0, Write Buffer 0x0 Interrupt on 16th sample Sample: AN0 -> CH1 CHPS<1:0> = 1x...
Page 421: A/D Sampling Requirements
= interconnect resistance = sampling switch resistance HOLD = sample/hold capacitance (from DAC) Note: C negligible if Rs ≤ 5 kΩ. value depends on device package and is not tested. Effect of C © 2004 Microchip Technology Inc. DS70064C-page 17-45...
Page 422: Reading The A/D Result Buffer
Family Reference Manual 17.17 Reading the A/D Result Buffer The RAM is 10-bits wide, but the data is automatically formatted to one of four selectable formats when a read from the buffer is performed. The FORM<1:0> bits (ADCON1<9:8>) select the format.
Page 423: Transfer Function
Any external components connected (via high-impedance) to an analog input pin (capacitor, zener diode, etc.) should have very little leakage current at the pin. © 2004 Microchip Technology Inc. DS70064C-page 17-47...
Page 424: Initialization
Family Reference Manual 17.21 Initialization Example 17-7 shows a simple initialization code example for the A/D module. In this particular configuration, all 16 analog input pins, AN0-AN15, are set up as analog inputs. Operation in Idle mode is disabled output data is in unsigned fractional format, and AV...
Page 425: Operation During Sleep And Idle Modes
All pins that are multiplexed with analog inputs will be configured as analog inputs. The corresponding TRIS bits will be set. The values in the ADCBUF registers are not initialized during a Power-on Reset. ADCBUF0...ADCBUFF will contain unknown data. © 2004 Microchip Technology Inc. DS70064C-page 17-49...
Page 426 Section 17. 10-bit A/D Converter © 2004 Microchip Technology Inc. DS70064C-page 17-50...
Page 427: Design Tips
Question 3: My combination of channels/sample and samples/interrupt is greater than the size of the buffer. What will happen to the buffer? Answer: This configuration is not recommended. The buffer will contain unknown results. © 2004 Microchip Technology Inc. DS70064C-page 17-51...
Page 428: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 429: Revision History
This is the initial released revision of this document. Revision B To reflect editorial and technical content revisions for the dsPIC30F 10-bit A/D Converter module. Revision C This revision incorporates all known errata at the time of this document update.
Page 430 Family Reference Manual NOTES: DS70064C-page 17-54 © 2004 Microchip Technology Inc.
Page 431: Section 18. 12-Bit A/D Converter
18.21 Operation During Sleep and Idle Modes..............18-30 18.22 Effects of a Reset....................... 18-30 18.23 Special Function Registers Associated with the 12-bit A/D Converter....... 18-31 18.24 Design Tips ........................ 18-32 18.25 Related Application Notes..................18-33 18.26 Revision History ......................18-34 © 2004 Microchip Technology Inc. DS70065C-page 18-1...
Page 432: Introduction
These voltage reference inputs may be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific dsPIC30F device. Refer to the dsPIC30F device data sheets (DS70082 and DS70083) for further details.
Page 433 Conversion Logic 0011 0100 16-word, 12-bit 0101 Dual Port 0110 0111 Sample/Sequence 1000 Sample Control 1001 1010 Input AN10 Input MUX Switches Control 1011 AN11 1100 AN12 1101 AN13 1110 AN14 1111 AN15 © 2004 Microchip Technology Inc. DS70065C-page 18-3...
Page 434: Control Registers
Family Reference Manual 18.2 Control Registers The A/D module has six Control and Status registers. These registers are: • ADCON1: A/D Control Register 1 • ADCON2: A/D Control Register 2 • ADCON3: A/D Control Register 3 • ADCHS: A/D Input Channel Select Register •...
Page 435 HC = Hardware clear HS = Hardware set U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70065C-page 18-5...
Page 436 Family Reference Manual Register 18-2: ADCON2: A/D Control Register 2 Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 VCFG<2:0> — — CSCNA — — bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS — SMPI<3:0> BUFM ALTS...
Page 437 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70065C-page 18-7...
Page 438 Family Reference Manual Register 18-4: ADCHS: A/D Input Select Register Upper Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CH0NB CH0SB<3:0> bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — CH0NA CH0SA<3:0> bit 7 bit 0 bit 15-13 Unimplemented: Read as ‘0’...
Page 439 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70065C-page 18-9...
Page 440: A/D Terminology And Conversion Sequence
Family Reference Manual 18.4 A/D Terminology and Conversion Sequence Figure 18-2 shows a basic conversion sequence and the terms that are used. A sampling of the analog input pin voltage is performed by sample and hold S/H amplifiers. The S/H amplifiers are also called S/H channels.
Page 441: A/D Module Configuration
V + and V - input pins. The voltages applied to the external reference pins must meet certain specifications. Refer to the “Electrical Specifications” section of the device data sheet for further details. © 2004 Microchip Technology Inc. DS70065C-page 18-11...
Page 442: Selecting The A/D Conversion Clock
The internal RC clock source should be used when A/D conversions are performed while the dsPIC30F is in Sleep mode. The internal RC oscillator is selected by setting the ADRC bit (ADCON3<7>). When the ADRC bit is set, the ADCS<5:0> bits have no effect on the A/D operation.
Page 443 CH0SB<3:0>, will still select the alternating input. When the input selections are programmed in this manner, the input will alternate between a set of scanning inputs specified by the ADCSSL register and a fixed input specified by the CH0SB bits. © 2004 Microchip Technology Inc. DS70065C-page 18-13...
Page 444: Enabling The Module
The SSRC<2:0> bits (ADCON1<7:5>) select the source of the conversion trigger. Note: The available conversion trigger sources may vary depending on the dsPIC30F device variant. Please refer to the specific device data sheet for the available conversion trigger sources.
Page 445 SAMP bit includes the conversion time, as well as the sampling time. Figure 18-4: Converting 1 Channel, Automatic Sample Start, Manual Conversion Start ADCLK CONV CONV SAMP SAMP SAMP ADCBUF0 BSF ADCON1,ASAM BCF ADCON1,SAMP BCF ADCON1,SAMP Instruction Execution © 2004 Microchip Technology Inc. DS70065C-page 18-15...
Page 446 Family Reference Manual 18.11.2 Clocked Conversion Trigger When SSRC<2:0> = 111, the conversion trigger is under A/D clock control. The SAMC bits (ADCON3<12:8>) select the number of T clock cycles between the start of sampling and the start of conversion. After the start of sampling, the module will count a number of T clocks specified by the SAMC bits.
Page 447 PWM period. The special event trigger allows the user to minimize the delay between the time when A/D conversion results are acquired and the time when the duty cycle value is updated. Refer to Section 15. “Motor Control PWM” for more details. © 2004 Microchip Technology Inc. DS70065C-page 18-17...
Page 448 Family Reference Manual 18.11.3.4 Synchronizing A/D Operations to Internal or External Events The modes where an external event trigger pulse ends sampling and starts conversion (SSRC = 001, 010, 011) may be used in combination with auto sampling (ASAM = 1) to cause the A/D to synchronize the sample conversion events to the trigger pulse source.
Page 449: Controlling Sample/Conversion Operation
User software may attempt to read each A/D conversion result as it is generated, however, this might consume too much CPU time. Generally, to simplify the code, the module will fill the buffer with results and then generate an interrupt when the buffer is filled. © 2004 Microchip Technology Inc. DS70065C-page 18-19...
Page 450 Family Reference Manual 18.13.1 Number of Conversions per Interrupt The SMPI<3:0> bits (ADCON2<5:2>) will select how many A/D conversions will take place before the CPU is interrupted. This can vary from 1 sample per interrupt to 16 samples per interrupt.
Page 451: Conversion Sequence Examples
Figure 18-9: Converting One Channel 16 Times/Interrupt Conversion Trigger SAMP SAMP SAMP SAMP ADCLK CONV CONV CONV CONV Input to CH0 ASAM SAMP DONE ADCBUF0 ADCBUF1 ADCBUFE ADCBUFF ADIF Instruction Execution BSF ADCON1,ASAM © 2004 Microchip Technology Inc. DS70065C-page 18-21...
Page 452 Family Reference Manual Example 18-3: Sampling and Converting a Single Channel Multiple Times Code Example ADPCFG = 0xFFFB; // all PORTB = Digital; RB2 = analog ADCON1 = 0x00E0; // SSRC bit = 111 implies internal // counter ends sampling and starts // converting.
Page 453 AN0 sample 12 AN0 sample 28 ADCBUFC AN0 sample 13 AN0 sample 29 ADCBUFD AN0 sample 14 AN0 sample 30 ADCBUFE AN0 sample 15 AN0 sample 31 ADCBUFF AN0 sample 16 AN0 sample 32 © 2004 Microchip Technology Inc. DS70065C-page 18-23...
Page 454 Family Reference Manual 18.14.2 Example: A/D Conversions While Scanning Through All Analog Inputs Figure 18-10 and Table 18-2 illustrate a typical setup, where all available analog input channels are sampled and converted. The set CSCNA bit specifies scanning of the A/D inputs to the CH0 positive input.
Page 455 AN11 sample 12 AN11 sample 28 ADCBUFC AN12 sample 13 AN12 sample 29 ADCBUFD AN13 sample 14 AN13 sample 30 ADCBUFE AN14 sample 15 AN14 sample 31 ADCBUFF AN15 sample 16 AN15 sample 32 © 2004 Microchip Technology Inc. DS70065C-page 18-25...
Page 456: A/D Sampling Requirements
Family Reference Manual 18.14.3 Example: Using Dual 8-Word Buffers Refer to Subsection 17.15.4 in Section 17. “10-bit A/D Converter” for an example that uses dual buffers. 18.14.4 Example: Using Alternating MUX A, MUX B Input Selections See Subsection 17.15.5 in Section 17. “10-bit A/D Converter” for an example that uses the MUX A and MUX B input selections.
Page 457: Reading The A/D Result Buffer
1000 0000 0001 0000 = -2047 = 0.0002 = -0.9995 0/4096 0000 0000 0000 0000 0000 0000 0000 1111 1000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 = -2048 = 0.000 = -1.000 © 2004 Microchip Technology Inc. DS70065C-page 18-27...
Page 458: Transfer Function
Family Reference Manual 18.17 Transfer Function The ideal transfer function of the A/D converter is shown in Figure 18-13. The difference of the input voltages (V – V ), is compared to the reference (V REFH – V REFL...
Page 459: Initialization
; elapsed before starting conversion. BCLR ADCON1,#SAMP ; End A/D Sampling and start Conversion ; The DONE bit is set by hardware when conversion sequence is complete. ; The ADIF bit will be set. © 2004 Microchip Technology Inc. DS70065C-page 18-29...
Page 460: Operation During Sleep And Idle Modes
Family Reference Manual 18.21 Operation During Sleep and Idle Modes Sleep and Idle modes are useful for minimizing conversion noise because the digital activity of the CPU, buses and other peripherals is minimized. 18.21.1 CPU Sleep Mode Without RC A/D Clock When the device enters Sleep mode, all clock sources to the module are shutdown and stay at logic ‘0’.
Page 461 Section 18. 12-bit A/D Converter © 2004 Microchip Technology Inc. DS70065C-page 18-31...
Page 462: Design Tips
Family Reference Manual 18.24 Design Tips Question 1: How can I optimize the system performance of the A/D converter? Answer: Make sure you are meeting all of the timing specifications. If you are turning the module off and on, there is a minimum delay you must wait before taking a sample. If you are...
Page 463: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 464: Revision History
This is the initial released revision of this document. Revision B To reflect editorial and technical content revisions for the dsPIC30F 12-bit A/D Converter module. Revision C This revision incorporates all known errata at the time of this document update.
Page 465: Section 19. Uart
19.11 UART Operation During CPU Sleep and Idle Modes ..........19-21 19.12 Registers Associated with UART Module ..............19-22 19.13 Design Tips ........................ 19-23 19.14 Related Application Notes..................19-24 19.15 Revision History ......................19-25 © 2004 Microchip Technology Inc. DS70066C-page 19-1...
Page 466: Introduction
The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the dsPIC30F device family. The UART is a full-duplex asynchronous sys- tem that can communicate with peripheral devices, such as personal computers, RS-232 and RS-485 interfaces.
Page 467: Control Registers
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70066C-page 19-3...
Page 468 Family Reference Manual Register 19-2: STA: UART Status and Control Register Upper Byte: R/W-0 R/W-0 R/W-0 UTXISEL — — — UTXBRK UTXEN UTXBF TRMT bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/C-0 URXISEL<1:0> ADDEN RIDLE PERR FERR...
Page 469 U = Unimplemented bit, read as ‘0’ C = Bit can be cleared -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70066C-page 19-5...
Page 470 Family Reference Manual Register 19-3: RXREG: UART Receive Register Upper Byte: — — — — — — — URX8 bit 15 bit 8 Lower Byte: URX<7:0> bit 7 bit 0 bit 15-9 Unimplemented: Read as ‘0’ bit 8 URX8: Data bit 8 of the Received Character (in 9-bit mode) bit 7-0 URX<7:0>: Data bits 7-0 of the Received Character...
Page 471 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70066C-page 19-7...
Page 472: Uart Baud Rate Generator (Brg)
Family Reference Manual 19.3 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit baud rate generator. The UxBRG register controls the period of a free running 16-bit timer. Equation 19-1 shows the formula for computation of the baud rate.
Page 473 +0.2 2.4038 +0.2 2.4038 +0.2 9.4697 -1.4 9.6154 +0.2 19.2 19.5313 +1.7 19.2308 +0.2 19.2 19.2 38.4 39.0625 +1.7 38.4 38.4 MIN. 0.005 65535 0.004 65535 0.003 65535 0.002 65535 MAX. 312.5 115.2 © 2004 Microchip Technology Inc. DS70066C-page 19-9...
Page 474: Uart Configuration
19.4.3 Alternate UART I/O Pins Some dsPIC30F devices have an alternate set of UART transmit and receive pins that can be used for communications. The alternate UART pins are useful when the primary UART pins are shared by other peripherals. The alternate I/O pins are enabled by setting the ALTIO bit (UxMODE<10>).
Page 475: Uart Transmitter
UTX9 bit (UxTXREG<8>). A word write should be performed to UxTXREG so that all nine bits are written at the same time. Note: There is no parity in the case of 9-bit data transmission. © 2004 Microchip Technology Inc. DS70066C-page 19-11...
Page 476 Family Reference Manual 19.5.1 Transmit Buffer (UxTXB) Each UART has a 4-deep, 9-bit wide FIFO transmit data buffer. The UxTXREG register provides user access to the next available buffer location. The user may write up to 4 words in the buffer.
Page 477 (UTXISEL = 0) UxTXIF Cleared by User in Software UxTXIF (UTXISEL = 1) Character 1 to Character 2 to Transmit Shift Reg. Transmit Shift Reg. TRMT bit Note: This timing diagram shows two consecutive transmissions. © 2004 Microchip Technology Inc. DS70066C-page 19-13...
Page 478: Uart Receiver
Family Reference Manual 19.5.4 Transmission of Break Characters Setting the UTXBRK bit (UxSTA<11>) will force the UxTX line to ‘0’. UTXBRK overrides any other transmitter activity. The user should wait for the transmitter to be Idle (TRMT = 1) before setting UTXBRK.
Page 479 This bit is set as long as there is at least one character to be read from the receive buffer. URXDA is a read only bit. Figure 19-5 shows a block diagram of the UART receiver. © 2004 Microchip Technology Inc. DS70066C-page 19-15...
Page 480 Family Reference Manual Figure 19-5: UART Receiver Block Diagram Internal Data Bus Word or Word Read Only Byte Read UxMODE UxSTA URX8 UxRXREG Low Byte Receive Buffer Control – Generate Flags – Generate Interrupt – Shift Data Characters UxRXIF...
Page 481 Note: This diagram shows 6 characters received without the user reading the input buffer. The 5th character received is held in the receive shift register. An overrun error occurs at the start of the 6th character. © 2004 Microchip Technology Inc. DS70066C-page 19-17...
Page 482: Using The Uart For 9-Bit Communication
Family Reference Manual 19.7 Using the UART for 9-bit Communication A typical multi-processor communication protocol will differentiate between data bytes and address/control bytes. A common scheme is to use a 9th data bit to identify whether a data byte is address or data information.
Page 483: Receiving Break Characters
Start bit. Break is regarded as a character containing all ‘0’s with the FERR bit set. The break character is loaded into the buffer. No further reception can occur until a Stop bit is received. Note that RIDLE goes high when the Stop bit has been received. © 2004 Microchip Technology Inc. DS70066C-page 19-19...
Page 484: Initialization
Family Reference Manual 19.9 Initialization Example 19-2 is an initialization routine for the Transmitter/Receiver in 8-bit mode. Example 19-3 shows an initialization of the Addressable UART in 9-bit Address Detect mode. In both examples, the value to load into the UxBRG register is dependent on the desired baud rate and the device frequency.
Page 485: Other Features Of The Uart
Idle mode, or whether the module will continue normal operation in Idle mode. If USIDL = 0, the module will continue normal operation during Idle mode. If USIDL = 1, the module will stop in Idle mode. Any transmission or reception in progress will be aborted. © 2004 Microchip Technology Inc. DS70066C-page 19-21...
Page 486 Family Reference Manual DS70066C-page 19-22 © 2004 Microchip Technology Inc.
Page 487: Design Tips
What are the possible causes? Answer: Ensure the following control bits have been setup correctly: • UxBRG: UART Baud Rate register • PDSEL<1:0>: Parity and Data Size Selection bits • STSEL: Stop bit Selection © 2004 Microchip Technology Inc. DS70066C-page 19-23...
Page 488: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 489: Revision History
This is the initial released revision of this document. Revision B Revision B has been expanded to include a full description of the dsPIC30F UART module. Revision C This revision incorporates all known errata at the time of this document update.
Page 490 Family Reference Manual NOTES: DS70066C-page 19-26 © 2004 Microchip Technology Inc.
Page 491: Section 20. Serial Peripheral Interface (Spi™)
20.4 SPI Master Mode Clock Frequency ................20-19 20.5 Operation in Power Save Modes ................20-20 20.6 Special Function Registers Associated with SPI Modules ......... 20-22 20.7 Related Application Notes..................20-23 20.8 Revision History ......................20-24 © 2004 Microchip Technology Inc. DS70067C-page 20-1...
Page 492: Introduction
Motorola's SPI and SIOP interfaces. Depending on the variant, the dsPIC30F family offers one or two SPI modules on a single device. SPI1 and SPI2 are functionally identical. The SPI2 module is available in many of the higher pin count packages (64-pin and higher), while the SPI1 module is available on all devices.
Page 493 Frame Control Select Sync Control Secondary Primary Prescaler Prescaler 1:1 → 1:8 1, 4, 16, 64 SCKx Enable Master Clock Note: The SPIxTXB and SPIxRXB registers are memory mapped to the SPIxBUF register. © 2004 Microchip Technology Inc. DS70067C-page 20-3...
Page 494: Status And Control Registers
Family Reference Manual 20.2 Status and Control Registers Register 20-2: SPIxSTAT: SPI Status and Control Register Upper Byte: R/W-0 R/W-0 SPIEN — SPISIDL — — — — — bit 15 bit 8 Lower Byte: R/W-0 — SPIROV — —...
Page 495 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode © 2004 Microchip Technology Inc. DS70067C-page 20-5...
Page 496 Family Reference Manual Register 20-2: CON: SPIx Control Register (Continued) bit 4-2 SPRE<2:0>: Secondary Prescale (Master Mode) bits (Supported settings: 1:1, 2:1 through 8:1, all inclusive) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 000 = Secondary prescale 8:1 bit 1-0 PPRE<1:0>: Primary Prescale (Master Mode) bits...
Page 497: Modes Of Operation
Note 1: Using the SSx pin in Slave mode of operation is optional. 2: User must write transmit data to/read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. © 2004 Microchip Technology Inc. DS70067C-page 20-7...
Page 498 Family Reference Manual 20.3.2.1 Master Mode The following steps should be taken to set up the SPI module for the Master mode of operation: If using interrupts: • Clear the SPIxIF bit in the respective IFSn register. • Set the SPIxIE bit in the respective IECn register.
Page 499 Only one of the two configurations of the SMP bit can be chosen during operation. 3: If there are no pending transmissions, SPIxTXB is transferred to SPIxSR as soon as the user writes to SPIxBUF. 4: Operation for 8-bit mode shown. The 16-bit mode is similar. © 2004 Microchip Technology Inc. DS70067C-page 20-9...
Page 500 Family Reference Manual 20.3.2.2 Slave Mode The following steps should be taken to set up the SPI module for the Slave mode of operation: Clear the SPIxBUF register. If using interrupts: • Clear the SPIxIF bit in the respective IFSn register.
Page 501 2: If there are no pending transmissions or a transmission in progress, SPIxBUF is transferred to SPIxSR as soon as the user writes to SPIxBUF. 3: Operation for 8-bit mode shown. The 16-bit mode is similar. © 2004 Microchip Technology Inc. DS70067C-page 20-11...
Page 502 Family Reference Manual Figure 20-5: SPI Slave Mode Operation with Slave Select Pin Enabled SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) User writes SPIxBUF SPIxBUF SPIxSR SPITBF bit6 bit2 SDOx bit7 bit5...
Page 503 2: When the SSEN (SPIxCON<7>) bit is set to ‘1’, the SSx pin must be driven low so as to enable transmission and reception in Slave mode. 3: Transmit data is held in SPIxTXB and SPITBF remains set until all bits are transmitted. 4: Operation for 8-bit mode shown. The 16-bit mode is similar. © 2004 Microchip Technology Inc. DS70067C-page 20-13...
Page 504 Family Reference Manual 20.3.3 SPI Error Handling When a new data word has been shifted into SPIxSR and the previous contents of SPIxRXB have not been read by the user software, the SPIROV bit (SPIxSTAT<6>) will be set. The module will not transfer the received data from SPIxSR to SPIxRXB.
Page 505 Section 20. Serial Peripheral Interface (SPI) Figure 20-7: SPI Master, Frame Master Connection Diagram dsPIC30F [SPI Master, Frame Master] PROCESSOR 2 SDOx SDIx Serial Receive Buffer Serial Receive Buffer (SPIxRXB) (SPIxRXB) SDIx SDOx Shift Register Shift Register (SPIxSR) (SPIxSR) MSbit...
Page 506 Family Reference Manual 20.3.5.2 SPIx Buffers in Framed SPI Modes When SPIFSD (SPIxCON<13>) = 0, the SPIx module is in the Frame Master mode of operation. In this mode, the frame sync pulse is initiated by the module when the user software writes the transmit data to SPIxBUF location (thus writing the SPIxTXB register with transmit data).
Page 507 Note 1: In Framed SPI modes, the SSx pin is used to transmit/receive the frame synchronization pulse. 2: Framed SPI modes require the use of all four pins (i.e., Using the SSx pin is not optional). © 2004 Microchip Technology Inc. DS70067C-page 20-17...
Page 508 Family Reference Manual 20.3.5.5 SPI Slave Mode and Frame Master Mode This framed SPI mode is enabled by setting the MSTEN (SPIxCON<5>) bit to ‘0’, the FRMEN (SPIxCON<14>) bit to ‘1’ and the SPIFSD (SPIxCON<13>) bit to ‘0’. The input SPI clock will be continuous in Slave mode.
Page 509: Spi Master Mode Clock Frequency
2500 1250 1250 16:1 64:1 Note: SCKx frequencies shown in kHz. Note: Not all clock rates are supported. For further information, refer to the SPI timing specifications in the specific device data sheet. © 2004 Microchip Technology Inc. DS70067C-page 20-19...
Page 510: Operation In Power Save Modes
• Power Save modes: These are invoked by the execution of the PWRSAV instruction. There are two Power Save modes supported in the dsPIC30F family of devices. These are specified in the PWRSAV instruction via a parameter. The two modes are: - Sleep mode: Device clock source and entire device is shut down.
Page 511 2) Used as Frame Sync I/O Pulse when FRMEN and SPIFSD (SPI2CON<14:13>) are set to ‘11’ or ‘10’. Legend: CMOS = CMOS compatible input or output, ST = Schmitt Trigger input with CMOS levels, I = Input, O = Output © 2004 Microchip Technology Inc. DS70067C-page 20-21...
Page 512 Family Reference Manual DS70067C-page 20-22 © 2004 Microchip Technology Inc.
Page 513: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 514: Revision History
Revision A This is the initial released revision of this document. Revision B This revision reflects editorial and technical content changes for the dsPIC30F Serial Peripheral Interface (SPI) module. Revision C There were no technical content revisions to this section of the manual, however, this section was updated to reflect Revision C throughout the manual.
Page 515: Section 21. Inter-Integrated Circuit™ (I2C™)
C Bus ..............21-47 21.9 Module Operation During PWRSAV Instruction ............21-49 21.10 Effects of a Reset....................... 21-49 21.11 Design Tips ........................ 21-50 21.12 Related Application Notes..................21-51 21.13 Revision History ......................21-52 © 2004 Microchip Technology Inc. DS70068C-page 21-1...
Page 516: Overview
• Where the dsPIC30F acts as a Slave Device • Where the dsPIC30F acts as a Master Device in a Single Master System (Slave may also be active) • Where the dsPIC30F acts as a Master/Slave Device in a Multi-Master System...
Page 517 Start and Stop bit Detect Write Start and Stop bit Generate Read Collision Detect Write Acknowledge Read Generation Clock Stretching Write I2CTRN Shift Read Clock Reload Control Write I2CBRG BRG Down Counter Read © 2004 Microchip Technology Inc. DS70068C-page 21-3...
Page 518: I 2 C Bus Characteristics
The I C bus is a two-wire serial interface. Figure 21-2 is a schematic of a typical I C connection between the dsPIC30F device and a 24LC256 I C serial EEPROM. The I C interface employs a comprehensive protocol to ensure reliable transmission and reception of data.
Page 519 Both data and clock lines remain HIGH at those times after a Stop condition and before a Start condition. Figure 21-3: C Bus Protocol States (A) or (N) NACK Start Data or Data Stop ACK/NACK Address Condition Allowed Condition Valid Valid to Change © 2004 Microchip Technology Inc. DS70068C-page 21-5...
Page 520 C message is shown in Figure 21-4. In this example, the message will read a specified byte from a 24LC256 I C serial EEPROM. The dsPIC30F device will act as the master and the 24LC256 device will act as the slave.
Page 521: Control And Status Registers
I2CTRN (8 bits) Bit 7 Bit 0 I2CBRG (9 bits) Bit 8 Bit 0 I2CCON (16 bits) Bit 15 Bit 0 I2CSTAT (16 bits) Bit 15 Bit 0 I2CADD (10 bits) Bit 9 Bit 0 © 2004 Microchip Technology Inc. DS70068C-page 21-7...
Page 522 Family Reference Manual Register 21-2 and Register 21-2 define the I C module Control and Status registers, I2CCON and I2CSTAT. The I2CTRN is the register to which transmit data is written. This register is used when the module operates as a master transmitting data to the slave or as a slave sending reply data to the master.
Page 523 ACKDT: Acknowledge Data bit (When operating as I C Master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during acknowledge 0 = Send ACK during acknowledge © 2004 Microchip Technology Inc. DS70068C-page 21-9...
Page 524 Family Reference Manual Register 21-1: I2CCON: I C Control Register (Continued) bit 4 ACKEN: Acknowledge Sequence Enable bit (When operating as I C master. Applicable during master receive.) 1 = Initiate Acknowledge sequence on SDA and SCL pins, and transmit ACKDT data bit Hardware clear at end of master Acknowledge sequence.
Page 525 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by write to I2CTRN or by reception of slave byte. © 2004 Microchip Technology Inc. DS70068C-page 21-11...
Page 526 Family Reference Manual Register 21-2: I2CSTAT: I C Status Register (Continued) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected.
Page 527: Enabling I 2 C Operation
The slave interrupt is called SI2CIF and is activated on detection of a message directed to the slave. • Detection of a valid device address (including general call) • Request to transmit data • Reception of data © 2004 Microchip Technology Inc. DS70068C-page 21-13...
Page 528 Family Reference Manual 21.4.3 Setting Baud Rate when Operating as a Bus Master When operating as an I C master, the module must generate the system SCL clock. Generally, C system clocks are specified to be either 100 kHz, 400 kHz or 1 MHz. The system clock rate is specified as the minimum SCL low time plus the minimum SCL high time.
Page 529: Communicating As A Master In A Single Master Environment
C serial memory. In an I C system, the master controls the sequence of all data communication on the bus. In this example, the dsPIC30F and its I C module have the role of the single master in the system. As the single master, it is responsible for generating the SCL clock and controlling the message protocol.
Page 530 Family Reference Manual 21.5.1 Generating Start Bus Event To initiate a Start event, the software sets the Start enable bit, SEN (I2CCON<0>). Prior to setting the Start bit, the software can check the P (I2CSTAT<4>) status bit to ensure that the bus is in an Idle state.
Page 531 Idle state until the next data byte is loaded into I2CTRN. 21.5.2.4 ACKSTAT Status Flag The ACKSTAT bit (I2CCON<15>) is cleared when the slave has sent an Acknowledge (ACK = 0), and is set when the slave does not Acknowledge (ACK = 1). © 2004 Microchip Technology Inc. DS70068C-page 21-17...
Page 532 Family Reference Manual 21.5.2.5 TBF Status Flag When transmitting, the TBF bit (I2CSTAT<0>) is set when the CPU writes to I2CTRN and is cleared when all 8 bits are shifted out. 21.5.2.6 IWCOL Status Flag If the software writes the I2CTRN when a transmit is already in progress (i.e., the module is still shifting out a data byte), then IWCOL is set and the contents of the buffer are unchanged (the write doesn’t occur).
Page 533 IWCOL bit is set and the contents of the buffer are unchanged (the write doesn’t occur). Note: Since queueing of events is not allowed, writing to the lower 5 bits of I2CCON is disabled until the data reception condition is complete. © 2004 Microchip Technology Inc. DS70068C-page 21-19...
Page 534 Family Reference Manual Figure 21-10: Master Reception Timing Diagram RCEN I2C Bus State (D) (Q) SCL (Master) SCL (Slave) SDA (Master) SDA (Slave) I2CRCV MI2CIF Interrupt - Typically, the slave can pull SCL low (clock stretch) to request a wait to prepare data response.
Page 535 - Baud generator times out. Module releases SCL. Baud generator restarts. SDA (Master) - Baud generator times out. MI2CIF Interrupt Module drives SCL low then releases SDA. Module clears ACKEN. Master generates interrupt. © 2004 Microchip Technology Inc. DS70068C-page 21-21...
Page 536 Family Reference Manual 21.5.5 Generating Stop Bus Event Setting the Stop sequence enable bit, PEN (I2CCON<2>), enables generation of a master Stop sequence. Note: The lower 5 bits of I2CCON must be ‘0’ (master logic inactive) before attempting to set the PEN bit.
Page 537 Baud generator restarts. - Slave logic detects Start. Module sets S = 1, P = 0. - The baud generator times out. Module drives SCL low. MI2CIF Interrupt Module clears RSEN. Master generates interrupt. © 2004 Microchip Technology Inc. DS70068C-page 21-23...
Page 538 Family Reference Manual 21.5.7 Building Complete Master Messages As described at the beginning of Section 21.5, the software is responsible for constructing messages with the correct message protocol. The module controls individual portions of the I message protocol, however, sequencing of the components of the protocol to construct a complete message is a software task.
Page 539 Section 21. Inter-Integrated Circuit (I © 2004 Microchip Technology Inc. DS70068C-page 21-25...
Page 540 Family Reference Manual DS70068C-page 21-26 © 2004 Microchip Technology Inc.
Page 541 Section 21. Inter-Integrated Circuit (I © 2004 Microchip Technology Inc. DS70068C-page 21-27...
Page 542 Family Reference Manual DS70068C-page 21-28 © 2004 Microchip Technology Inc.
Page 543: Communicating As A Master In A Multi-Master Environment
- At what would be the master baud counter rollover, detecting SCL low holds counter. - Logic samples SCL once per T . Logic detects SCL high. - The baud counter rollover occurs on next cycle. - On next rollover, the master SCL will transition. © 2004 Microchip Technology Inc. DS70068C-page 21-29...
Page 544 Family Reference Manual 21.6.3 Bus Arbitration and Bus Collision Bus arbitration supports multi-master system operation. The wired-and nature of the SDA line permits arbitration. Arbitration takes place when the first master outputs a ‘1’ on SDA by letting SDA float high and, simultaneously, the second master outputs a ‘0’...
Page 545 If the master software loses track of the state of the I C bus, there are conditions which cause a bus collision during a Stop condition. In this case, the master generating the Stop condition will lose arbitration and generate a bus collision interrupt. © 2004 Microchip Technology Inc. DS70068C-page 21-31...
Page 546: Communicating As A Slave
In some systems, particularly where multiple processors communicate with each other, the dsPIC30F device may communicate as a slave (see Figure 21-21). When the module is enabled, the slave module is active. The slave may not initiate a message, it can only respond to a message sequence initiated by a master.
Page 547 SDA (Slave) - Address match of first byte clears D_A bit. Slave generates ACK. SI2CIF Interrupt - R_W bit cleared. Slave generates interrupt. - Bus waiting. Slave ready to receive data. ADD10 SCLREL © 2004 Microchip Technology Inc. DS70068C-page 21-33...
Page 548 Family Reference Manual 21.7.3.2 7-bit Address and Slave Read When a slave read is specified by having R/W = 1 in a 7-bit address byte, the process of detecting the device address is similar to that for a slave write (see Figure 21-23). If the addresses match, the following events occur: An ACK is generated.
Page 549 - Address match of first and second byte sets ADD10 and causes slave logic to generate ACK. - Reception of second byte completes 10-bit address. Slave logic generates interrupt. - Bus waiting. Slave ready to receive data. © 2004 Microchip Technology Inc. DS70068C-page 21-35...
Page 550 Family Reference Manual 21.7.3.4 General Call Operation The addressing procedure for the I C bus is such that the first byte after a Start condition usually determines which slave device the master is addressing. The exception is the general call address, which can address all devices.
Page 551 A slave interrupt is generated. Software may check the status of the I2CSTAT register to determine the cause of the event and then clear the SI2CIF flag. The module will wait for the next data byte. © 2004 Microchip Technology Inc. DS70068C-page 21-37...
Page 552 Family Reference Manual 21.7.4.1 Acknowledge Generation Normally, the slave module will Acknowledge all received bytes by sending an ACK on the ninth SCL clock. If the receive buffer is overrun, the slave module does not generate this ACK. Overrun is indicated if either (or both): The buffer full bit, RBF (I2CSTAT<1>), was set before the transfer was received.
Page 553 SCLREL bit, the module will pull the SCL line low after it detects the bus SCL low. The SCL line will remain low, suspending transactions on the bus until the SCLREL bit is set. © 2004 Microchip Technology Inc. DS70068C-page 21-39...
Page 554 Family Reference Manual DS70068C-page 21-40 © 2004 Microchip Technology Inc.
Page 555 Section 21. Inter-Integrated Circuit (I © 2004 Microchip Technology Inc. DS70068C-page 21-41...
Page 556 Family Reference Manual DS70068C-page 21-42 © 2004 Microchip Technology Inc.
Page 557 Section 21. Inter-Integrated Circuit (I © 2004 Microchip Technology Inc. DS70068C-page 21-43...
Page 558 Family Reference Manual 21.7.5 Sending Data to a Master Device When the R/W bit of the incoming device address byte is one and an address match occurs, the R_W bit (I2CSTAT<2>) is set. At this point, the master device is expecting the slave to respond by sending a byte of data.
Page 559 Section 21. Inter-Integrated Circuit (I © 2004 Microchip Technology Inc. DS70068C-page 21-45...
Page 560 Family Reference Manual DS70068C-page 21-46 © 2004 Microchip Technology Inc.
Page 561: Connection Considerations For I
C Bus + 10% Device = 10 - 400 pF Note: C devices with input levels related to V must have one common supply line to which the pull-up resistor is also connected. © 2004 Microchip Technology Inc. DS70068C-page 21-47...
Page 562 Family Reference Manual 21.8.1 Integrated Signal Conditioning The SCL and SDA pins have an input glitch filter. The I C bus requires this filter in both the 100 kHz and 400 kHz systems. When operating on a 400 kHz bus, the I C specification requires a slew rate control of the device pin output.
Page 563: Module Operation During Pwrsav Instruction
I2CCON and I2CSTAT for the Reset conditions of those registers. Note: In this discussion, ‘Idle’ refers to the CPU power saving state. The lower-case ‘idle’ refers to the time when the I C module is not transferring data on the bus. © 2004 Microchip Technology Inc. DS70068C-page 21-49...
Page 564: Design Tips
Family Reference Manual 21.11 Design Tips Question 1: I’m operating as a bus master and transmitting data, however, slave and receive interrupts are also occurring. Answer: The master and slave circuits are independent. The slave module will receive events from the bus sent by the master.
Page 565: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 566: Revision History
Revision History Revision A This is the initial released revision of this document. Revision B This revision has been expanded to contain a full description of the dsPIC30F Inter-Integrated Circuit (I C) module. Revision C This revision incorporates all known errata at the time of this document update.
Page 567: Section 22. Data Converter Interface (Dci)
22.5 Using the DCI Module....................22-17 22.6 Operation in Power Saving Modes ................22-28 22.7 Registers Associated with DCI................... 22-28 22.8 Design Tips ........................ 22-30 22.9 Related Application Notes..................22-31 22.10 Revision History ......................22-32 © 2004 Microchip Technology Inc. DS70069C-page 22-1...
Page 568: Introduction
The data word length for the DCI is programmable up to 16 bits to match the data size of the dsPIC30F CPU. However, many codecs have data word sizes greater than 16 bits. Long data word lengths can be supported by the DCI. The DCI is configured to transmit/receive the long word in multiple 16-bit time slots.
Page 569 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70069C-page 22-3...
Page 570 Family Reference Manual Register 22-2: DCICON2 Upper Byte: R/W-0 R/W-0 R/W-0 — — — — BLEN<1:0> — COFSG3 bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 COFSG<2:0> — WS<3:0> bit 7 bit 0 bit 15-12 Reserved: Read as ‘0’...
Page 571 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70069C-page 22-5...
Page 572 Family Reference Manual Register 22-4: DCISTAT Upper Byte: — — — — SLOT<3:0> bit 15 bit 8 Lower Byte: — — — — RFUL TUNF TMPTY bit 7 bit 0 bit 15-12 Reserved: Read as ‘0’ bit 11-8 SLOT<3:0>: DCI Slot Status bits...
Page 573 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70069C-page 22-7...
Page 574: Codec Interface Basics And Terminology
Family Reference Manual 22.3 Codec Interface Basics and Terminology The interface protocols supported by the DCI require the use of a Frame Synchronization (FS) signal to initiate a data transfer between two devices. In most cases, the rising edge of FS starts a new data transfer.
Page 575 FSO signal at the end of the transfer. The FSO signal begins the transfer of the second data word from the second device in the chain. Figure 22-3: DAISY-CHAINED DATA TRANSFER EXAMPLE Data Frame Period (1/fs) SDI or SDO Time Slot 0 Time Slot 1 © 2004 Microchip Technology Inc. DS70069C-page 22-9...
Page 576: Dci Operation
Family Reference Manual The FS pulse has a minimum active time of one SCK period so the slave device can detect the start of the data frame. The duty cycle of the FS pulse may vary depending on the specific pro- tocol that is used to mark certain boundaries in the data frame.
Page 577 CSCKD control bit, DCICON1<10>. When the CSCK pin is configured as an output (CSCKD = 0), the serial clock is derived from the dsPIC30F system clock source and supplied to external devices by the DCI. When the CSCK pin is configured as an input (CSCKD = 1), the serial clock must be provided by an external device.
Page 578 Family Reference Manual 22.4.3 Bit Clock Generator The DCI module has a dedicated 12-bit time base that produces the bit clock. The bit clock rate (period) is set by writing a non-zero 12-bit value to the BCG<11:0> control bits (DCICON3<11:0>).
Page 579 The DCI buffer control unit always accesses the same relative location in the Transmit and Receive buffers. If the DCI is transmitting data from TXBUF3, for example, then any data received during that time slot will be written to RXBUF3. © 2004 Microchip Technology Inc. DS70069C-page 22-13...
Page 580 If the CSDOM bit is set, the CSDO pin will be tri-stated during unused time slot periods. This mode allows multiple dsPIC30F devices to share the same CSDO line in a multiplexed application. Each device on the CSDO line is configured so that it will only transmit data during specific time slots.
Page 581 RXBUF register location is not read by the user software before new data is transferred from the buffer memory. When a receive overflow occurs, the old contents of the register are overwritten. The ROV status bit is cleared automatically when the register that caused the overflow is read. © 2004 Microchip Technology Inc. DS70069C-page 22-15...
Page 582 Family Reference Manual 22.4.14 Transmit Status Bits There are two transmit status bits, TMPTY and TUNF. The transmit status bits only indicate status for register locations that are used by the module. If the buffer length is set to less than four words, for example, the unused register locations will not affect the transmit status bits.
Page 583: Using The Dci Module
The DCIIF status bit (IFS2<9>) is set each time a DCI buffer transfer takes place and generates a CPU interrupt, if enabled. The DCIIF status bit is generated by the logical ORing of the RFUL and TMPTY status bits. © 2004 Microchip Technology Inc. DS70069C-page 22-17...
Page 584 Family Reference Manual 22.5.1.1 DCI Start-up and Data Buffering Data transfers are begun by setting the DCIEN control bit (DCICON1<15>). Prior to this, the DCI Control registers should have been initialized for the desired operating mode. (See Section 22.5.4 “Multi-Channel Operation”, Section 22.5.5 “I...
Page 585 Figure 22-8: DCI Timing, Module Disable FS pulse not generated. WS = 0011b COFSG = 0011b CSCK Data COFS DCIEN SLOT 0011 0000 0001 0010 0011 0000 RFUL Receive buffer contents transferred to RXBUF. © 2004 Microchip Technology Inc. DS70069C-page 22-19...
Page 586 Family Reference Manual 22.5.2 Master vs. Slave Operation The DCI can be configured for master or slave operation. The master device generates the frame sync signal to initiate a data transfer. The Operating mode (master or slave) is selected by the COFSD control bit (DCICON1<8>).
Page 587 Write the WS<3:0> control bits (DCICON2<3:0>) for the desired data word size. The example codec requires WS<3:0> = 1111b for a 16-bit data word size. © 2004 Microchip Technology Inc. DS70069C-page 22-21...
Page 588 Family Reference Manual Write the COFSG<3:0> control bits (DCICON2<8:5>) for the desired number of data words per frame. The WS and COFSG control bits will determine the length of the data frame in CSCK cycles (see Section 22.4.7 “Frame Synchronization Generator”) COFSG<3:0>...
Page 589 13. Begin operation as described in Section 22.5.1.1 “DCI Start-up and Data Buffering”. In the I S Master mode, the COFS pin will be driven high after the module is enabled and begin transmitting the data loaded in TXBUF0. © 2004 Microchip Technology Inc. DS70069C-page 22-23...
Page 590 Family Reference Manual 22.5.5.2 How to Determine the I S Channel Alignment Most I S codecs support two channels of data and the level of the frame sync signal indicates the channel that is transferred during that half of the data frame. The COFS pin can be polled in software using its associated Port register to determine the present level on the pin in the DCI Interrupt Service Routine.
Page 591 CSCK. The control and data time slots in the AC-Link have defined uses in the ® protocol as shown in Figure 22-15. Refer to the Appendix of this manual or the Intel AC ‘97 Codec Specification, Rev 2.2 for a complete definition of the AC-Link protocol. © 2004 Microchip Technology Inc. DS70069C-page 22-25...
Page 592 Family Reference Manual Figure 22-14: AC-Link Signal Connections BIT_CLK CSCK 24.576 SYNC COFS ® dsPIC SDATA_OUT AC ‘97 CSDO (AC ‘97 Controller) Codec SDATA_IN CSDI /RESET Figure 22-15: AC-Link Data Frame SYNC Slot 3 Slot 4 Slot 10 Slot 11...
Page 593 The word size selection bits (WS<3:0>) and the frame synchronization generator bits (COFSG<3:0>) have no effect for the 16- and 20-bit AC-Link modes, since the frame and word sizes are set by the protocol. © 2004 Microchip Technology Inc. DS70069C-page 22-27...
Page 594: Operation In Power Saving Modes
Family Reference Manual Clear the CSDOM control bit (DCICON1<6>). Write the TSCON and RSCON registers to determine which data time slots in the frame are to be transmitted and received, respectively. This will depend on which data time slots in the AC-Link protocol will be used.
Page 595 Section 22. Data Converter Interface (DCI) © 2004 Microchip Technology Inc. DS70069C-page 22-29...
Page 596: Design Tips
Family Reference Manual 22.8 Design Tips Question 1: Can the DCI support data word lengths greater than 16-bits? Answer: Yes. A long data word can be transmitted and received using multiple Transmit and Receive registers. See Section 22.5.3 “Data Packing for Long Data Word Support” for details.
Page 597: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 598: Revision History
Revision A This is the initial released revision of this document. Revision B This revision incorporates additional technical content and changes for the dsPIC30F Data Converter Interface (DCI) module. Revision C This revision incorporates all known errata at the time of this document update.
Page 599: Section 23. Can Module
23.11 Time-stamping ......................23-65 23.12 CAN Module I/O......................23-65 23.13 Operation in CPU Power Saving Modes..............23-66 23.14 CAN Protocol Overview ..................... 23-68 23.15 Related Application Notes..................23-72 23.16 Revision History ......................23-73 © 2004 Microchip Technology Inc. DS70070B-page 23-1...
Page 600: Introduction
Family Reference Manual 23.1 Introduction The Controller Area Network (CAN) module is a serial interface useful for communicating with other peripherals or microcontroller devices. This interface/protocol was designed to allow communications within noisy environments. Figure 23-1 shows an example CAN bus network.
Page 601 000 = Set Normal Operation mode bit 7-5 OPMODE<2:0>: Operation Mode bits Note: These bits indicate the current Operating mode of the CAN module. See description for REQOP bits (CiCTRL<10:8>). bit 4 Unimplemented: Read as ‘0’ © 2004 Microchip Technology Inc. DS70070B-page 23-3...
Page 602 Family Reference Manual Register 23-1: CiCTRL: CAN Module Control and Status Register (Continued) bit 3-1 ICODE<2:0>: Interrupt Flag Code bits 111 = Wake-up interrupt 110 = RXB0 interrupt 101 = RXB1 interrupt 100 = TXB0 interrupt 011 = TXB1 interrupt...
Page 603 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70070B-page 23-5...
Page 604 Family Reference Manual Register 23-3: CiTXnSID: Transmit Buffer n Standard Identifier Upper Byte: R/W-x R/W-x R/W-x R/W-x R/W-x SID<10:6> — — — bit 15 bit 8 Lower Byte: R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID<5:0> TXIDE bit 7 bit 0 bit 15-11 SID<10:6>: Standard Identifier bits...
Page 605 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70070B-page 23-7...
Page 606 Family Reference Manual 23.2.3 CAN Receive Buffer Registers This subsection shows the Receive buffer registers with their associated control registers. Register 23-7: CiRX0CON: Receive Buffer 0 Status and Control Register Upper Byte: — — — — — — —...
Page 607 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70070B-page 23-9...
Page 608 Family Reference Manual Register 23-9: CiRXnSID: Receive Buffer n Standard Identifier Upper Byte: R/W-x R/W-x R/W-x R/W-x R/W-x — — — SID<10:6> bit 15 bit 8 Lower Byte: R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x SID<5:0> RXIDE bit 7 bit 0 bit 15-13 Unimplemented: Read as ‘0’...
Page 609 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70070B-page 23-11...
Page 610 Family Reference Manual 23.2.4 Message Acceptance Filters This subsection describes the Message Acceptance filters. Register 23-13: CiRXFnSID: Acceptance Filter n Standard Identifier Upper Byte: R/W-x R/W-x R/W-x R/W-x R/W-x — — — SID<10:6> bit 15 bit 8 Lower Byte:...
Page 611 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70070B-page 23-13...
Page 612 Family Reference Manual 23.2.5 Acceptance Filter Mask Registers Register 23-16: CiRXMnSID: Acceptance Filter Mask n Standard Identifier Upper Byte: R/W-x R/W-x R/W-x R/W-x R/W-x — — — SID<10:6> bit 15 bit 8 Lower Byte: R/W-x R/W-x R/W-x R/W-x R/W-x...
Page 613 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70070B-page 23-15...
Page 614 Family Reference Manual 23.2.6 CAN Baud Rate Registers This subsection describes the CAN baud rate registers. Register 23-19: CiCFG1: Baud Rate Configuration Register 1 Upper Byte: — — — — — — — — bit 15 bit 8 Lower Byte:...
Page 615 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70070B-page 23-17...
Page 616 Family Reference Manual 23.2.7 CAN Module Error Count Register This subsection describes the CAN Module Transmission/Reception Error Count register. The various error status flags are present in the CAN Interrupt Flag Register. Register 23-21: CiEC: Transmit/Receive Error Count Upper Byte: TERRCNT<7:0>...
Page 617 R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70070B-page 23-19...
Page 618 Family Reference Manual Register 23-23: CiINTF: Interrupt Flag Register Upper Byte: R/C-0 R/C-0 RX0OVR RX1OVR TXBO TXEP RXEP TXWAR RXWAR EWARN bit 15 bit 8 Lower Byte: R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 IVRIF WAKIF ERRIF TX2IF...
Page 619 C = Bit can be cleared U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown © 2004 Microchip Technology Inc. DS70070B-page 23-21...
Page 620 Family Reference Manual DS70070B-page 23-22 © 2003 Microchip Technology Inc.
Page 621 Section 23. CAN © 2003 Microchip Technology Inc. DS70070B-page 23-23...
Page 622 Family Reference Manual DS70070B-page 23-24 © 2003 Microchip Technology Inc.
Page 623 Section 23. CAN © 2003 Microchip Technology Inc. DS70070B-page 23-25...
Page 624 Family Reference Manual DS70070B-page 23-26 © 2003 Microchip Technology Inc.
Page 625 Section 23. CAN © 2003 Microchip Technology Inc. DS70070B-page 23-27...
Page 626: Can Module Features
Family Reference Manual 23.3 CAN Module Features The CAN module is a communication controller implementing the CAN 2.0A/B protocol as defined in the BOSCH specification. The module will support CAN 1.2, CAN 2.0A, CAN 2.0B Passive and CAN 2.0B Active versions of the protocol. The module implementation is a Full CAN system.
Page 627: Can Module Implementation
ENGINE Transmit ErrPas Error BusOff Counter Transmit Shift Receive Shift Protocol Finite CRC Check CRC Generator State Machine Transmit Timing Bit Timing Logic Logic Generator CxTX CxRX Note: x = 1 or 2 © 2004 Microchip Technology Inc. DS70070B-page 23-29...
Page 628 Family Reference Manual 23.4.1 CAN Message Formats The CAN protocol engine handles all functions for receiving and transmitting messages on the CAN bus. Messages are transmitted by first loading the appropriate data registers. Status and errors can be checked by reading the appropriate registers. Any message detected on the CAN bus is checked for errors and then matched against filters to see if it should be received and stored in one of the two receive registers.
Page 629 Interframe Space before any other message is transmitted by that node. This time period is called the Suspend Transmit field. The Suspend Transmit field allows additional delay time for other transmitting nodes to take control of the bus. © 2004 Microchip Technology Inc. DS70070B-page 23-31...
Page 630 Family Reference Manual Figure 23-3: Standard Data Frame DS70070B-page 23-32 © 2004 Microchip Technology Inc.
Page 631 Section 23. CAN Figure 23-4: Extended Data Format © 2004 Microchip Technology Inc. DS70070B-page 23-33...
Page 632 Family Reference Manual Figure 23-5: Remote Data Frame DS70070B-page 23-34 © 2004 Microchip Technology Inc.
Page 633 Section 23. CAN Figure 23-6: Error Frame © 2004 Microchip Technology Inc. DS70070B-page 23-35...
Page 634: Can Module Operation Modes
Family Reference Manual 23.5 CAN Module Operation Modes The CAN Module can operate in one of several Operation modes selected by the user. These modes include: • Normal Operation mode • Disable mode • Loopback mode • Listen Only mode •...
Page 635 CAN bus. To use this, it is necessary that there are at least two further nodes that communicate with each other. The baud rate can be detected empirically by testing different values. This mode is also useful as a bus monitor without influencing the data traffic. © 2004 Microchip Technology Inc. DS70070B-page 23-37...
Page 636 Family Reference Manual 23.5.5 Configuration Mode In the Configuration mode, the module will not transmit or receive. The error counters are cleared and the interrupt flags remain unchanged. The programmer will have access to configuration registers that are access restricted in other modes.
Page 637: Message Reception
In the case of Receive Buffer 0, a limited number of Acceptance Filters can be used to enable a reception. A single bit, FILHIT0 (CiRX0CON<0>) determines which of the 2 filters, RXF0 or RXF1, enabled the message reception. © 2004 Microchip Technology Inc. DS70070B-page 23-39...
Page 638 Family Reference Manual 23.6.1.1 Receive Buffer Priority To provide flexibility, there are several acceptance filters corresponding to each receive buffer. There is also an implied priority to the receive buffers. RXB0 is the higher priority buffer and has 2 message acceptance filters associated with it. RXB1 is the lower priority buffer and has 4 acceptance filters associated with it.
Page 639 Go to Start Set FILHIT<2:0> according to which filter criteria was met Does Generate RXnIE = 1 RXnIE = 1 Interrupt Set ICODE<3:0> according to which receive buffer the message was loaded into © 2004 Microchip Technology Inc. DS70070B-page 23-41...
Page 640 Family Reference Manual 23.6.2 Message Acceptance Filters The message acceptance filters and masks are used to determine if a message in the message assembly buffer should be loaded into either of the receive buffers. Once a valid message has been received into the Message Assembly Buffer (MAB), the identifier fields of the message are compared to the filter values.
Page 641 Figure 23-10 shows a block diagram of the message acceptance filters. Figure 23-10: Message Acceptance Filter Acceptance Filter Register Acceptance Mask Register RXMn0 RXFn0 RxRqst RXMn1 RXFn1 RXMnn RXFnn Message Assembly Buffer Identifier © 2004 Microchip Technology Inc. DS70070B-page 23-43...
Page 642 Family Reference Manual 23.6.3 Receiver Overrun An overrun condition occurs when the Message Assembly Buffer (MAB) has assembled a valid received message, the message is accepted through the acceptance filters, and when the receive buffer associated with the filter has not been designated as clear of the previous message.
Page 643 Receive Error Counter was between 1 and 127. If the Receive Error Counter was ‘0’, it will stay ‘0’. If the Receive Error Counter was greater than 127, it will change to a value between 119 and 127. © 2004 Microchip Technology Inc. DS70070B-page 23-45...
Page 644 Family Reference Manual 23.6.6 Receive Interrupts Several Interrupts are linked to the message reception. The receive interrupts can be broken up into two separate groups: • Receive Error Interrupts • Receive interrupts 23.6.6.1 Receive Interrupt A message has been successfully received and loaded into one of the receive buffers. This inter- rupt is activated immediately after receiving the End-Of-Frame (EOF) field.
Page 645 Figure 23-11: Receive Buffer Interrupt Flag ACK DELIMITER ACK SIST BIT CRCDEL CRC0 CRC1 CRC2 CRC3 CRC4 CRC5 CRC6 CRC7 CRC8 CRC9 CRC10 CRC11 CRC12 CRC13 CRC14 DLC0 DLC1 STUFF DLC2 DLC3 ID10 © 2004 Microchip Technology Inc. DS70070B-page 23-47...
Page 646 Family Reference Manual 23.6.6.3 Receive Error Interrupts A receive error interrupt will be indicated by the ERRIF bit (CiINTF<5>). This bit shows that an error condition occurred. The source of the error can be determined by checking the bits in the CAN Interrupt Status Register CiINTF.
Page 647: Transmission
Prior to sending the message, the user must initialize the TXnIE bit (CiINTE<2>, CiINTE<3> or CiINTE<4>) to enable or disable an interrupt when the message is sent. The user must also initialize the transmit priority. Figure 23-12 shows a block diagram of the Transmit Buffers. © 2004 Microchip Technology Inc. DS70070B-page 23-49...
Page 648 Family Reference Manual Figure 23-12: Transmit Buffers TXB0 TXB1 TXB2 Message Queue Control Transmit Byte Sequencer 23.7.3 Transmit Message Priority Transmit priority is a prioritization within each node of the pending transmittable messages. Prior to sending the SOF (Start-Of-Frame), the priorities of all buffers ready for transmission are compared.
Page 649 - Processor sets TXREQ while module receiving/transmitting message. Module continues with CAN message. - Processor clears TXREQ while module looking for 11 recessive bits. Module aborts pending transmission, sets TXABT bit in 2 clocks. - Another module takes the available transmit slot. © 2004 Microchip Technology Inc. DS70070B-page 23-51...
Page 650 Family Reference Manual Figure 23-14: Abort All Messages CAN bus CiTX ABAT TXREQ TXnIF TXABT - Processor sets TXREQ while module receiving/transmitting message. Module continues with CAN message. - Processor sets ABAT while module looking for 11 recessive bits. Module clears TXREQ bits.
Page 651 - Message loses arbitration. Module releases bus and sets TXLARB bit. - Module waits for 11 recessive bits before re-trying transmission of queued message. - At successful completion of transmission, TXREQ bit cleared and TXnIF bit set. © 2004 Microchip Technology Inc. DS70070B-page 23-53...
Page 652 Family Reference Manual Figure 23-17: Transmit Flowchart START The message transmission sequence begins when the device determines that the TXREQ for any of the Transmit registers has been set. Are any TXREQ bits = 1 Clearing the TXREQ bit while it is set, or setting...
Page 653 Upon any Reset the CAN module has to be initialized. All registers are set according to the reset values. The content of a transmitted message is lost. The initialization is discussed in Section 23.5.5 “Configuration Mode”. © 2004 Microchip Technology Inc. DS70070B-page 23-55...
Page 654 Family Reference Manual 23.7.8 Transmission Errors The CAN module will detect the following transmission errors: • Acknowledge Error • Form Error • Bit Error These transmission errors will not necessarily generate an interrupt but are indicated by the transmission error counter. However, each of these errors will cause the transmission error counter to be incremented by one.
Page 655 At least one of the three transmit buffers is empty (not scheduled) and can be loaded to schedule a message for transmission. Reading the TXnIF flags in the CiINTF register will indicate which transmit buffer is available and caused the interrupt. © 2004 Microchip Technology Inc. DS70070B-page 23-57...
Page 656: Error Detection
Family Reference Manual 23.7.9.2 Transmission Error Interrupts A transmission error interrupt will be indicated by the ERRIF flag. This flag shows that an error condition occurred. The source of the error can be determined by checking the error flags in the CAN Interrupt Status register CiINTF.
Page 657 It may be desirable to disable specific interrupts after they have occurred once to stop the device from interrupting repeatedly as the Error Counter moves up and down in the vicinity of a threshold value. © 2004 Microchip Technology Inc. DS70070B-page 23-59...
Page 658: Can Baud Rate
Family Reference Manual 23.9 CAN Baud Rate All nodes on any particular CAN bus must have the same nominal bit rate. The CAN bus uses NRZ coding which does not encode a clock. Therefore the receivers independent clock must be recovered by the receiving nodes and synchronized to the transmitters clock.
Page 659 The frequencies of the oscillators in the different nodes must be coordinated in order to provide a system-wide specified time quantum. This means that all oscillators must have a T that is a integral divisor of T © 2004 Microchip Technology Inc. DS70070B-page 23-61...
Page 660 Family Reference Manual 23.9.3 Propagation Segment This part of the bit time is used to compensate physical delay times within the network. These delay times consist of the signal propagation time on the bus line and the internal delay time of the nodes.
Page 661 Nominal Sample Length Bit Length Point Figure 23-22: Shortening a Bit Period Input Signal Propagation Phase Phase ≤ sjw Sync Segment Segment 1 Segment 2 Sample Actual Nominal Point Bit Length Bit Length © 2004 Microchip Technology Inc. DS70070B-page 23-63...
Page 662: Interrupts
Family Reference Manual 23.9.7 Programming Time Segments Some requirements for programming of the time segments are as follows: • Propagation Segment + Phase1 Segment > = Phase2 Segment • Phase2 Segment > Synchronous Jump Width Typically, the sampling of the bit should take place at about 60-70% through the bit time, depending on the system parameters.
Page 663: Time-Stamping
When the module is active, the CiTX pin (i = 1 or 2) is always dedicated to the CAN output function. The TRIS bits associated with the transmit pins are overridden by the CAN bus modes. The module receives the CAN input on the CiRX input pin. © 2004 Microchip Technology Inc. DS70070B-page 23-65...
Page 664: Operation In Cpu Power Saving Modes
Family Reference Manual 23.13 Operation in CPU Power Saving Modes 23.13.1 Operation in Sleep Mode Sleep mode is entered by executing a PWRSAV #0 instruction. This will stop the crystal oscillator and shut down all system clocks. The user should ensure that the module is not active when the CPU goes into Sleep mode.
Page 665 If CSIDL = 1, the module will discontinue operation in Idle mode. The same rules and conditions for entry to and wake from Sleep mode apply. Refer to Section 23.13.1 “Operation in Sleep Mode” for further details. © 2004 Microchip Technology Inc. DS70070B-page 23-67...
Page 666: Can Protocol Overview
Family Reference Manual 23.14 CAN Protocol Overview The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of robustness. The CAN Protocol is fully defined by Robert Bosch GmbH, in the CAN Specification V2.0B from 1991.
Page 667 The CAN bus module definition encompasses two levels of the overall protocol: • The Data Link Layer - The Logical Link Control (LLC) sub layer - The Medium Access Control (MAC) sub layer • The Physical Layer - The Physical Signaling (PLS) sub layer © 2004 Microchip Technology Inc. DS70070B-page 23-69...
Page 668 Family Reference Manual The LLC sub layer is concerned with Message Filtering, Overload Notification and Error Recovery Management. The scope of the LLC sub layer is: • To provide services for data transfer and for remote data request. • To decide which messages received by the LLC sub layer are actually to be accepted.
Page 669 Bus Failure Bit Timing Management Synchronization PMA (Physical Medium Attachment) Driver/Receiver Characteristics MDI (Medium Dependent Interface) Connectors Shaded Regions Has to be Implemented Implemented by Transceiver Connector in dsPIC30F Firmware the CAN Module Chip © 2004 Microchip Technology Inc. DS70070B-page 23-71...
Page 670: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 671: Revision History
Revision A This is the initial released revision of this document. Revision B This revision incorporates additional technical content for the dsPIC30F CAN module. Revision C This revision incorporates all known errata at the time of this document update. © 2004 Microchip Technology Inc.
Page 672 Family Reference Manual NOTES: DS70070B-page 23-74 © 2004 Microchip Technology Inc.
Page 673: Section 24. Device Configuration
This section of the manual contains the following topics: 24.1 Introduction ........................24-2 24.2 Device Configuration Registers ................... 24-2 24.3 Configuration Bit Descriptions..................24-7 24.4 Device Identification Registers..................24-8 24.5 Related Application Notes.................... 24-9 24.6 Revision History ......................24-10 © 2004 Microchip Technology Inc. DS70071C-page 24-1...
Page 674: Introduction
Family Reference Manual 24.1 Introduction The device configuration registers allow each user to customize certain aspects of the device to fit the needs of the application. Device configuration registers are non-volatile memory locations in the program memory map that hold settings for the dsPIC device during power-down. The configuration registers hold global setup information for the device, such as the oscillator source, Watchdog Timer mode and code protection settings.
Page 675 001x = HS - HS Crystal Oscillator mode (10 MHz-25 MHz crystal) 000x = XTL - XTL Crystal Oscillator mode (200 kHz-4 MHz crystal) Legend: R = Readable bit P = Programmable bit U = Unimplemented bit © 2004 Microchip Technology Inc.. DS70071C-page 24-3...
Page 676 Family Reference Manual Register 24-2: FWDT: Watchdog Timer Configuration Register Upper Byte: — — — — — — — — bit 23 bit 16 Middle Byte: FWDTEN — — — — — — — bit 15 bit 8 Lower Byte: FWPSA<1:0>...
Page 677 11 = PWRT = 64 ms 10 = PWRT = 16 ms 01 = PWRT = 4 ms 00 = Power-up timer disabled Legend: R = Readable bit P = Programmable bit U = Unimplemented bit © 2004 Microchip Technology Inc.. DS70071C-page 24-5...
Page 678 Family Reference Manual Register 24-4: FGS: General Code Segment Configuration Register Upper Byte: — — — — — — — — bit 23 bit 16 Middle Byte: — — — — — — — — bit 15 bit 8 Lower Byte: —...
Page 679: Configuration Bit Descriptions
Note: If the code protection configuration fuse group (FGS<GCP:GWRP>) bits have been programmed, an erase of the entire code-protected device is only possible at voltages, V >= 4.5 volts. © 2004 Microchip Technology Inc.. DS70071C-page 24-7...
Page 680: Device Identification Registers
Family Reference Manual 24.4 Device Identification Registers The dsPIC30F devices have two sets of registers located in configuration space that provide identification information. 24.4.1 Device ID (DEVID) Registers The configuration memory space locations 0xFF0000 and 0xFF0002 are used to store a read only Device ID number that is set when the device is manufactured.
Page 681: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 682: Revision History
Revision A This is the initial released revision of this document. Revision B This revision incorporates technical content changes for the dsPIC30F Device Configuration module. Revision C This revision incorporates all known errata at the time of this document update.
Page 683: Section 25. Development Tool Support
25.1 Introduction ........................25-2 25.2 Microchip Hardware and Language Tools..............25-2 25.3 Third Party Hardware/Software Tools and Application Libraries ........25-6 25.4 dsPIC30F Hardware Development Boards..............25-11 25.5 Related Application Notes..................25-15 25.6 Revision History ......................25-16 © 2004 Microchip Technology Inc.
Page 684: Introduction
Family Reference Manual Note: Some development tools described in this section are not available at the time of this writing, however they are currently under development. Some of the product details may change. Please check the Microchip web site or your local Microchip sales office for the most current information and the availability of each product.
Page 685 Microchip sales office for availability of the MPLAB C30 C compiler. The Microchip Technology MPLAB C30 C compiler is a complete, easy-to-use language product. It allows dsPIC applications codes to be written in high level C language and then be fully converted into machine-object code for programming of the microcontroller.
Page 686 Family Reference Manual 25.2.4 MPLAB ICE 4000 In-Circuit Emulator Note: This product is currently under development at the time of this writing. Some of the product details may change. Please refer to the Microchip web site or your local Microchip sales office for the most current information and the availability of this product.
Page 687 In Stand-alone mode, the PRO MATE II device programmer will be able to read, verify or program PICmicro and dsPIC30F devices. It will also be able to set code protection in this mode. PRO MATE II features will include: •...
Page 688: Third Party Hardware/Software Tools And Application Libraries
Microchip sales office for the most current information and the availability of these products. In addition to the Microchip MPLAB C30 C Compiler, the dsPIC30F will be supported by ANSI C compilers developed by IAR, HI-TECH and Custom Computer Services (CCS).
Page 689 • ceil(), floor() • fmod(), frexp() The math function routines will be developed and optimized in dsPIC30F assembly language and will be callable from both assembly and C language. Floating point and double precision versions of each function shall be provided. The Microchip MPLAB C30 and IAR C compilers will be supported.
Page 690 Microchip sales office for the most current information and the availability of this product. Microchip will offer a peripheral driver library that will support the setup and control of dsPIC30F hardware peripherals, including, but not limited to: • Analog-to-Digital Converter •...
Page 691 Microchip sales office for the most current information and the availability of this product. Microchip will offer a CAN driver library, which will support the dsPIC30F CAN peripheral. Some of the CAN functions which will be supported are: • Initialize CAN Module •...
Page 692 Operating Systems for the vehicle software standard OSEK/VDX will be developed for support of the dsPIC30F product family. The functionality of OSEK, “Offene Systeme und deren Schnittstellen für die Elektronik im Kraftfahrzeug” (Open systems and the corresponding interfaces for automotive electronics), is harmonized with VDX “Vehicle Distributed eXecutive”...
Page 693: Dspic30F Hardware Development Boards
Each board will feature key dsPIC30F peripherals and support Microchip’s MPLAB In-Circuit Debugger (ICD 2) tool for cost effective debugging and programming of the dsPIC30F device. The three initial boards to be provided are: •...
Page 694 The dsPIC30F general purpose development board will provide the application designer with a low cost development tool in which to become familiar with the dsPIC30F 16-bit architecture, high performance peripherals and powerful instruction set. The development board will serve as an ideal prototyping tool in which to quickly develop and validate key design requirements.
Page 695 400 volts and up to 1 kW power output. The high voltage module will have an active power factor correction circuit that will be controlled by the dsPIC30F device. This power module is intended for AC induction motor and power inverter applications.
Page 696 Microchip sales office for the most current information and the availability of this product. The dsPIC30F connectivity development board will provide the application developer a basic platform for developing and evaluating various connectivity solutions, implementing TCP/IP protocol layers combined with V.22/V.22bis and V.32 (non-trellis coding) ITU specifications, across PSTN or Ethernet communication channels.
Page 697: Related Application Notes
This section lists application notes that are related to this section of the manual. These application notes may not be written specifically for the dsPIC30F Product Family, but the concepts are pertinent and could be used with modification and possible limitations. The current...
Page 698: Revision History
25.6 Revision History Revision A This is the initial released revision of the dsPIC30F Development Tool Support description. Revision B There were no technical content or editorial revisions to this section of the manual, however, this section was updated to reflect Revision B throughout the manual.
Page 699: Section 26. Appendix
This section of the manual contains the following topics: Appendix A: I2C™ Overview ....................26-2 Appendix B: CAN Overview ....................26-12 Appendix C: Codec Protocol Overview ................26-25 C is a trademark of Philips Corporation. © 2004 Microchip Technology Inc. DS70074C-page 26-1...
Page 700: Appendix A: I2C™ Overview
Family Reference Manual APPENDIX A: I C OVERVIEW This appendix provides an overview of the Inter-Integrated Circuit (I C™) bus, with Subsection A.2 “Addressing I C Devices” discussing the operation of the SSP modules in I C mode. The I C bus is a two-wire serial interface.
Page 701 Procedure that ensures that only one of the master devices will control the bus. This ensures that the transfer data does not get corrupted. Synchronization Procedure where the clock signals of two or more devices are synchronized. © 2004 Microchip Technology Inc. DS70074C-page 26-3...
Page 702 Family Reference Manual Addressing I C Devices There are two address formats. The simplest is the 7-bit address format with a R/W bit (Figure A-2). The more complex is the 10-bit address with a R/W bit (Figure A-3). For 10-bit address format, two bytes must be transmitted.
Page 703 Data Transfer Wait State Acknowledgment Acknowledgment Byte Complete Signal from Receiver Signal from Receiver Interrupt with Receiver Clock Line Held Low while Interrupts are Serviced 3 • 8 Start Stop Address Wait Data Condition Condition State © 2004 Microchip Technology Inc. DS70074C-page 26-5...
Page 704 Family Reference Manual Figure A-6 and Figure A-7 illustrate master-transmitter and master-receiver data transfer sequences. Figure A-6: Master-Transmitter Sequence For 7-bit address: Slave Address R/W A Data A Data A/A P '0' (write) data transferred (n bytes - acknowledge) A master transmitter addresses a slave receiver with a 7-bit address.
Page 705 A = acknowledge (SDA low) A = not acknowledge (SDA high) From master to slave S = Start Condition From slave to master P = Stop Condition © 2004 Microchip Technology Inc. DS70074C-page 26-7...
Page 706 Family Reference Manual Multi-master The I C protocol allows a system to have more than one master. This is called a multi-master system. When two or more masters try to transfer data at the same time, arbitration and synchronization occur.
Page 707 SCL line low. The SCL line high time is determined by the device with the shortest high period, Figure A-10. Figure A-10: Clock Synchronization Start Counting Wait State High Period CLK 1 Counter Reset CLK 2 © 2004 Microchip Technology Inc. DS70074C-page 26-9...
Page 708 Family Reference Manual Table A-2 and Table A-3 show the specifications of a compliant I C bus. The column titled, Parameter No., is provided to ease the user’s correlation to the corresponding parameter in the device data sheet. Figure A-11 and Figure A-12 show these times on the appropriate waveforms.
Page 709 LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line, max.+T = 1000 + 250 = 1250 ns (according to the Standard mode I C bus specification) before the SCL line is released. © 2004 Microchip Technology Inc. DS70074C-page 26-11...
Page 710: Appendix B: Can Overview
Family Reference Manual APPENDIX B: CAN OVERVIEW This appendix provides an overview of the Controller Area Network (CAN) bus. The CAN Section of this reference manual discusses the implementation of the CAN protocol for that hardware module. CAN Bus Background The Controller Area Network (CAN) is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security.
Page 711 The advantages of Basic CAN are the small chip size leading to low costs of these devices. © 2004 Microchip Technology Inc. DS70074C-page 26-13...
Page 712 Family Reference Manual Full CAN devices do the whole bus protocol in hardware, including the acceptance filtering and the message management. They contain several so called message objects which handle the identifier, the data, the direction (receive or transmit) and the information Standard CAN/Extended CAN.
Page 713 Medium Access Management (MAC-LME) Error Detection Error Signalling Acknowledgment Serialization/Deserialization Physical Layer PLS (Physical Signalling) Bus Failure Bit Encoding/Decoding management Bit Timing (PLS-LME) Synchronization PMA (Physical Medium Attachment) Driver/Receiver Characteristics MDI (Medium Dependent Interface) Connectors © 2004 Microchip Technology Inc. DS70074C-page 26-15...
Page 714 Family Reference Manual CAN Bus Features CAN has the following properties: • Prioritization of messages • Latency times ensured • Configuration flexibility • Multi-cast reception with time synchronization • System wide data consistency • Multi-master • Error detection and signaling •...
Page 715 (by checking for eleven consecutive ‘recessive’ bits), before the bus drivers are set to “on-bus” again. © 2004 Microchip Technology Inc. DS70074C-page 26-17...
Page 716 Family Reference Manual Frame Types B.6.1 Standard Data Frame A data frame is generated by a node when the node wishes to transmit data. The Standard CAN Data Frame is shown in Figure B-2. In common with all other frames, the frame begins with a Start-Of-Frame bit (SOF –...
Page 717 This is provided to allow nodes time for internal processing before the start of the next message frame. After the intermission, the bus line remains in the recessive state (Bus idle) until the next transmission starts. © 2004 Microchip Technology Inc. DS70074C-page 26-19...
Page 718 Family Reference Manual Figure B-2: Standard Data Frame DS70074C-page 26-20 © 2004 Microchip Technology Inc.
Page 719 Section 26. Appendix Figure B-3: Extended Data Format © 2004 Microchip Technology Inc. DS70074C-page 26-21...
Page 720 Family Reference Manual Figure B-4: Remote Data Frame DS70074C-page 26-22 © 2004 Microchip Technology Inc.
Page 721 Section 26. Appendix Figure B-5: Error Frame © 2004 Microchip Technology Inc. DS70074C-page 26-23...
Page 722 Family Reference Manual B.11 Referenced Documents Title Document Road Vehicles; Interchange of Digital Information, Controller Area Network ISO11898 Bosch CAN Specification Version 2.0 DS70074C-page 26-24 © 2004 Microchip Technology Inc.
Page 723: Appendix C: Codec Protocol Overview
Figure C-1 shows possible I S bus configurations. Although it is not indicated in Figure C-1, the two connected devices may have both a data transmit and a data receive connection. © 2004 Microchip Technology Inc. DS70074C-page 26-25...
Page 724 Family Reference Manual Figure C-1: S Bus Connections Transmitter master S Transmitter S Receiver S Transmitter S Receiver Receiver master S Controller S Transmitter S Receiver Separate controller as master Figure C-2: S Interface Timing Diagram Note: A 5 bit transfer is shown here for illustration purposes. The I S protocol does not specify word length –...
Page 725 Slot #3 – Slot #12 is dependent on the AC ‘97 codec that is selected, so the slot usage is summarized briefly here. For more details on slot usage, refer to the AC ‘97 Component Specification. © 2004 Microchip Technology Inc. DS70074C-page 26-27...
Page 726 Family Reference Manual C.4.2 Slot #0, TAG Frame Slot #0 is commonly called the ‘tag frame’. The tag frame has a bit location for each data time slot in the AC-Link protocol. These bits are used to specify which time slots in a frame are valid for use by the controller.
Page 727 The bits in Slot #12 are used for reading and writing GPIO pins in the AC ‘97 codec. The GPIO pins are provided for modem control functions on modem compatible devices. Figure C-3: AC-Link Signal Connections BIT_CLK 24.576 SYNC SDATA_OUT ‘ ‘ Controller Codec SDATA_IN /RESET © 2004 Microchip Technology Inc. DS70074C-page 26-29...
Page 728 Family Reference Manual Figure C-4: AC-Link Data Frame SYNC Slot3 Slot 4 Slot 10 Slot 11 Slot 12 Command Command SDATA_OUT Left PCM Right PCM Line 2 Handset Codec I/O Frame Address Data Data Data Control Slot3 Slot 4...
Page 729 19 bit 18 bit 12 bit 11 Reserved Control Register Index (set to 0) SLOT#2: Command Data bit 0 bit 19 bit 4 Control Register 16-bit Write Data Reserved (Set to 0sifcurrentlyperformingareadoperation.)' (set to 0) © 2004 Microchip Technology Inc. DS70074C-page 26-31...
Page 730 Family Reference Manual NOTES: DS70074C-page 26-32 © 2004 Microchip Technology Inc.
Page 731 Family Reference Manual Numerics Low Voltage Detect (LVD) ......... 9-3 Oscillator System............7-3 10-bit Address Mode ............21-35 Output Compare Module ......... 14-2 12-Bit A/D Reset System ............8-2 ADCHS ............17-4, 18-4 Shared Port Structure..........11-4 ADPCFG ............17-4, 18-4 Type A Timer ............
Page 732 BOR and POR ............24-7 DSP Filter Design Software Utility ........25-8 General Code Segment ...........24-7 dsPIC Language Suite............. 25-3 Motor Control PWM Module........24-7 dsPIC30F Hardware Development Boards....25-11 Oscillator ..............24-7 Connection Considerations ..........17-47 Connectivity Development Board........25-14 Equations Control Register Descriptions ..........3-18 Calculating the PWM Period........
Page 733 Family Reference Manual Bus Arbitration and Bus Collision......21-30 Interrupt Latency Bus Collision During a Repeated One-Cycle Instructions ..........6-11 Start Condition ..........21-31 Two-Cycle Instructions ..........6-12 Bus Collision During a Start Condition....21-31 Interrupt Operation ............6-9 Bus Collision During a Stop Condition ....
Page 734 With Fault Protection Input Pin ......14-19 Oscillator Switching Sequence.........7-23 PWM Duty Cycle Comparison Units ......15-20 OSEK Operating Systems..........25-10 PWM Fault Pins ............. 15-32 Other dsPIC30F CPU Control Registers......2-16 PWM Output and Polarity Control........15-32 DISICNT..............2-16 PWM Output Override ........... 15-29 MODCON..............2-16 PWM Special Event Trigger...........
Page 735 Family Reference Manual ADCON1 (A/D Control) Register1..17-5, 18-5, 21-11 FBORPOR (BOR and POR ADCON1 A/D Control 1 ........17-5, 17-6 Configuration Register)........24-5 ADCON1 A/D Control 1 (12-bit) ....... 18-5 FBORPOR BOR and POR Device Configuration.. 15-15 ADCON2 (A/D Control) Register2....17-7, 18-6 FGS (General Code Segment ADCON2 A/D Control 2 ...........
Page 736 UART Reception............ 19-17 Time-base for Input Capture/Output Compare....12-22 UART Reception with Receive Overrun ....19-17 Timer as an External Interrupt Pin .........12-22 TRIS (Data Direction) Registers ........11-3 Timer Interrupts..............12-14 Tuning the Oscillator Circuit..........7-11 DS70046C-page 6 © 2004 Microchip Technology Inc.
Page 737 Family Reference Manual Using QEI as Alternate 16-bit Timer/Counter ....16-16 Type A Timer ..............12-3 Type B Timer ..............12-4 Using Table Read Instructions........... 5-3 Type C Timer ..............12-5 Byte Mode ..............5-3 Word Mode ..............5-3 Using Table Write Instructions...........
Page 738 Fax: 86-532-502-7205 Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 10/20/04  2004 Microchip Technology Inc. DS70046C-page 8...

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