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Microchip Technology dsPIC30F6010 Datasheet

Microchip Technology dsPIC30F6010 Datasheet

High performance digital signal controllers
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dsPIC30F6010
Data Sheet
High Performance
Digital Signal Controllers
Advance Information
 2004 Microchip Technology Inc.
DS70119B

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Summary of Contents for Microchip Technology dsPIC30F6010

  • Page 1 Data Sheet High Performance Digital Signal Controllers Advance Information  2004 Microchip Technology Inc. DS70119B...
  • Page 2 MPSIM, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, Select Mode, SmartSensor, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A.
  • Page 3 • ± 16-bit single cycle shift • Position Measurement (x2 and x4) mode • Programmable digital noise filters on inputs • Alternate 16-bit Timer/Counter mode • Interrupt on position counter rollover/underflow Advance Information  2004 Microchip Technology Inc. DS70119B-page 1...
  • Page 4 4096 8 ch 16 ch * This table provides a summary of the dsPIC30F6010 peripheral features. Other available devices in the dsPIC30F Motor Control and Power Conversion Family are shown for feature comparison. Advance Information  2004 Microchip Technology Inc.
  • Page 5 SCK2/CN8/RG6 IC1/RD8 SDI2/CN9/RG7 INT4/RA15 SDO2/CN10/RG8 MCLR INT3/RA14 SS2/CN11/RG9 dsPIC30F6010 OSC2/CLKO/RC15 OSC1/CLKI FLTA/INT1/RE8 SCL/RG2 FLTB/INT2/RE9 SDA/RG3 AN5/QEB/CN7/RB5 AN4/QEA/CN6/RB4 EMUC3/SCK1/INT0/RF6 AN3/INDX/CN5/RB3 SDI1/RF7 AN2/SS1/LVDIN/CN4/RB2 EMUD3/SDO1/RF8 PGC/EMUC/AN1/CN3/RB1 U1RX/RF2 PGD/EMUD/AN0/CN2/RB0 U1TX/RF3 Note: Pinout subject to change. Advance Information  2004 Microchip Technology Inc. DS70119B-page 3...

  • Page 6: Table Of Contents

    When contacting a sales office or the literature center, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com/cn to receive the most current information on all of our products. Advance Information  2004 Microchip Technology Inc. DS70119B-page 4...

  • Page 7: Device Overview

    DEVICE OVERVIEW This document contains device specific information for the dsPIC30F6010 device. The dsPIC30F devices contain extensive Digital Signal Processor (DSP) func- tionality within a high performance 16-bit microcontroller (MCU) architecture. Figure 1-1 shows a device block diagram for the dsPIC30F6010 device.

  • Page 8: Pwm3H/Re5

    PWM4L/RE6 PWM4H/RE7 UART1, FLTA/INT1/RE8 SPI1, Motor Control Timers UART2 FLTB/INT2/RE9 SPI2 PORTE C1RX/RF0 C2RX/RG0 C1TX/RF1 C2TX/RG1 U1RX/RF2 SCL/RG2 U1TX/RF3 SDA/RG3 U2RX/CN17/RF4 SCK2/CN8/RG6 U2TX/CN18/RF5 SDI2/CN9/RG7 EMUC3/SCK1/INT0/RF6 SDO2/CN10/RG8 SDI1/RF7 SS2/CN11/RG9 EMUD3/SDO1/RF8 PORTG PORTF Advance Information  2004 Microchip Technology Inc. DS70119B-page 6...
  • Page 9 Multiple functions may exist on one port pin. When direction of the port pin. TABLE 1-1: dsPIC30F6010 I/O PIN DESCRIPTIONS Buffer Pin Name Description Type...

  • Page 10: Mclr

    TABLE 1-1: dsPIC30F6010 I/O PIN DESCRIPTIONS (CONTINUED) Buffer Pin Name Description Type Type FLTA PWM Fault A input. FLTB PWM Fault B input. PWM1L — PWM 1 Low output. PWM1H — PWM 1 High output. PWM2L — PWM 2 Low output.
  • Page 11 TABLE 1-1: dsPIC30F6010 I/O PIN DESCRIPTIONS (CONTINUED) Buffer Pin Name Description Type Type T1CK Timer1 external clock input. T2CK Timer2 external clock input. T3CK Timer3 external clock input. T4CK Timer4 external clock input. T5CK Timer5 external clock input. U1RX UART1 Receive.
  • Page 12 NOTES: Advance Information  2004 Microchip Technology Inc. DS70119B-page 10...

  • Page 13: Cpu Architecture Overview

    This document provides summary dsPIC30F6010 CPU and peripheral function. For a The X AGU also supports bit-reversed addressing on complete description of this functionality, please refer destination effective addresses, to greatly simplify input to the dsPIC30F Family Reference Manual (DS70046).
  • Page 14 (DA) and the Digit Carry (DC) status bit. 2.2.3 PROGRAM COUNTER The Program Counter is 23 bits wide. Bit 0 is always clear. Therefore, the PC can address up to 4M instruction words. Advance Information  2004 Microchip Technology Inc. DS70119B-page 12...
  • Page 15 Program Space Visibility Page Address RCOUNT REPEAT Loop Counter DCOUNT DO Loop Counter DOSTART DO Loop Start Address DO Loop End Address DOEND Core Configuration Register CORCON OAB SAB IPL2 IPL1 IPL0 Status Register Advance Information  2004 Microchip Technology Inc. DS70119B-page 13...
  • Page 16 Automatic saturation on/off for AccA (SATA). Automatic saturation on/off for AccB (SATB). Automatic saturation on/off for writes to data memory (SATDW). Accumulator Saturation mode selection (ACCSAT). Note: For CORCON layout, see Table 4-2. Advance Information  2004 Microchip Technology Inc. DS70119B-page 14...
  • Page 17 FIGURE 2-2: DSP ENGINE BLOCK DIAGRAM 40-bit Accumulator A Round 40-bit Accumulator B Logic Carry/Borrow Out Saturate Adder Carry/Borrow In Negate Barrel Shifter Sign-Extend Zero Backfill 17-bit Multiplier/Scaler To/From W Array Advance Information  2004 Microchip Technology Inc. DS70119B-page 15...
  • Page 18 (OVATEN, OVBTEN) in the INTCON1 register (refer to Section 5.0) is set. This allows the user to take immediate action, for example, to correct system gain. Advance Information  2004 Microchip Technology Inc. DS70119B-page 16...
  • Page 19 MCU (X and Y) data space though the X bus. For this class of instructions, the data is always subject to rounding. Advance Information  2004 Microchip Technology Inc. DS70119B-page 17...
  • Page 20 (bit 39) is used to determine the sign of the operand being tested. If the SATDW bit in the CORCON register is not set, the input data is always passed through unmodified under all conditions. Advance Information  2004 Microchip Technology Inc. DS70119B-page 18...

  • Page 21: Memory Organization

    (Read 0’s) 7FEFFE 7FF000 Data EEPROM (4 Kbytes) 7FFFFE 800000 Reserved 8005BE 8005C0 UNITID (32 instr.) 8005FE 800600 Reserved F7FFFE Device Configuration F80000 Registers F8000E F80010 Reserved FEFFFE FF0000 DEVID (2) FFFFFE Advance Information  2004 Microchip Technology Inc. DS70119B-page 19...

  • Page 22: 2004 Microchip Technology Inc

    Table Instruction 8 bits 16 bits User/ Byte 24-bit EA Configuration Select Space Select Note: Program Space Visibility cannot be used to access bits <23:16> of a word in program memory. Advance Information  2004 Microchip Technology Inc. DS70119B-page 20...

  • Page 23: 2004 Microchip Technology Inc

    PROGRAM DATA TABLE ACCESS (LS WORD) PC Address 0x000000 00000000 0x000002 00000000 00000000 0x000004 0x000006 00000000 TBLRDL.B (Wn<0> = 0) TBLRDL.W Program Memory ‘Phantom’ Byte TBLRDL.B (Wn<0> = 1) (Read as ‘0’). Advance Information  2004 Microchip Technology Inc. DS70119B-page 21...

  • Page 24: 2004 Microchip Technology Inc

    - Execution upon re-entering the loop after an interrupt is serviced • Any other iteration of the REPEAT loop will allow the instruction, accessing data using PSV, to execute in a single cycle. Advance Information  2004 Microchip Technology Inc. DS70119B-page 22...

  • Page 25: 2004 Microchip Technology Inc

    A data space memory map is shown in Figure 3-6. addresses. Figure 3-7 shows a graphical summary of how X and Y data spaces are accessed for MCU and DSP instructions. Advance Information  2004 Microchip Technology Inc. DS70119B-page 23...

  • Page 26: 2004 Microchip Technology Inc

    FIGURE 3-6: dsPIC30F6010 DATA SPACE MEMORY MAP LS Byte MS Byte 16 bits Address Address 0x0000 0x0001 2 Kbyte SFR Space SFR Space 0x07FE 0x07FF 0x0800 0x0801 8 Kbyte Near X Data RAM (X) Data Space 8 Kbyte 0x17FE...

  • Page 27: 2004 Microchip Technology Inc

    (Y SPACE) UNUSED Non-MAC Class Ops (Read/Write) MAC Class Ops Read Only MAC Class Ops (Write) Indirect EA using any W Indirect EA using W8, W9 Indirect EA using W10, W11 Advance Information  2004 Microchip Technology Inc. DS70119B-page 25...

  • Page 28: 2004 Microchip Technology Inc

    MAC instruction All effective addresses are 16 bits wide and point to bytes within the data space. Therefore, the data space address range is 64 Kbytes or 32K words. Advance Information  2004 Microchip Technology Inc. DS70119B-page 26...

  • Page 29: 2004 Microchip Technology Inc

    MSB is always clear. Note: A PC push during exception processing POP: [--W15] PUSH: [W15++] will concatenate the SRL register to the MSB of the PC prior to the push. Advance Information  2004 Microchip Technology Inc. DS70119B-page 27...

  • Page 30: 2004 Microchip Technology Inc

    Advance Information DS70119B-page 28  2004 Microchip Technology Inc.

  • Page 31: 2004 Microchip Technology Inc

    Advance Information  2004 Microchip Technology Inc. DS70119B-page 29...

  • Page 32: 2004 Microchip Technology Inc

    NOTES: Advance Information DS70119B-page 30  2004 Microchip Technology Inc.

  • Page 33: Address Generator Units

    • Register Indirect Post-modified • Register Indirect Pre-modified • 5-bit or 10-bit Literal Note: Not all instructions support all the address- modes given above. Individual instructions may support different subsets of these addressing modes. Advance Information  2004 Microchip Technology Inc. DS70119B-page 31...

  • Page 34: 2004 Microchip Technology Inc

    X data space for W8 and W9 and Y data space upper address boundaries). for W10 and W11. Note: Register Indirect with Register Offset Addressing is only available for W9 (in X space) and W11 (in Y space). Advance Information DS70119B-page 32  2004 Microchip Technology Inc.

  • Page 35: 2004 Microchip Technology Inc

    ;fill the 50 buffer locations W0, [W1++] ;fill the next location AGAIN: INC W0,W0 ;increment the fill value 0x1163 Start Addr = 0x1100 End Addr = 0x1163 Length = 0x0032 words Advance Information  2004 Microchip Technology Inc. DS70119B-page 33...

  • Page 36: 2004 Microchip Technology Inc

    Around Center of Binary Value b2 b3 b4 b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer Advance Information DS70119B-page 34  2004 Microchip Technology Inc.

  • Page 37: 2004 Microchip Technology Inc

    BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size (Words) XB<14:0> Bit-Reversed Address Modifier Value 32768 0x4000 16384 0x2000 8192 0x1000 4096 0x0800 2048 0x0400 1024 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 Advance Information  2004 Microchip Technology Inc. DS70119B-page 35...

  • Page 38: 2004 Microchip Technology Inc

    NOTES: Advance Information DS70119B-page 36  2004 Microchip Technology Inc.

  • Page 39: Interrupts

    All interrupt sources can be user assigned to one of 7 priority levels, 1 through 7, via the IPCx registers. The dsPIC30F6010 has 44 interrupt sources and 4 Each interrupt source is associated with an interrupt processor exceptions (traps), which must be arbitrated vector, as shown in Table 5-1.

  • Page 40: 2004 Microchip Technology Inc

    PWM - PWM Period Match QEI - QEI Interrupt Reserved LVD - Low Voltage Detect FLTA - PWM Fault A FLTB - PWM Fault B 45-53 53-61 Reserved Lowest Natural Order Priority Advance Information DS70119B-page 38  2004 Microchip Technology Inc.

  • Page 41: 2004 Microchip Technology Inc

    B causes a catastrophic overflow from bit 39 and all saturation is disabled. If the shift amount specified in a shift instruction is greater than the maximum allowed shift amount, a trap will occur. Advance Information  2004 Microchip Technology Inc. DS70119B-page 39...

  • Page 42: 2004 Microchip Technology Inc

    Address Error Trap Vector Math Error Trap Vector Reserved Vector AIVT Reserved Vector Reserved Vector Interrupt 0 Vector 0x000094 Interrupt 1 Vector — — — Interrupt 52 Vector 0x0000FE Interrupt 53 Vector Advance Information DS70119B-page 40  2004 Microchip Technology Inc.

  • Page 43: 2004 Microchip Technology Inc

    At the same time, the processor will wake-up from Sleep or Idle and begin execution of the Interrupt Service Routine (ISR) needed to process the interrupt request. Advance Information  2004 Microchip Technology Inc. DS70119B-page 41...

  • Page 44: 2004 Microchip Technology Inc

    Advance Information DS70119B-page 42  2004 Microchip Technology Inc.

  • Page 45: Flash Program Memory

    NVMADR Reg EA Using NVMADRU Reg NVMADR Addressing 8 bits 16 bits Working Reg EA Using TBLPAG Reg Table Instruction 8 bits 16 bits Byte User/Configuration Select 24-bit EA Space Select Advance Information  2004 Microchip Technology Inc. DS70119B-page 43...

  • Page 46: 2004 Microchip Technology Inc

    0xAA to the NVMKEY register. Refer to Section 6.6 for further details. Note: The user can also directly write to the NVMADR and NVMADRU registers to specify a program memory address for erasing or programming. Advance Information DS70119B-page 44  2004 Microchip Technology Inc.

  • Page 47: 2004 Microchip Technology Inc

    NVMKEY ; Write the 0x55 key #0xAA,W1 NVMKEY ; Write the 0xAA key BSET NVMCON,#WR ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Advance Information  2004 Microchip Technology Inc. DS70119B-page 45...

  • Page 48: 2004 Microchip Technology Inc

    NVMKEY ; Write the 0x55 key #0xAA,W1 NVMKEY ; Write the 0xAA key BSET NVMCON,#WR ; Start the erase sequence ; Insert two NOPs after the erase ; command is asserted Advance Information DS70119B-page 46  2004 Microchip Technology Inc.

  • Page 49: 2004 Microchip Technology Inc

    Advance Information  2004 Microchip Technology Inc. DS70119B-page 47...

  • Page 50: 2004 Microchip Technology Inc

    NOTES: Advance Information DS70119B-page 48  2004 Microchip Technology Inc.

  • Page 51: Data Eeprom Memory

    EEPROM. The gram word address. This example uses W0 as a dsPIC30F6010 device has 8 Kbytes (4K words) of data pointer to data EEPROM. The result is placed in EEPROM, with an address range from 0x7FF000 to register W4, as shown in Example 7-1.
  • Page 52 ; Erase cycle will complete in 2mS. CPU is not stalled for the Data Erase Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine erasure complete Advance Information DS70119B-page 50  2004 Microchip Technology Inc.
  • Page 53 ; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle ; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete Advance Information  2004 Microchip Technology Inc. DS70119B-page 51...
  • Page 54 Power-up Timer prevents EEPROM write. The write initiate sequence and the WREN bit together, help prevent an accidental write during brown-out, power glitch or software malfunction. Advance Information DS70119B-page 52  2004 Microchip Technology Inc.

  • Page 55: I/O Ports

    BLOCK DIAGRAM OF A DEDICATED PORT STRUCTURE Dedicated Port Module Read TRIS I/O Cell TRIS Latch Data Bus WR TRIS Data Latch I/O Pad WR LAT + WR Port Read LAT Read Port Advance Information  2004 Microchip Technology Inc. DS70119B-page 53...
  • Page 56 TRIS bit set (input). If the TRIS bit is cleared (out- input buffer to consume current that exceeds the put), the digital output level (V or V ) will be device specifications. converted. Advance Information DS70119B-page 54  2004 Microchip Technology Inc.
  • Page 57 Advance Information  2004 Microchip Technology Inc. DS70119B-page 55...
  • Page 58 CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE CN0PUE 0000 0000 0000 0000 CNPU2 00C6 CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE — — 0000 0000 0000 0000 Legend: u = uninitialized bit Advance Information DS70119B-page 56  2004 Microchip Technology Inc.

  • Page 59: Timer1 Module

    16-BIT TIMER1 MODULE BLOCK DIAGRAM (TYPE A TIMER) Equal Comparator x 16 TSYNC Sync TMR1 Reset T1IF Event Flag TGATE TGATE TCKPS<1:0> SOSCO/ T1CK Gate Prescaler LPOSCEN Sync 1, 8, 64, 256 SOSCI Advance Information  2004 Microchip Technology Inc. DS70119B-page 57...
  • Page 60 When a match between the timer and the period regis- C1 = C2 = 18 pF; R = 100K ter occurs, an interrupt can be generated, if the respective Timer Interrupt Enable bit is asserted. Advance Information DS70119B-page 58  2004 Microchip Technology Inc.
  • Page 61 32 kHz external crystal oscillator is active and the control bits have not been changed. The TSIDL bit should be cleared to ‘0’ in order for RTC to continue operation in Idle mode. Advance Information  2004 Microchip Technology Inc. DS70119B-page 59...
  • Page 62 Advance Information DS70119B-page 60  2004 Microchip Technology Inc.

  • Page 63: Timer2/3 Module

    32-bit timer module, but an interrupt is generated with the Timer3 interrupt flag (T3IF) and the interrupt is enabled with the Timer3 Interrupt Enable bit (T3IE). Advance Information  2004 Microchip Technology Inc. DS70119B-page 61...
  • Page 64 Gate 1, 8, 64, 256 Sync Note: Timer Configuration bit T32, T2CON(<3>) must be set to 1 for a 32-bit timer/counter operation. All control bits are respective to the T2CON register. Advance Information  2004 Microchip Technology Inc. DS70119B-page 62...
  • Page 65 FIGURE 10-3: 16-BIT TIMER3 BLOCK DIAGRAM (TYPE C TIMER) ADC Event Trigger Equal Comparator x 16 TMR3 Reset T3IF Event Flag TGATE TGATE TCKPS<1:0> T3CK Sync Prescaler 1, 8, 64, 256 Advance Information  2004 Microchip Technology Inc. DS70119B-page 63...
  • Page 66 However, if the timer is disabled (TON = 0), then the Timer 2 prescaler cannot be reset, since the prescaler clock is halted. TMR2/TMR3 is not cleared when T2CON/T3CON is written. Advance Information  2004 Microchip Technology Inc. DS70119B-page 64...
  • Page 67 Advance Information  2004 Microchip Technology Inc. DS70119B-page 65...
  • Page 68 NOTES: Advance Information DS70119B-page 66  2004 Microchip Technology Inc.

  • Page 69: Timer4/5 Module

    1, 8, 64, 256 Sync Note: Timer Configuration bit T32, T4CON(<3>) must be set to ‘ ’ for a 32-bit timer/counter operation. All control bits are respective to the T4CON register. Advance Information  2004 Microchip Technology Inc. DS70119B-page 67...
  • Page 70 FIGURE 11-3: 16-BIT TIMER5 BLOCK DIAGRAM (TYPE C TIMER) Equal ADC Event Trigger Comparator x 16 TMR5 Reset T5IF Event Flag TGATE TGATE TCKPS<1:0> Sync T5CK Prescaler 1, 8, 64, 256 Advance Information DS70119B-page 68  2004 Microchip Technology Inc.
  • Page 71 Advance Information  2004 Microchip Technology Inc. DS70119B-page 69...
  • Page 72 NOTES: Advance Information DS70119B-page 70  2004 Microchip Technology Inc.

  • Page 73: Input Capture Module

    These operating modes are determined by setting the Capture module. Input capture is useful for such modes appropriate bits in the ICxCON register (where x = 1,2,...,N). The dsPIC30F6010 device has 8 capture channels. • Frequency/Period/Pulse Measurements • Additional sources of External Interrupts...
  • Page 74 111 and the Interrupt Enable bit is asserted. The same wake-up can generate an interrupt, if the conditions for processing the interrupt have been satisfied. The wake-up feature is useful as a method of adding extra external pin interrupts. Advance Information DS70119B-page 72  2004 Microchip Technology Inc.
  • Page 75 Advance Information  2004 Microchip Technology Inc. DS70119B-page 73...
  • Page 76 NOTES: Advance Information  2004 Microchip Technology Inc. DS70119B-page 74...

  • Page 77: Output Compare Module

    These operating modes are determined by setting the Compare module. appropriate bits in the 16-bit OCxCON SFR (where x = 1,2,3,...,N). The dsPIC30F6010 device has 8 compare channels. OCxRS and OCxR in the figure represent the Dual Compare registers. In the dual compare mode, the OCxR register is used for the first compare and OCxRS is used for the second compare.
  • Page 78 • The external FAULT condition has been removed. To initiate another single pulse, issue another write to • The PWM mode has been re-enabled by writing set OCM<2:0> = 100. to the appropriate control bits. Advance Information  2004 Microchip Technology Inc. DS70119B-page 76...
  • Page 79 CPU Idle mode if the OCSIDL bit (OCxCON<13>) is at logic 0 and the selected time base (Timer2 or Timer3) is enabled and the TSIDL bit of the selected timer is set to logic 0. Advance Information  2004 Microchip Technology Inc. DS70119B-page 77...
  • Page 80 Advance Information DS70119B-page 78  2004 Microchip Technology Inc.

  • Page 81: Quadrature Encoder Interface (Qei) Module

    Reset Quadrature Encoder Interface Logic UPDN_SRC Comparator/ Zero Detect Equal QEICON<11> QEIM<2:0> Mode Select Max Count Register (MAXCNT) Programmable Digital Filter Programmable INDX Digital Filter PCDOUT Existing Pin Logic UPDN Up/Down Advance Information  2004 Microchip Technology Inc. DS70119B-page 79...
  • Page 82 This bit is only applicable when QEIM<2:0> = ‘100’ or ‘110’. The x4 Measurement mode provides for finer resolu- tion data (more position counts) for determining motor position. Advance Information DS70119B-page 80  2004 Microchip Technology Inc.
  • Page 83 The UPDN Control/Status bit (QEICON<11>) can be used to select the count direction state of the Timer register. When UPDN = 1, the timer will count up. When UPDN = 0, the timer will count down. Advance Information  2004 Microchip Technology Inc. DS70119B-page 81...
  • Page 84 QEIIF is located in the IFS2 Status register. Enabling an interrupt is accomplished via the respec- tive Enable bit, QEIIE. The QEIIE bit is located in the IEC2 Control register. Advance Information DS70119B-page 82  2004 Microchip Technology Inc.
  • Page 85 Advance Information  2004 Microchip Technology Inc. DS70119B-page 83...
  • Page 86 NOTES: Advance Information  2004 Microchip Technology Inc. DS70119B-page 84...

  • Page 87: Motor Control Pwm Module

    • ‘On-the-Fly’ PWM frequency changes The PWM module allows several modes of operation • Edge and Center Aligned Output modes which are beneficial for specific power control applications. • Single Pulse Generation mode Advance Information  2004 Microchip Technology Inc. DS70119B-page 85...
  • Page 88 PTPER Buffer FLTA PTCON FLTB Special Event Comparator Special Event Trigger Postscaler SEVTDIR PTDIR SEVTCMP PWM time base Note: Details of PWM Generator #1, #2, and #3 not shown for clarity. Advance Information  2004 Microchip Technology Inc. DS70119B-page 86...
  • Page 89 The interrupt signals generated by the PWM time base depend on the mode selection bits (PTMOD<1:0>) and the postscaler bits (PTOPS<3:0>) in the PTCON SFR. Advance Information  2004 Microchip Technology Inc. DS70119B-page 87...
  • Page 90 • Up/Down Counting modes: When the PTMR register is zero. Period The value held in the PTPER buffer is automatically loaded into the PTPER register when the PWM time base is disabled (PTEN = 0). Advance Information  2004 Microchip Technology Inc. DS70119B-page 88...
  • Page 91 I/O pin pair by clearing the appropriate PMODx bit in the resolution is effectively doubled. PWMCON1 SFR. The PWM I/O pins are set to Complementary mode by default upon a device Reset. Advance Information  2004 Microchip Technology Inc. DS70119B-page 89...
  • Page 92 Table 15-1 summarizes the function of each dead-time selection control bit. Note: The user should not modify the DTCON1 or DTCON2 values while the PWM mod- ule is operating (PTEN = 1). Unexpected results may occur. Advance Information  2004 Microchip Technology Inc. DS70119B-page 90...
  • Page 93 PTMR matches PTPER. ister is cleared, all active PWM I/O pins are driven to the inactive state, the PTEN bit is cleared, and an interrupt is generated. Advance Information  2004 Microchip Technology Inc. DS70119B-page 91...
  • Page 94 FAULT pin(s) could be software. used as general purpose interrupt pin(s). Each FAULT pin has an interrupt vector, Interrupt Flag bit and Interrupt Priority bits associated with it. Advance Information  2004 Microchip Technology Inc. DS70119B-page 92...
  • Page 95 PWM time base. The SEVTDIR control bit has no effect unless the PWM time base is configured for an Up/Down Counting mode. Advance Information  2004 Microchip Technology Inc. DS70119B-page 93...
  • Page 96 Advance Information DS70119B-page 94  2004 Microchip Technology Inc.

  • Page 97: Spi™ Module

    In Master mode, the clock is generated by prescaling the system clock. Data is transmitted as soon as a value is written to SPIxBUF. The interrupt is generated at the middle of the transfer of the last bit. Advance Information  2004 Microchip Technology Inc. DS70119B-page 95...
  • Page 98 Serial Input Buffer (SPIxBUF) (SPIyBUF) SDIx SDOy Shift Register Shift Register (SPIxSR) (SPIySR) Serial Clock SCKx SCKy PROCESSOR 1 PROCESSOR 2 Note: x = 1 or 2, y = 1 or 2. Advance Information  2004 Microchip Technology Inc. DS70119B-page 96...
  • Page 99 SPI module will stop or continue on Idle. If SPISIDL = 0, the module will continue to operate when the CPU enters Idle mode. If SPISIDL = 1, the module will stop when the CPU enters Idle mode. Advance Information  2004 Microchip Technology Inc. DS70119B-page 97...
  • Page 100 Advance Information DS70119B-page 98  2004 Microchip Technology Inc.

  • Page 101: I2C Module

    I2CRCV is the receive buffer, as shown in Figure 16-1. I2CTRN is the transmit register to which bytes are writ- ten during a transmit operation, as shown in Figure 16-2. Advance Information  2004 Microchip Technology Inc. DS70119B-page 99...
  • Page 102 Stop bit Detect Write Start, Restart, Stop bit Generate Read Collision Detect Write Acknowledge Read Generation Clock Stretching Write I2CTRN Shift Read Clock Reload Control Write I2CBRG BRG Down Counter Read Advance Information  2004 Microchip Technology Inc. DS70119B-page 100...
  • Page 103 Once addressed, the master can generate a Repeated Start, reset the high byte of the address and set the R_W bit without generating a Stop bit, thus initiating a slave transmit operation. Advance Information  2004 Microchip Technology Inc. DS70119B-page 101...
  • Page 104 This will prevent buffer overruns from occurring. bit, DISSLW, enables the user to disable slew rate con- trol, if desired. It is necessary to disable the slew rate control for 1 MHz mode. Advance Information  2004 Microchip Technology Inc. DS70119B-page 102...
  • Page 105 (7 bits) and the data direction bit. In this case, the data direction bit (R_W) is logic 0. Serial data is transmitted 8 bits at a time. After each byte is Advance Information  2004 Microchip Technology Inc. DS70119B-page 103...
  • Page 106 0. When the user services the bus colli- sion Interrupt Service Routine, and if the I C bus is free, the user can resume communication by asserting a Start condition. Advance Information  2004 Microchip Technology Inc. DS70119B-page 104...
  • Page 107 Advance Information  2004 Microchip Technology Inc. DS70119B-page 105...
  • Page 108 NOTES: Advance Information DS70119B-page 106  2004 Microchip Technology Inc.

  • Page 109: Universal Asynchronous Receiver Transmitter (Uart) Module

    UTXBRK Data Transmit Shift Register (UxTSR) ‘0’ (Start) UxTX ‘1’ (Stop) 16X Baud Clock Parity 16 Divider Parity from Baud Rate Generator Generator Control Signals Note: x = 1 or 2. Advance Information  2004 Microchip Technology Inc. DS70119B-page 107...
  • Page 110 Receive Shift Register UxRX (UxRSR) · Start bit Detect · Parity Check · Stop bit Detect 16 Divider · Shift Clock Generation · Wake Logic 16X Baud Clock from Baud Rate Generator UxRXIF Advance Information DS70119B-page 108  2004 Microchip Technology Inc.
  • Page 111 The default (Power-on) setting of the UART is 8 bits, no Power Saving mode. parity, 1 stop bit (typically represented as 8, N, 1). Advance Information  2004 Microchip Technology Inc. DS70119B-page 109...
  • Page 112 FIFO, and the PERR and (until the OERR bit is cleared in software or a Reset FERR values will be updated. occurs). The data held in UxRSR and UxRXREG remains valid. Advance Information DS70119B-page 110  2004 Microchip Technology Inc.
  • Page 113 Note that RIDLE goes high when / (16* 65536). the stop bit has not been received yet. With a full 16-bit baud rate generator, at 30 MIPs operation, the minimum baud rate achievable is 28.5 bps. Advance Information  2004 Microchip Technology Inc. DS70119B-page 111...
  • Page 114 Interrupt Select Mode bit (URXISEL) has no effect for this function. If the receive interrupt is enabled, then this will wake-up the device from Sleep. The UARTEN bit must be set in order to generate a wake-up interrupt. Advance Information DS70119B-page 112  2004 Microchip Technology Inc.
  • Page 115 Advance Information  2004 Microchip Technology Inc. DS70119B-page 113...
  • Page 116 NOTES: Advance Information  2004 Microchip Technology Inc. DS70119B-page 114...

  • Page 117: Can Module

    CAN bus is checked for errors and then matched protocol was designed to allow communications within against filters to see if it should be received and stored noisy environments. The dsPIC30F6010 has 2 CAN in one of the receive registers. modules.
  • Page 118 CRC Check CRC Generator State Machine Transmit Timing Bit Timing Logic Logic Generator CiTX CiRX Note 1: i = 1 or 2 refers to a particular CAN module (CAN1 or CAN2). Advance Information  2004 Microchip Technology Inc. DS70119B-page 116...
  • Page 119 OPMODE<2:0> bits (CiCTRL<7:5>) = ‘001’, that indi- cates whether the module successfully went into mod- ule disable mode. The I/O pins will revert to normal I/O function when the module is in the module disable mode. Advance Information  2004 Microchip Technology Inc. DS70119B-page 117...
  • Page 120 • Wake-up interrupt The CAN module has woken up from Disable Mode or the device has woken up from Sleep mode. Advance Information  2004 Microchip Technology Inc. DS70119B-page 118...
  • Page 121 TXREQ bit and the Start of Frame (SOF), ensuring that if the priority was changed, it is resolved correctly before the SOF occurs. When TXREQ is set, the TXABT (CiTXnCON<6>), TXLARB (CiTXnCON<5>) TXERR (CiTXnCON<4>) flag bits automatically cleared. Advance Information  2004 Microchip Technology Inc. DS70119B-page 119...
  • Page 122 1 µsec, corresponding to a maximum bit rate of 1 MHz. FIGURE 19-2: CAN BIT TIMING Input Signal Prop Phase Phase Sync Sync Segment Segment 1 Segment 2 Sample Point Advance Information  2004 Microchip Technology Inc. DS70119B-page 120...
  • Page 123 Phase2 Seg. The re-synchronization jump width is programmable between 1 T and 4 T The following requirement must be fulfilled while setting the SJW<1:0> bits: • Phase2 Seg > Synchronization Jump Width Advance Information  2004 Microchip Technology Inc. DS70119B-page 121...
  • Page 124 Advance Information DS70119B-page 122  2004 Microchip Technology Inc.
  • Page 125 Advance Information  2004 Microchip Technology Inc. DS70119B-page 123...
  • Page 126 Advance Information DS70119B-page 124  2004 Microchip Technology Inc.
  • Page 127 Advance Information  2004 Microchip Technology Inc. DS70119B-page 125...
  • Page 128 NOTES: Advance Information  2004 Microchip Technology Inc. DS70119B-page 126...

  • Page 129: 10-Bit High Speed Analog-To-Digital Converter (A/D) Module

    ADCON3 and ADCSSL registers, must not be written to while ADON = 1. This would lead to indeterminate results. The block diagram of the A/D module is shown in Figure 20-1. Advance Information  2004 Microchip Technology Inc. DS70119B-page 127...
  • Page 130 Conversion Logic AN10 16-word, 10-bit Dual Port Buffer CH1,CH2, CH3,CH0 AN11 Sample/Sequence sample Control input switches Input Mux Control AN10 AN10 AN11 AN11 AN12 AN12 AN13 AN13 AN14 AN14 AN15 AN15 Advance Information  2004 Microchip Technology Inc. DS70119B-page 128...
  • Page 131 The channels are then converted sequentially. Obvi- greater than the number of samples taken per interrupt, ously, if there is only 1 channel selected, the SIMSAM the higher numbered inputs are unused. bit is not applicable. Advance Information  2004 Microchip Technology Inc. DS70119B-page 129...
  • Page 132 These values violate the minimum required T time of 154 ns. For faster conversion times, the selection of another clock source is recommended. A/D cannot meet full accuracy with RC clock source and F > 20 MHz. Advance Information  2004 Microchip Technology Inc. DS70119B-page 130...
  • Page 133 = interconnect resistance = sampling switch HOLD = sample/hold capacitance (from DAC) Note: Values shown here are untested typical values, for reference only. Exact electrical specifications are to be determined. Advance Information  2004 Microchip Technology Inc. DS70119B-page 131...
  • Page 134 Signed Integer d09 d09 d09 d09 d09 d09 d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Integer d09 d08 d07 d06 d05 d04 d03 d02 d01 d00 Advance Information  2004 Microchip Technology Inc. DS70119B-page 132...
  • Page 135 Analog levels on any pin that is defined as a current at the pin. digital input (including the ANx pins), may cause the input buffer to consume current that exceeds the device specifications. Advance Information  2004 Microchip Technology Inc. DS70119B-page 133...
  • Page 136 Advance Information DS70119B-page 134  2004 Microchip Technology Inc.

  • Page 137: System Integration

    Note 1: dsPIC30F maximum operating frequency of 120 MHz must be met. 2: LP oscillator can be conveniently shared as system clock, as well as real-time clock for Timer1. 3: Requires external R and C. Frequency operation up to 4 MHz. Advance Information  2004 Microchip Technology Inc. DS70119B-page 135...
  • Page 138 Secondary 32 kHz LP Oscillator Oscillator SOSCI Stability Detector POST<1:0> Internal Fast RC Oscillator (FRC) Internal Low LPRC Power RC Oscillator (LPRC) Fail-Safe Clock FCKSM<1:0> Monitor (FSCM) Oscillator Trap to Timer1 Advance Information  2004 Microchip Technology Inc. DS70119B-page 136...
  • Page 139 Keeping the LP oscillator ON at all times allows for a the primary oscillator. fast switch to the 32 kHz system clock for lower power operation. Returning to the faster main oscillator will still require a start-up time. Advance Information  2004 Microchip Technology Inc. DS70119B-page 137...
  • Page 140 In the event of a clock failure, the WDT is unaffected - 4.5% 1101 and continues to run on the LPRC clock. - 6.0% 1100 - 7.5% 1011 - 9.0% 1010 - 10.5% 1001 - 12.0% 1000 Advance Information  2004 Microchip Technology Inc. DS70119B-page 138...
  • Page 141 • OSWEN: Control bit changes from a ‘0’ to a ‘1’ when a clock transition sequence is initiated. Clearing the OSWEN control bit will abort a clock transition in progress (used for hang-up situations). Advance Information  2004 Microchip Technology Inc. DS70119B-page 139...
  • Page 142 Q1 clock, and the PC will jump to selects the device clock source identified by the oscil- the Reset vector. lator configuration fuses. The timing for the SYSRST signal is shown in Figure 21-3 through Figure 21-5. Advance Information  2004 Microchip Technology Inc. DS70119B-page 140...
  • Page 143 OST TIME-OUT PWRT PWRT TIME-OUT INTERNAL Reset FIGURE 21-5: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO V ): CASE 2 MCLR INTERNAL POR OST TIME-OUT PWRT PWRT TIME-OUT INTERNAL Reset Advance Information  2004 Microchip Technology Inc. DS70119B-page 141...
  • Page 144 • 4.5V the MCP1XX and MCP8XX, may also be Note: The BOR voltage trip points indicated here used as an external Power-on Reset are nominal values provided for design circuit. guidance only. Advance Information  2004 Microchip Technology Inc. DS70119B-page 142...
  • Page 145 = unchanged, x = unknown, - = unimplemented bit, read as '0' Note 1: When the wake-up is due to an enabled interrupt, the PC is loaded with the corresponding interrupt vector. Advance Information  2004 Microchip Technology Inc. DS70119B-page 143...
  • Page 146 In order to have the small- est possible start-up delay when waking up from Sleep, one of these faster wake-up options should be selected before entering Sleep. Advance Information  2004 Microchip Technology Inc. DS70119B-page 144...
  • Page 147 CPU and instruction execution begins immedi- have been programmed, an erase of the ately, starting with the instruction following the PWRSAV entire code-protected device is only ≥ 4.5V. instruction. possible at voltages V Advance Information  2004 Microchip Technology Inc. DS70119B-page 145...
  • Page 148 EMUC3 is selected as the Debug I/O pin pair, then a 7-pin interface is required, as the EMUDx/EMUCx pin functions (x = 1, 2 or 3) are not multiplexed with the PGD and PGC pin functions. Advance Information  2004 Microchip Technology Inc. DS70119B-page 146...
  • Page 149 Advance Information  2004 Microchip Technology Inc. DS70119B-page 147...
  • Page 150 NOTES: Advance Information  2004 Microchip Technology Inc. DS70119B-page 148...

  • Page 151: Instruction Set Summary

    (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value, or indirectly by the contents of register ‘Wb’) Advance Information  2004 Microchip Technology Inc. DS70119B-page 149...
  • Page 152 DSP status bits: AccA Overflow, AccB Overflow, AccA Saturate, AccB Saturate OA, OB, SA, SB Program Counter 10-bit signed literal ∈ {-512...511} Slit10 16-bit signed literal ∈ {-32768...32767} Slit16 6-bit signed literal ∈ {-16...16} Slit6 Advance Information  2004 Microchip Technology Inc. DS70119B-page 150...
  • Page 153 Y data space pre-fetch address register for DSP instructions ∈ {[W10]+=6, [W10]+=4, [W10]+=2, [W10], [W10]-=6, [W10]-=4, [W10]-=2, [W11]+=6, [W11]+=4, [W11]+=2, [W11], [W11]-=6, [W11]-=4, [W11]-=2, [W11+W12], none} Y data space pre-fetch destination register for DSP instructions ∈ {W4..W7} Advance Information  2004 Microchip Technology Inc. DS70119B-page 151...
  • Page 154 Ws,#bit4 Bit Set Ws None BSW.C Ws,Wb Write C bit to Ws<Wb> None BSW.Z Ws,Wb Write Z bit to Ws<Wb> None f,#bit4 Bit Toggle f None Ws,#bit4 Bit Toggle Ws None Advance Information  2004 Microchip Technology Inc. DS70119B-page 152...
  • Page 155 WREG = f -1 C,DC,N,OV,Z Ws,Wd Wd = Ws - 1 C,DC,N,OV,Z DEC2 DEC2 f = f -2 C,DC,N,OV,Z DEC2 f,WREG WREG = f -2 C,DC,N,OV,Z DEC2 Ws,Wd Wd = Ws - 2 C,DC,N,OV,Z Advance Information  2004 Microchip Technology Inc. DS70119B-page 153...
  • Page 156 Pre-fetch and store accumulator None Wm*Wn,Acc,Wx,Wxd,Wy,Wyd Multiply Wm by Wn to Accumulator OA,OB,OAB, SA,SB,SAB Wm*Wm,Acc,Wx,Wxd,Wy,Wyd Square Wm to Accumulator OA,OB,OAB, SA,SB,SAB MPY.N MPY.N Wm*Wn,Acc,Wx,Wxd,Wy,Wyd -(Multiply Wm by Wn) to Accumulator None Advance Information  2004 Microchip Technology Inc. DS70119B-page 154...
  • Page 157 None SAC.R Acc,#Slit4,Wdo Store Rounded Accumulator None Ws,Wnd Wnd = sign extended Ws C,N,Z SETM SETM f = 0xFFFF None SETM WREG WREG = 0xFFFF None SETM Ws = 0xFFFF None Advance Information  2004 Microchip Technology Inc. DS70119B-page 155...
  • Page 158 = f .XOR. WREG f,WREG WREG = f .XOR. WREG #lit10,Wn Wd = lit10 .XOR. Wd Wb,Ws,Wd Wd = Wb .XOR. Ws Wb,#lit5,Wd Wd = Wb .XOR. lit5 Ws,Wnd Wnd = Zero-Extend Ws C,Z,N Advance Information  2004 Microchip Technology Inc. DS70119B-page 156...

  • Page 159: Development Support

    • Integration into MPLAB IDE projects • User defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process Advance Information  2004 Microchip Technology Inc. DS70119B-page 157...
  • Page 160 DSP dynamic memory allocation, data conversion, time- routines. keeping and math functions (trigonometric, exponential and hyperbolic). The compiler provides symbolic information for high-level source debugging with the MPLAB IDE. Advance Information  2004 Microchip Technology Inc. DS70119B-page 158...
  • Page 161 The PC platform and Microsoft Windows 32-bit operating system were chosen to best make these features available in a simple, unified application. Advance Information  2004 Microchip Technology Inc. DS70119B-page 159...
  • Page 162 Also included are: header for expansion, eight LEDs, four potentiometers, three push buttons and a proto- typing area. Included with the kit is a PIC16F627A and a PIC18F1320. Tutorial firmware is included along with the User’s Guide. Advance Information  2004 Microchip Technology Inc. DS70119B-page 160...
  • Page 163 “Tips 'n Tricks for 8-pin Flash ® Microcontrollers” Handbook and a USB interface cable. Supports all current 8/14-pin Flash PIC microcontrollers, as well as many future planned devices. Advance Information  2004 Microchip Technology Inc. DS70119B-page 161...
  • Page 164 NOTES: Advance Information  2004 Microchip Technology Inc. DS70119B-page 162...

  • Page 165: Electrical Characteristics

    Exposure to maximum rating conditions for extended periods may affect device reliability. Note: All peripheral electrical characteristics are specified. For exact peripherals available on specific devices, please refer the the Family Cross Reference Table. Advance Information  2004 Microchip Technology Inc. DS70119B-page 163...
  • Page 166 Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. These parameters are characterized but not tested in manufacturing. This is the limit to which V can be lowered without losing RAM data. Advance Information  2004 Microchip Technology Inc. DS70119B-page 164...
  • Page 167 All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. Advance Information  2004 Microchip Technology Inc. DS70119B-page 165...
  • Page 168 All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. Advance Information  2004 Microchip Technology Inc. DS70119B-page 166...
  • Page 169 All I/O pins are configured as Inputs and pulled to V MCLR = V , WDT, FSCM, LVD and BOR are disabled. CPU, SRAM, Program Memory and Data Memory are operational. No peripheral modules are operating. Advance Information  2004 Microchip Technology Inc. DS70119B-page 167...
  • Page 170 Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. IDLE Base I current is measured with Core off, Clock on and all modules turned off. Advance Information  2004 Microchip Technology Inc. DS70119B-page 168...
  • Page 171 Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. IDLE Base I current is measured with Core off, Clock on and all modules turned off. Advance Information  2004 Microchip Technology Inc. DS70119B-page 169...
  • Page 172 Data in “Typical” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base I IDLE current is measured with Core off, Clock on and all modules turned off. Advance Information  2004 Microchip Technology Inc. DS70119B-page 170...
  • Page 173 LVD, BOR, WDT, etc. are all switched off. The ∆ current is the additional current consumed when the module is enabled. This current should be added to the base I current. Advance Information  2004 Microchip Technology Inc. DS70119B-page 171...
  • Page 174 LVD, BOR, WDT, etc. are all switched off. The ∆ current is the additional current consumed when the module is enabled. This current should be added to the base I current. Advance Information  2004 Microchip Technology Inc. DS70119B-page 172...
  • Page 175 The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Advance Information  2004 Microchip Technology Inc. DS70119B-page 173...
  • Page 176 Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. These parameters are characterized but not tested in manufacturing. FIGURE 24-1: LOW-VOLTAGE DETECT CHARACTERISTICS LV10 LVDIF (LVDIF set by hardware) Advance Information  2004 Microchip Technology Inc. DS70119B-page 174...
  • Page 177 These parameters are characterized but not tested in manufacturing. These values not in usable operating range. FIGURE 24-2: BROWN-OUT RESET CHARACTERISTICS (Device not in Brown-out Reset) BO15 BO10 (Device in Brown-out Reset) RESET (due to BOR) Power Up Time-out Advance Information  2004 Microchip Technology Inc. DS70119B-page 175...
  • Page 178 — Row Erase D138 During Programming — Bulk Erase Note 1: Data in “Typ” column is at 5V, 25°C unless otherwise stated. These parameters are characterized but not tested in manufacturing. Advance Information  2004 Microchip Technology Inc. DS70119B-page 176...
  • Page 179 = 464 Ω = 50 pF for all pins except OSC2 5 pF for OSC2 output FIGURE 24-4: EXTERNAL CLOCK TIMING OSC1 OS20 OS30 OS30 OS31 OS31 OS25 CLKOUT OS40 OS41 Advance Information  2004 Microchip Technology Inc. DS70119B-page 177...
  • Page 180 Measurements are taken in EC or ERC modes. The CLKOUT signal is measured on the OSC2 pin. CLKOUT is low for the Q1-Q2 period (1/2 T ) and high for the Q3-Q4 period (1/2 T Advance Information  2004 Microchip Technology Inc. DS70119B-page 178...
  • Page 181 -40°C to +85°C = 5V Note 1: Frequency calibrated at 25°C. TUN bits can be used to compensate for temperature drift. LPRC frequency after calibration. Change of LPRC frequency as V changes. Advance Information  2004 Microchip Technology Inc. DS70119B-page 179...
  • Page 182 Measurements are taken in RC mode and EC mode where CLKOUT output is 4 x T These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 5V, 25°C unless otherwise stated. Advance Information  2004 Microchip Technology Inc. DS70119B-page 180...
  • Page 183 TIMER TIMING CHARACTERISTICS SY12 MCLR SY10 Internal SY11 PWRT Time-out SY30 Time-out Internal RESET Watchdog Timer RESET SY20 SY13 SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 24-3 for load conditions. Advance Information  2004 Microchip Technology Inc. DS70119B-page 181...
  • Page 184 RCON<13>Status bit Note 1: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 5V, 25°C unless otherwise stated. Advance Information  2004 Microchip Technology Inc. DS70119B-page 182...
  • Page 185 SOSC1/T1CK oscillator input — frequency range (oscillator enabled by setting bit TCS (T1CON, bit 1)) CKEXTMRL TA20 Delay from External TQCK Clock — Edge to Timer Increment Note: Timer1 is a Type A. Advance Information  2004 Microchip Technology Inc. DS70119B-page 183...
  • Page 186 (1, 8, 64, 256) Synchronous, Greater of: with prescaler 20 ns or + 40)/N CKEXTMRL TC20 Delay from External TQCK Clock — — Edge to Timer Increment Note: Timer3 and Timer5 are Type C. Advance Information  2004 Microchip Technology Inc. DS70119B-page 184...
  • Page 187 + 40 — — with prescaler CKEXTMRL TQ20 Delay from External TQCK Clock Tosc 5 Tosc — Edge to Timer Increment Note 1: These parameters are characterized but not tested in manufacturing. Advance Information  2004 Microchip Technology Inc. DS70119B-page 185...
  • Page 188 Note 1: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Advance Information  2004 Microchip Technology Inc. DS70119B-page 186...
  • Page 189 Note 1: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Advance Information  2004 Microchip Technology Inc. DS70119B-page 187...
  • Page 190 Note 1: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Advance Information  2004 Microchip Technology Inc. DS70119B-page 188...
  • Page 191 These parameters are characterized but not tested in manufacturing. N = Index Channel Digital Filter Clock Divide Select Bits. Refer to Section 16. “Quadrature Encoder Interface (QEI)” in the dsPIC30F Family Reference Manual. Advance Information  2004 Microchip Technology Inc. DS70119B-page 189...
  • Page 192 Alignment of Index Pulses to QEA and QEB is shown for Position Counter reset timing only. Shown for forward direction only (QEA leads QEB). Same timing applies for reverse direction (QEA lags QEB) but Index Pulse recognition occurs on falling edge. Advance Information  2004 Microchip Technology Inc. DS70119B-page 190...
  • Page 193 The minimum clock period for SCK is 100 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPI pins. Advance Information  2004 Microchip Technology Inc. DS70119B-page 191...
  • Page 194 The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. Assumes 50 pF load on all SPI pins. Advance Information  2004 Microchip Technology Inc. DS70119B-page 192...
  • Page 195 These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Assumes 50 pF load on all SPI pins. Advance Information  2004 Microchip Technology Inc. DS70119B-page 193...
  • Page 196 SP21 SP20 SP52 BIT14 - - - - - -1 SP30,SP31 SP51 MSb IN BIT14 - - - -1 LSb IN SP41 SP40 Note: Refer to Figure 24-3 for load conditions. Advance Information  2004 Microchip Technology Inc. DS70119B-page 194...
  • Page 197 The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. Assumes 50 pF load on all SPI pins. Advance Information  2004 Microchip Technology Inc. DS70119B-page 195...
  • Page 198 Note: Refer to Figure 24-3 for load conditions. FIGURE 24-22: C BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM21 IM11 IM10 IM11 IM26 IM10 IM33 IM25 IM45 IM40 IM40 Note: Refer to Figure 24-3 for load conditions. Advance Information  2004 Microchip Technology Inc. DS70119B-page 196...
  • Page 199 C Baud Rate Generator. Refer to Section 21 “Inter-Integrated Circuit™ (I C)” in the dsPIC30F Family Reference Manual. Maximum pin capacitance = 10 pF for all I C pins (for 1 MHz mode only). Advance Information  2004 Microchip Technology Inc. DS70119B-page 197...
  • Page 200 C BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) IS34 IS31 IS30 IS33 Start Stop Condition Condition FIGURE 24-24: C BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS21 IS11 IS10 IS30 IS26 IS31 IS33 IS25 IS45 IS40 IS40 Advance Information  2004 Microchip Technology Inc. DS70119B-page 198...
  • Page 201 µs 1 MHz mode — IS50 Bus Capacitive — — Loading Note 1: Maximum pin capacitance = 10 pF for all I C pins (for 1 MHz mode only). Advance Information  2004 Microchip Technology Inc. DS70119B-page 199...
  • Page 202 Note 1: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Advance Information  2004 Microchip Technology Inc. DS70119B-page 200...
  • Page 203 Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. Advance Information  2004 Microchip Technology Inc. DS70119B-page 201...
  • Page 204 Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. The A/D conversion result never decreases with an increase in the input voltage, and has no missing codes. Advance Information  2004 Microchip Technology Inc. DS70119B-page 202...
  • Page 205 3 - Software clears ADCON. SAMP to start conversion. 4 - Sampling ends, conversion sequence starts. 5 - Convert bit 9. 6 - Convert bit 8. 8 - Convert bit 0. 9 - One T for end of conversion. Advance Information  2004 Microchip Technology Inc. DS70119B-page 203...
  • Page 206 Family Reference Manual, Section 17. 8 - Sample for time specified by SAMC. 3 - Convert bit 9. SAMP is described in the dsPIC30F 4 - Convert bit 8. Family Reference Manual, Section 17. Advance Information  2004 Microchip Technology Inc. DS70119B-page 204...
  • Page 207 — — from A/D Off to A/D On Note 1: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. Advance Information  2004 Microchip Technology Inc. DS70119B-page 205...
  • Page 208 NOTES: Advance Information  2004 Microchip Technology Inc. DS70119B-page 206...

  • Page 209: Packaging Information

    Standard device marking consists of Microchip part number, year code, week code, and traceability code. For device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. Advance Information  2004 Microchip Technology Inc. DS70119B-page 207...
  • Page 210 § Significant Characteristic Notes: Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-026 Drawing No. C04-092 Advance Information  2004 Microchip Technology Inc. DS70119B-page 208...
  • Page 211 10-bit High Speed A/D Functional......128 16-bit Timer1 Module ..........57 Data Access from Program Memory Using Program 16-bit Timer4............... 68 Space Visibility ............22 16-bit Timer5............... 68 Data Accumulators and Adder/Subtractor ......16 Advance Information  2004 Microchip Technology Inc. DS70119B-page 211...
  • Page 212 Device Overview ..............5 Master Mode............. 196 Divide Support..............14 Slave Mode............198 DSP Engine................. 14 Bus Data Timing Requirements Multiplier..............16 Master Mode............. 197 dsPIC30F6010 Port Register Map ........55 Slave Mode............199 Advance Information  2004 Microchip Technology Inc. DS70119B-page 212...
  • Page 213 Timing Requirements ..........182 Operation Example ............. 33 PRO MATE II Universal Device Programmer ....159 Start and End Address..........33 Program Address Space............. 19 W Address Register Selection ........33 Construction ............... 20 Advance Information  2004 Microchip Technology Inc. DS70119B-page 213...
  • Page 214 Timer Operation During CPU Sleep Mode....81 16-bit Asynchronous Counter Mode ......57 Quadrature Decoder Timing Requirements ...... 189 16-bit Synchronous Counter Mode ......57 Quadrature Encoder Interface (QEI) Module ...... 79 16-bit Timer Mode............57 Advance Information  2004 Microchip Technology Inc. DS70119B-page 214...
  • Page 215 Time-out Sequence on Power-up Receive Buffer Overrun Error (OERR Bit) ..110 (MCLR Not Tied to V ), Case 1...... 141 Time-out Sequence on Power-up (MCLR Not Tied to V ), Case 2...... 141 Advance Information  2004 Microchip Technology Inc. DS70119B-page 215...
  • Page 216 UART2 Register Map ..........113 Watchdog Timer (WDT)..........135, 144 Unit ID Locations............... 135 Enabling and Disabling ..........144 Universal Asynchronous Receiver Transmitter Operation ..............144 Module (UART) ............107 WWW, On-Line Support ............4 Advance Information  2004 Microchip Technology Inc. DS70119B-page 216...

  • Page 217: On-Line Support

    • Microchip Consultant Program Member Listing • Links to other useful web sites related to Microchip Products • Conferences for products, Development Systems, technical information and more • Listing of seminars and events Advance Information  2004 Microchip Technology Inc. DS70119B-page 217...

  • Page 218: Reader Response

    5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? Advance Information  2004 Microchip Technology Inc. DS70119B-page 218...

  • Page 219: Product Identification System

    9 = 769K and Up 20 = 20 MIPS 30 = 30 MIPS Device ID T = Tape and Reel A,B,C… = Revision Level Example: dsPIC30F6010AT-30I/PF = 30 MIPS, Industrial temp., TQFP package, Rev. A Advance Information  2004 Microchip Technology Inc. DS70119B-page 219...
  • Page 220 NOTES: Advance Information  2004 Microchip Technology Inc. DS70119B-page 220...
  • Page 221 NOTES: Advance Information  2004 Microchip Technology Inc. DS70119B-page 221...
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