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Microchip Technology PL360 Manual

Microchip Technology PL360 Manual

Host controller
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Introduction

The PL360 is a multi-protocol modem for the Power Line Communication (PLC) device, implementing a
very flexible architecture and allowing the implementation of standard and customized PLC solutions. It
has been conceived to be bundled with an external Microchip MCU, which downloads the corresponding
PLC firmware and controls the operation of the PL360 device.
The purpose of the PL360 Host Controller is to provide the external microcontroller a way to control the
PL360 device and offer upper layers an easy way to get access to PLC communication.
As an example of the PLC system, the figure below shows the system architecture for G3 protocol based
on a PL360 device being controlled by a SAM4C MCU.
Figure 1. G3 System Architecture
The aim of this document is to clarify and detail the user interface of the PL360 Host Controller.
©
2018 Microchip Technology Inc.
PL360 Host Controller
USER APPLICATION
IPv6 STACK
G3-PLC Stack
Adaptation Layer
( IETF RFC 4944 )
MAC Layer
( IEEE 802.15.4 )
PAL Layer
( ITU-T G.9903 )
Host Controller
PHY + PLC Transceiver
PLC
User Guide
app_if
adp_if
mac_if
phy_if
sniffer_if
SPI
PL360
PL360
50002738B-page 1

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Summary of Contents for Microchip Technology PL360

  • Page 1: Introduction

    PLC firmware and controls the operation of the PL360 device. The purpose of the PL360 Host Controller is to provide the external microcontroller a way to control the PL360 device and offer upper layers an easy way to get access to PLC communication.

  • Page 2: Features

    PL360 Features • Compliant with PRIME 1.3 Physical Layer • Compliant with PRIME 1.4 Physical Layer • Compliant with G3 Physical Layer • SPI Interface • Secure Boot Option User Guide 50002738B-page 2 © 2018 Microchip Technology Inc.

  • Page 3: Table Of Contents

    Table of Contents Introduction........................1 Features.......................... 2 1. PL360 Host Controller Architecture................5 1.1. PL360 Host Controller File Structure....................5 1.2. PLC Application Interface (API)....................6 1.3. PLC Stack Wrapper........................6 1.4. Add-ons............................7 1.5. Bootloader............................ 7 1.6. Hardware Abstraction Layer (HAL)....................7 2. PL360 System Architecture..................8 2.1.
  • Page 4 Supported Boards........................35 9.4. Platform Porting..........................35 10. Abbreviations......................36 11. References......................38 12. Appendix A: PL360 Host Controller API..............39 12.1. Common PHY API........................39 12.2. G3 PHY API..........................42 12.3. PRIME PHY SAP........................59 13. Appendix B: ZC Offset Configuration..............74 14.

  • Page 5: Pl360 Host Controller Architecture

    API of the Power Line Communications PHY layer running in the PL360 device. Figure 1-1 shows the architecture of the software which runs on the host MCU. The components of the PL360 Host Controller are described in the following subsections.

  • Page 6: Plc Application Interface (Api)

    This module provides an interface to the application for all PLC operations. This API includes the following services: • Set custom hardware interface • Manage Bootloader process of the PL360 device • Manage external configuration of the PL360 device • Enable / Disable PLC interface •...

  • Page 7: Add-Ons

    Sniffer PC tool, and another one to connect with the Microchip PLC PHY Tester PC tool. Bootloader The PL360 device is a RAM-based device, so it is required to transfer the binary code to the device after each reset. The main purpose of this module is to manage the download process.

  • Page 8: Pl360 System Architecture

    Cortex M7 CPU to run the PLC firmware. This firmware can either implement the G3 or the PRIME Physical layer depending on what has been loaded by the PL360 Host Controller. The components of the system are described in the following subsections.

  • Page 9: Pl360 Memory

    • Host Interface: This block is in charge of managing the communication with the PL360 Host Controller through SPI. It is responsible for parsing/serializing the SPI data, managing PLC data regions and providing control on PLC Interruption PIO •...

  • Page 10: Phy Host Application

    PHY Utils: This block contains several functionalities used by the TX/RX chains PHY Host Application The PHY Host Application is responsible for running the main application of the PL360 device. It is in charge of initializing the hardware and clock systems, checking the watchdog timer and managing the PL360 PLC service described in the previous chapter.

  • Page 11: Brief About Asf

    For details on ASF please refer to Advanced Software Framework documentation: • Advanced Software Framework - Website • [PDF] Atmel AVR4029: Atmel Software Framework - Getting Started • [PDF] Atmel AVR4030: Atmel Software Framework - Reference Manual User Guide 50002738B-page 11 © 2018 Microchip Technology Inc.

  • Page 12: Initialization Example

    This chapter aims to explain the different steps required during the initialization phase of the system. After powering up the PL360 device, a set of initialization sequences must be executed in the correct order for the proper operation of the PL360 device.

  • Page 13: Enable Controller

    • Disable/enable PLC interrupt and component • Transfer the PL360 firmware to the PL360 device and validate. In case of failure, report a critical error in host communication with the PL360 device through exception callback PLC Event Handling Once the controller callbacks have been set up, the PL360 Host Controller component must be enabled.

  • Page 14: Code Example

    /* Enable ATPL360 */ uc_ret = atpl360_enable(ATPL360_BINARY_ADDRESS, ATPL360_BINARY_LEN); if (uc_ret == ATPL360_ERROR) { printf("\r\nmain: atpl360_enable call error!(%d)\r\n", uc_ret); while (1) { while (1) { /* Check ATPL360 pending events */ atpl360_handle_events(); User Guide 50002738B-page 14 © 2018 Microchip Technology Inc.

  • Page 15: Configuration

    Configuration Configuration The PL360 firmware has a set of configurable parameters that control its behavior. There is a set of configuration APIs provided to the host MCU application to configure these parameters. The configuration APIs are categorized according to their functionality: application, coupling parameters and secure mode.

  • Page 16: Configure Secure Mode

    During startup, the PL360 Host Controller verifies that the firmware is running in the PL360 device and sets custom coupling parameters through the atpl360_comm_set_coup_cfg function in the API, which should be adapted by customers depending on their hardware requirements.

  • Page 17: Host Interface Management

    Controller to the PL360 device. Figure 6-1. Sequence of Message Transmission Message Reception The following figure shows the steps involved in the reception of a message from the PL360 device to the PL360 Host Controller. Figure 6-2. Sequence of Message Reception User Guide 50002738B-page 17 ©...

  • Page 18: Spi Protocol

    SPI Protocol SPI Protocol The main interface of the PL360 device is the SPI. The PL360 device employs a protocol to allow the exchange of formatted data with the PL360 Host Controller. The PL360 SPI protocol uses raw bytes exchanged on the SPI bus to form high level structures like requests and callbacks.

  • Page 19: Firmware Command Format

    SPI Protocol The header field is formed by the first 15 bits and it contains the boot signature data (0b010101100011010). This data is fixed by the PL360 device and it is used to identify the status of the PL360 device.

  • Page 20: Firmware Response Format

    The following frame format is used for firmware responses. Figure 7-3. Firmware Response Fields The header field contains the firmware signature data (0x1122). This field is fixed by the PL360 embedded firmware and is used to check if this firmware runs properly.
  • Page 21 In case of G3, only one message can be queued. In case of PRIME, two transmission messages can be queued simultaneously. This is possible because there are two transmission buffers defined in the PRIME PL360 embedded firmware, TX0 and TX1.

  • Page 22: Message Flow For Basic Transactions

    In a message transmission, there are 2 SPI blocks. The first one is relative to the transmission of G3 parameters of the message, the second one is relative to the data part of the same message. Figure 7-4. G3 Send Message SPI Sequence User Guide 50002738B-page 22 © 2018 Microchip Technology Inc.
  • Page 23 G3: Read TX confirm Information When message transmission is complete, the PL360 device reports the status of the last transmission. For that purpose, IRQ is used to notify the PL360 Host Controller that an event has occurred. User Guide 50002738B-page 23 ©...
  • Page 24 IRQ is used to notify of PL360 events • First SPI transaction corresponds to the retrieval of event information from the PL360 device • Second SPI transaction corresponds to the retrieval of confirmation data from the PL360 device (if needed) 7.6.2.1 Get Events Information Figure 7-8. G3 Get Events Information SPI Array...
  • Page 25 IRQ 1: Get data part of the message (two transactions): – Get Events Information – Get Data • IRQ 2: Get parameters part of the message (two transactions): – Get Events Information User Guide 50002738B-page 25 © 2018 Microchip Technology Inc.
  • Page 26 Get Parameters 7.6.3.1 Get Events Information and Data Figure 7-11. G3 Get Events Information and Data SPI Arrays If IRQ occurs (enabled in low), it is first needed to read events reported by the PL360 device. • Master (MOSI): – Send ID memory region(16 bits): 0x0000 (ATPL360_STATUS_INFO_ID) –...
  • Page 27 SPI Protocol 7.6.3.2 Get Events Information and Parameters Figure 7-12. G3 Get Events Information and Parameters SPI Arrays If IRQ occurs (enabled in low), first it is needed to read events reported by the PL360 device. • Master (MOSI): – Send ID memory region(16 bits): 0x0000 (ATPL360_STATUS_INFO_ID) –...
  • Page 28 PRIME: Read TX confirm Information (Buffer 0) When message transmission is complete, the PL360 device reports the status of the last transmission. For that purpose, IRQ is used to notify the PL360 Host Controller that an event has occurred. Figure 7-14. PRIME TX Confirm Information SPI Sequence In the figure above, the following can be seen: •...
  • Page 29 SPI Protocol It is similar to the flow described in section 7.6.2.1 Get Events Information, but changing the firmware descriptors for the ones applicable to the PRIME PL360 firmware. 7.6.5.2 Get Confirmation Data (Buffer 0) Figure 7-16. PRIME Confirmation Data SPI Array It is similar to the flow described in section 7.6.2.2 Get Confirmation...
  • Page 30 It is similar to the flow described in section 7.6.3.2 Get Events Information and Parameters, but changing the firmware descriptors for the ones applicable to the PRIME PL360 firmware. 7.6.7 Read Register Information It is possible to get internal information from the PL360 device.
  • Page 31 Access (G3) 12.3.4 PIB Objects Specification and Access (PRIME) – Send length of the register to read (2 bytes) • Slave (MISO): PL360 device responds with firmware header (0x1122) 7.6.7.2 Get Events Information Figure 7-23. Get Events Information Array • Master (MOSI): –...
  • Page 32 Send Firmware Header (16 bits): 0x1122 – Send Firmware Events (16 bits): 0x008 (ATPL360_REG_RSP_MASK) – Send Firmware register value. See section 12.2.5 PIB Objects Specification and Access (G3) 12.3.4 PIB Objects Specification and Access (PRIME) User Guide 50002738B-page 32 © 2018 Microchip Technology Inc.

  • Page 33: Example Applications

    PL360 Host Controller. In addition, PHY examples using only the PL360 Host Controller are provided in order to evaluate some low level parameters and to be used together with a Microchip PLC tool for demonstration purposes.
  • Page 34 PL360 Example Applications This example uses the serial interface configured through UART0 at 921600bps. User Guide 50002738B-page 34 © 2018 Microchip Technology Inc.

  • Page 35: Supported Platforms

    PL360 Supported Platforms Supported Platforms This chapter describes which hardware platforms are currently supported with the PL360 Host Controller source code. Usually, a platform usually is comprised of three major components: • An MCU • A transceiver chip • A specific board or even several boards that contain the MCU or the transceiver chip Supported MCU Families Platforms based in SAM4C family MCUs.

  • Page 36: Abbreviations

    Master Output Salve Input Platform Abstraction Layer Protocol Data Unit Programmable-Gain Amplifier Physical Layer PLC Information Base Power Line Communication Serial Peripheral Interface Read Root Raised Cosine Reed Solomon RSSI Received Signal Strength Indication User Guide 50002738B-page 36 © 2018 Microchip Technology Inc.
  • Page 37 PL360 Abbreviations Reception Signal to Noise Ratio Transmission Write User Guide 50002738B-page 37 © 2018 Microchip Technology Inc.

  • Page 38: References

    Microchip Power Line Communications: http://www.microchip.com/design-centers/smart-energy-products/ power-line-communications/overview Microchip Design Support: http://www.microchip.com/support/hottopics.aspx G3-PLC Alliance: http://www.g3-plc.com/ PRIME Alliance: http://www.prime-alliance.org/ PL360-EK User Guide, 2018 PL360 Datasheet, 2018 Advanced Software Framework: http://www.microchip.com/avr-support/advanced-software-framework- (asf) Atmel Studio: http://www.microchip.com/avr-support/atmel-studio-7 Documents for supported families and boards: http://asf.atmel.com/docs/latest/ User Guide 50002738B-page 38 ©...

  • Page 39: Appendix A: Pl360 Host Controller Api

    Initializes the PLC SPI service • And, if necessary, initializes add-on interfaces The component descriptor offers the customer a set of functions to get access to the PL360 device. It is defined as a structure of function pointers as follows: typedef struct atpl360_descriptor { pf_set_callbacks_t set_callbacks;...
  • Page 40 • PRIME. Refer to hal_plc.c/.h files. They are located in asf.thirdparty.prime_ng.hal path 12.1.2 Setting Callbacks The user can set their own callbacks using the following function pointer defined in the PL360 Host Controller descriptor: typedef void (*pf_set_callbacks_t)(atpl360_dev_callbacks_t *dev_cb); Parameters: atpl360_dev_callbacks_t...
  • Page 41 ATPL360_EXCEPTION_RESET, /* Reset device */ } atpl360_exception_t; Tip:  SPI critical error means that the PL360 firmware cannot be loaded into the PL360 device. A possible reason for this would be that the SPI is not working properly. 12.1.3 Enable Function...

  • Page 42: G3 Phy Api

    PL360 Appendix A: PL360 Host Controller API And then, it triggers the corresponding PL360 Host Controller callbacks. 12.1.6 Management Primitives 12.1.6.1 Set Configuration This is done by means of a specific function provided by the controller descriptor: typedef bool (*pf_mng_set_cfg_t)(uint16_t us_param_id, void *px_value, uint8_t uc_len);...
  • Page 43 PL360 Appendix A: PL360 Host Controller API 12.2.2 PHY-DATA.request This function sends a frame using the PHY layer. This is done by means of a specific function provided by the controller descriptor: typedef uint8_t (*pf_send_data_t)(tx_msg_t *px_msg); The input parameter structure is the following: typedef struct tx_msg { uint8_t *puc_data_buf;...
  • Page 44 PL360 Appendix A: PL360 Host Controller API #define TX_MODE_SYMBOLS_CONTINUOUS (1 << 3) /* ! TX Mode: Cancel transmission */ #define TX_MODE_CANCEL (1 << 4) /* Modulation types */ enum mod_types { MOD_TYPE_BPSK = 0, MOD_TYPE_QPSK = 1, MOD_TYPE_8PSK = 2,...
  • Page 45 /* No transmission ongoing */ 12.2.3 PHY-DATA.confirm This data confirm callback executes the function set by the upper layer at the initialization of the PL360 Host Controller. The pointer to the function is set in: typedef void (*pf_data_confirm_t)(tx_cfm_t *px_msg_cfm); The result is reported in the following structure: typedef struct tx_cfm { uint32_t ul_rms_calc;...
  • Page 46 PL360 Appendix A: PL360 Host Controller API int16_t ss_snr_fch; int16_t ss_snr_pay uint16_t us_payload_corrupted_carriers; uint16_t us_payload_noised_symbols; uint8_t uc_payload_snr_worst_carrier; uint8_t uc_payload_snr_worst_symbol; uint8_t uc_payload_snr_impulsive; uint8_t uc_payload_snr_be; uint8_t uc_payload_snr_background; uint8_t uc_lqi; enum delimiter_types uc_delimiter_type; uint8_t uc_rsrv0; uint8_t puc_tone_map[TONE_MAP_SIZE_MAX]; uint8_t puc_carrier_snr[PROTOCOL_CARRIERS_MAX]; uint8_t uc_rsrv1; uint8_t *puc_data_buf;...
  • Page 47 Access: Read-only. Value Range: 2 bytes. Default Value: 0x0002. 12.2.5.3 ATPL360_HOST_PHY_ID (0x010C) Physical identification number of the PL360 Host Controller. It is composed of ATPL360_HOST_VERSION_ID (0x0112) + ATPL360_HOST_BAND_ID (0x0116). Access: Read-only. Value Range: 4 bytes. Default Value: 0x36010201 for CENELEC A band. 0x36010202 for FCC band. 0x36010203 for ARIB band.
  • Page 48 Access: Read-only. Value Range: 2 bytes. Default Value: 0x3601. 12.2.5.10 ATPL360_REG_VERSION_STR (0x4002) Version number of PL360 embedded firmware in string format. The format is "AA.BB.CC.DD", where: • AA: Corresponds to device model ("36") • BB: Corresponds to G3 band ["01": CEN A, "02": FCC, "03": ARIB, "04": CEN B] •...
  • Page 49 PL360 Appendix A: PL360 Host Controller API 12.2.5.11 ATPL360_REG_VERSION_NUM (0x4003) Version number of PL360 embedded firmware in hexadecimal format. The format is 0xAABBCCDD, where: • AA: Corresponds to device model (0x36) • BB: Corresponds to G3 band [0x01: CEN A, 0x02: FCC, 0x03: ARIB, 0x04: CEN B] •...
  • Page 50 Access: Read-write. Value Range: 4 bytes. Default Value: 0. 12.2.5.17 ATPL360_REG_TX_BAD_BUSY_TX (0x4009) Number of times when the PL360 device received new data to transmit (send_data) and there is already data in the TX chain. Access: Read-write. Value Range: 4 bytes.
  • Page 51 PL360 Appendix A: PL360 Host Controller API Value Range: 4 bytes. Default Value: 0. 12.2.5.22 ATPL360_REG_RX_TOTAL (0x400E) Number of successfully received PDUs. Access: Read-write. Value Range: 4 bytes. Default Value: 0. 12.2.5.23 ATPL360_REG_RX_TOTAL_BYTES (0x400F) Number of bytes in successfully received PDUs.
  • Page 52 PL360 Appendix A: PL360 Host Controller API Default Value: 0. 12.2.5.29 ATPL360_REG_RX_BAD_FORMAT (0x4015) Number of errors in modulation type field included in FCH of received PDUs. Access: Read-write. Value Range: 4 bytes. Default Value: 0. 12.2.5.30 ATPL360_REG_ENABLE_AUTO_NOISE_CAPTURE (0x4016) Flag to indicate if automatic noise analyzer is enabled in the reception chain. If Automatic mode is enabled, notch filter parameters (12.2.5.33 ATPL360_REG_RRC_NOTCH_ACTIVE...
  • Page 53 PL360 Appendix A: PL360 Host Controller API • 1 (Auto-mode): Read-only • 0 (Manual-mode): Read-write Value Range: 1 byte. [0: OFF, 1-5: ON]. Default Value: 0. 12.2.5.34 ATPL360_REG_RRC_NOTCH_INDEX (0x401A) Array of RRC notch filter index values in format unsigned Q7.8. The 7 integer bits indicate the carrier index (0 –127) for which the notch filter is applied.
  • Page 54 PL360 Appendix A: PL360 Host Controller API 12.2.5.38 ATPL360_REG_ZC_PERIOD (0x4020) Estimated last Zero Cross period. Access: Read-only. Value Range: 4 bytes. Default Value: Not applicable. 12.2.5.39 ATPL360_REG_FCH_SYMBOLS (0x4021) Number of symbols in Frame Control Header. Access: Read-only. Value Range: 1 byte.
  • Page 55 PL360 Appendix A: PL360 Host Controller API Value Range: 32 bytes. Default Value: Provided in atpl360_coup_cfg.h file. 12.2.5.45 ATPL360_REG_THRESHOLDS_TABLE_HI (0x4027) Values of thresholds table in HIGH impedance status. (Refer to section 5.2 Configure Coupling Parameters). Access: Read-write. Value Range: 64 bytes.
  • Page 56 Access: Read-write. Value Range: 68 bytes. Default Value: Provided in atpl360_coup_cfg.h file. 12.2.5.55 ATPL360_REG_NUM_TX_LEVELS (0x4032) Number of transmission levels to use in the PL360 firmware. Access: Read-write. Value Range: 1 byte. Default Value: Provided in atpl360_coup_cfg.h file. 12.2.5.56 ATPL360_REG_CORRECTED_RMS_CALC (0x4033) RMS value obtained compensated with gain applied by AGC algorithm.
  • Page 57 PL360 Appendix A: PL360 Host Controller API Value Range: 2 bytes. Default Value: 270 (67.5 dBμV). 12.2.5.58 ATPL360_REG_RRC_NOTCH_THR_OFF (0x4035) Deactivation threshold for narrow band noise (in dBμV quarters, uQ14.2). Access: Read-write. Value Range: 2 bytes. Default Value: 254 (63.5 dBμV).
  • Page 58 Default Value: Not applicable. 12.2.5.64 ATPL360_REG_SYNC_XCORR_THRESHOLD (0x403B) Correlation threshold for synchronization (preamble detection). The format is uQ0.16. It represents percentage with respect to the maximum ideal value of correlation (computed internally in PL360). Access: Read-write. Value Range: 2 bytes. Default value: 0x7400 (45.3%).

  • Page 59: Prime Phy Sap

    PL360 Appendix A: PL360 Host Controller API 12.2.5.68 ATPL360_REG_PPM_CALIB_ON (0x403F) Enable the oscillator clock signal to go out by TXRX1 pad. This is useful to measure clock frequency deviation. Access: Read-write. Value Range: 1 byte [0: Disabled, 1: Enabled]. Default value: 0.
  • Page 60 PL360 Appendix A: PL360 Host Controller API uc_buffer_id Identificator of the buffer used for transmitting uc_rsvd Reserved field for future use *puc_data_buf Pointer to data buffer Related constants affecting above parameters: /* ! \name TX Mode Bit Mask */ /* ! TX Mode: Absolute transmission */ #define TX_MODE_ABSOLUTE (0 <<...
  • Page 61 Appendix A: PL360 Host Controller API 12.3.2 PHY-DATA.confirm This data confirm callback executes the function set by the upper layer at the initialization of the PL360 Host Controller. The pointer to the function is set in: typedef void (*pf_data_confirm_t)(tx_cfm_t *px_msg_cfm);...
  • Page 62 Access: Read-only. Value Range: 10 bytes. Default Value: “SAM4CMS16C” (for SAM4CMS16_0 core) or “SAM4C16C” (for SAM4C16_0 core). 12.3.4.2 ATPL360_HOST_MODEL_ID (0x010A) Model identification number of the PL360 Host Controller. Access: Read-only. Value Range: 2 bytes. Default Value: 0x0002. 12.3.4.3 ATPL360_HOST_PRODUCT_ID (0x0110) Product identification number of the PL360 Host Controller.
  • Page 63 PL360 Appendix A: PL360 Host Controller API Default Value: 0x36000200. 12.3.4.5 ATPL360_TIME_REF (0x0200) Time reference in microseconds from the last reset of the PL360 device. Access: Read-only. Value Range: 4 bytes. Default Value: Not applicable. 12.3.4.6 ATPL360_REG_PRODID (0x4000) Product Identifier of firmware embedded in PL360 device.
  • Page 64 PL360 Appendix A: PL360 Host Controller API Value Range: 1 byte [0: OFF, 1: ON, 2: only FW AGC enabled] Default Value: 0. 12.3.4.11 ATPL360_REG_CFG_IMPEDANCE (0x4005) Impedance setting configured in transmission branch. Access: Read-write. Value Range: 1 byte [0: HIGH, 1: LOW, 2: VERY_LOW] Default Value: 2.
  • Page 65 PL360 Appendix A: PL360 Host Controller API Access: Read-write. Value Range: 64 bytes. Default Value: Provided in atpl360_coup_cfg.h file. 12.3.4.18 ATPL360_REG_THRESHOLDS_TABLE_LO (0x400D) Values of thresholds table in LOW impedance status. (Refer to section 5.2 Configure Coupling Parameters). Access: Read-write. Value Range: 64 bytes.
  • Page 66 Access: Read-write. Value Range: 68 bytes. Default Value: Provided in atpl360_coup_cfg.h file. 12.3.4.27 ATPL360_REG_CHANNEL_CFG (0x4016) Number of channel used in transmission and reception in the PL360 device. Channels permitted range from 1 to 8. Access: Read-write. Value Range: 1 byte.
  • Page 67 Mode – Time Mode: 0: Start time in absolute mode, 1: Start time in relative mode. In any case, time is always relative to PL360 internal timer reference. – Band Mode: 0: Channel mode, 1: FCC band mode User Guide 50002738B-page 67 ©...
  • Page 68 Channel [Only valid if Band Mode = 0]: Select channel to capture from 1 to 8 • Start Time: Start time in microseconds referenced to PL360 internal timer • Duration: Duration time in microseconds. Maximum duration depends on the selected Band Mode.
  • Page 69 PL360 Appendix A: PL360 Host Controller API 12.3.4.39 ATPL360_REG_TIME_BETWEEN_NOISE_CAPTURES (0x4022) Time in milliseconds between noise captures. Access: Read-write. Value Range: 4 bytes. Default Value: 1000 (1 second). It is recommended to keep the default value of this parameter. If reduced, the power CAUTION consumption could increase.
  • Page 70 PL360 Appendix A: PL360 Host Controller API • Channel 4, INDEX = 16 (0x0010): F = 16 * k + 65429.6875 + 3 * 54687.5 = 229553 Hz Access: Depends on 12.2.5.30 ATPL360_REG_ENABLE_AUTO_NOISE_CAPTURE (0x4016) value: • 1 (Auto-mode): Read-only •...
  • Page 71 Access: Read-write. Value Range: 4 bytes. Default Value: 0. 12.3.4.50 ATPL360_REG_TX_BAD_BUSY_TX (0x402D) Number of times when the PL360 device received new data to transmit (send_data) and there is already data in the TX chain. Access: Read-write. Value Range: 4 bytes.
  • Page 72 PL360 Appendix A: PL360 Host Controller API Default Value: 0. 12.3.4.55 ATPL360_REG_RX_TOTAL (0x4032) Number of successfully received PDUs. Access: Read-write. Value Range: 4 bytes. Default Value: 0. 12.3.4.56 ATPL360_REG_RX_TOTAL_BYTES (0x4033) Number of bytes in successfully received PDUs. Access: Read-write. Value Range: 4 bytes.
  • Page 73 PL360 Appendix A: PL360 Host Controller API 12.3.4.62 ATPL360_REG_NOISE_PER_CARRIER (0x4039) Estimation of noise (in dBµV) in each carrier belonging to the corresponding band. It is measured every time a noise capture is executed (see 12.3.4.38 ATPL360_REG_ENABLE_AUTO_NOISE_CAPTURE (0x4021), 12.3.4.39 ATPL360_REG_TIME_BETWEEN_NOISE_CAPTURES (0x4022), 12.3.4.44...

  • Page 74: Appendix B: Zc Offset Configuration

    The PHY layer calculates the electrical phase difference between transmitter and receiver for a given frame. To do so, both devices have to be able to read the Zero Cross time of the mains. The PL360 device has a dedicated input pin to be connected to a signal which provides such mains zero cross.

  • Page 75: Revision History

    12.2.5.63 Added sections 12.2.5.64 12.2.5.65 12.2.5.66 12.2.5.67 12.2.5.68 12.2.5.69 12.3.4 PIB Objects Specification and Access Updated sections 12.3.4.38 12.3.4.39 (PRIME) 12.3.4.40 12.3.4.41 12.3.4.42 12.3.4.43 12.3.4.44 12.3.4.45 12.3.4.46 12.3.4.62 Added section 12.3.4.63 User Guide 50002738B-page 75 © 2018 Microchip Technology Inc.

  • Page 76: The Microchip Web Site

    Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. User Guide 50002738B-page 76 © 2018 Microchip Technology Inc.

  • Page 77: Legal Notice

    SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries.

  • Page 78: Quality Management System Certified By Dnv

    PL360 © 2018, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN: 978-1-5224-3623-2 Quality Management System Certified by DNV ISO/TS 16949 Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California ®...

  • Page 79: Worldwide Sales And Service

    New York, NY Sweden - Stockholm Tel: 631-435-6000 Tel: 46-8-5090-4654 San Jose, CA UK - Wokingham Tel: 408-735-9110 Tel: 44-118-921-5800 Tel: 408-436-4270 Fax: 44-118-921-5820 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078 User Guide 50002738B-page 79 © 2018 Microchip Technology Inc.

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